svm.c revision 276403
1/*- 2 * Copyright (c) 2013, Anish Gupta (akgupt3@gmail.com) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/amd64/vmm/amd/svm.c 276403 2014-12-30 08:24:14Z neel $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/smp.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/pcpu.h> 36#include <sys/proc.h> 37#include <sys/sysctl.h> 38 39#include <vm/vm.h> 40#include <vm/pmap.h> 41 42#include <machine/cpufunc.h> 43#include <machine/psl.h> 44#include <machine/pmap.h> 45#include <machine/md_var.h> 46#include <machine/specialreg.h> 47#include <machine/smp.h> 48#include <machine/vmm.h> 49#include <machine/vmm_dev.h> 50#include <machine/vmm_instruction_emul.h> 51 52#include "vmm_lapic.h" 53#include "vmm_stat.h" 54#include "vmm_ktr.h" 55#include "vmm_ioport.h" 56#include "vatpic.h" 57#include "vlapic.h" 58#include "vlapic_priv.h" 59 60#include "x86.h" 61#include "vmcb.h" 62#include "svm.h" 63#include "svm_softc.h" 64#include "svm_msr.h" 65#include "npt.h" 66 67SYSCTL_DECL(_hw_vmm); 68SYSCTL_NODE(_hw_vmm, OID_AUTO, svm, CTLFLAG_RW, NULL, NULL); 69 70/* 71 * SVM CPUID function 0x8000_000A, edx bit decoding. 72 */ 73#define AMD_CPUID_SVM_NP BIT(0) /* Nested paging or RVI */ 74#define AMD_CPUID_SVM_LBR BIT(1) /* Last branch virtualization */ 75#define AMD_CPUID_SVM_SVML BIT(2) /* SVM lock */ 76#define AMD_CPUID_SVM_NRIP_SAVE BIT(3) /* Next RIP is saved */ 77#define AMD_CPUID_SVM_TSC_RATE BIT(4) /* TSC rate control. */ 78#define AMD_CPUID_SVM_VMCB_CLEAN BIT(5) /* VMCB state caching */ 79#define AMD_CPUID_SVM_FLUSH_BY_ASID BIT(6) /* Flush by ASID */ 80#define AMD_CPUID_SVM_DECODE_ASSIST BIT(7) /* Decode assist */ 81#define AMD_CPUID_SVM_PAUSE_INC BIT(10) /* Pause intercept filter. */ 82#define AMD_CPUID_SVM_PAUSE_FTH BIT(12) /* Pause filter threshold */ 83 84#define VMCB_CACHE_DEFAULT (VMCB_CACHE_ASID | \ 85 VMCB_CACHE_IOPM | \ 86 VMCB_CACHE_I | \ 87 VMCB_CACHE_TPR | \ 88 VMCB_CACHE_CR2 | \ 89 VMCB_CACHE_CR | \ 90 VMCB_CACHE_DT | \ 91 VMCB_CACHE_SEG | \ 92 VMCB_CACHE_NP) 93 94static uint32_t vmcb_clean = VMCB_CACHE_DEFAULT; 95SYSCTL_INT(_hw_vmm_svm, OID_AUTO, vmcb_clean, CTLFLAG_RDTUN, &vmcb_clean, 96 0, NULL); 97 98static MALLOC_DEFINE(M_SVM, "svm", "svm"); 99static MALLOC_DEFINE(M_SVM_VLAPIC, "svm-vlapic", "svm-vlapic"); 100 101/* Per-CPU context area. */ 102extern struct pcpu __pcpu[]; 103 104static uint32_t svm_feature; /* AMD SVM features. */ 105SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, features, CTLFLAG_RD, &svm_feature, 0, 106 "SVM features advertised by CPUID.8000000AH:EDX"); 107 108static int disable_npf_assist; 109SYSCTL_INT(_hw_vmm_svm, OID_AUTO, disable_npf_assist, CTLFLAG_RWTUN, 110 &disable_npf_assist, 0, NULL); 111 112/* Maximum ASIDs supported by the processor */ 113static uint32_t nasid; 114SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, num_asids, CTLFLAG_RD, &nasid, 0, 115 "Number of ASIDs supported by this processor"); 116 117/* Current ASID generation for each host cpu */ 118static struct asid asid[MAXCPU]; 119 120/* 121 * SVM host state saved area of size 4KB for each core. 122 */ 123static uint8_t hsave[MAXCPU][PAGE_SIZE] __aligned(PAGE_SIZE); 124 125static VMM_STAT_AMD(VCPU_EXITINTINFO, "VM exits during event delivery"); 126static VMM_STAT_AMD(VCPU_INTINFO_INJECTED, "Events pending at VM entry"); 127static VMM_STAT_AMD(VMEXIT_VINTR, "VM exits due to interrupt window"); 128 129static int svm_setreg(void *arg, int vcpu, int ident, uint64_t val); 130 131static __inline int 132flush_by_asid(void) 133{ 134 135 return (svm_feature & AMD_CPUID_SVM_FLUSH_BY_ASID); 136} 137 138static __inline int 139decode_assist(void) 140{ 141 142 return (svm_feature & AMD_CPUID_SVM_DECODE_ASSIST); 143} 144 145static void 146svm_disable(void *arg __unused) 147{ 148 uint64_t efer; 149 150 efer = rdmsr(MSR_EFER); 151 efer &= ~EFER_SVM; 152 wrmsr(MSR_EFER, efer); 153} 154 155/* 156 * Disable SVM on all CPUs. 157 */ 158static int 159svm_cleanup(void) 160{ 161 162 smp_rendezvous(NULL, svm_disable, NULL, NULL); 163 return (0); 164} 165 166/* 167 * Verify that all the features required by bhyve are available. 168 */ 169static int 170check_svm_features(void) 171{ 172 u_int regs[4]; 173 174 /* CPUID Fn8000_000A is for SVM */ 175 do_cpuid(0x8000000A, regs); 176 svm_feature = regs[3]; 177 178 nasid = regs[1]; 179 KASSERT(nasid > 1, ("Insufficient ASIDs for guests: %#x", nasid)); 180 181 /* bhyve requires the Nested Paging feature */ 182 if (!(svm_feature & AMD_CPUID_SVM_NP)) { 183 printf("SVM: Nested Paging feature not available.\n"); 184 return (ENXIO); 185 } 186 187 /* bhyve requires the NRIP Save feature */ 188 if (!(svm_feature & AMD_CPUID_SVM_NRIP_SAVE)) { 189 printf("SVM: NRIP Save feature not available.\n"); 190 return (ENXIO); 191 } 192 193 return (0); 194} 195 196static void 197svm_enable(void *arg __unused) 198{ 199 uint64_t efer; 200 201 efer = rdmsr(MSR_EFER); 202 efer |= EFER_SVM; 203 wrmsr(MSR_EFER, efer); 204 205 wrmsr(MSR_VM_HSAVE_PA, vtophys(hsave[curcpu])); 206} 207 208/* 209 * Return 1 if SVM is enabled on this processor and 0 otherwise. 210 */ 211static int 212svm_available(void) 213{ 214 uint64_t msr; 215 216 /* Section 15.4 Enabling SVM from APM2. */ 217 if ((amd_feature2 & AMDID2_SVM) == 0) { 218 printf("SVM: not available.\n"); 219 return (0); 220 } 221 222 msr = rdmsr(MSR_VM_CR); 223 if ((msr & VM_CR_SVMDIS) != 0) { 224 printf("SVM: disabled by BIOS.\n"); 225 return (0); 226 } 227 228 return (1); 229} 230 231static int 232svm_init(int ipinum) 233{ 234 int error, cpu; 235 236 if (!svm_available()) 237 return (ENXIO); 238 239 error = check_svm_features(); 240 if (error) 241 return (error); 242 243 vmcb_clean &= VMCB_CACHE_DEFAULT; 244 245 for (cpu = 0; cpu < MAXCPU; cpu++) { 246 /* 247 * Initialize the host ASIDs to their "highest" valid values. 248 * 249 * The next ASID allocation will rollover both 'gen' and 'num' 250 * and start off the sequence at {1,1}. 251 */ 252 asid[cpu].gen = ~0UL; 253 asid[cpu].num = nasid - 1; 254 } 255 256 svm_msr_init(); 257 svm_npt_init(ipinum); 258 259 /* Enable SVM on all CPUs */ 260 smp_rendezvous(NULL, svm_enable, NULL, NULL); 261 262 return (0); 263} 264 265static void 266svm_restore(void) 267{ 268 269 svm_enable(NULL); 270} 271 272/* Pentium compatible MSRs */ 273#define MSR_PENTIUM_START 0 274#define MSR_PENTIUM_END 0x1FFF 275/* AMD 6th generation and Intel compatible MSRs */ 276#define MSR_AMD6TH_START 0xC0000000UL 277#define MSR_AMD6TH_END 0xC0001FFFUL 278/* AMD 7th and 8th generation compatible MSRs */ 279#define MSR_AMD7TH_START 0xC0010000UL 280#define MSR_AMD7TH_END 0xC0011FFFUL 281 282/* 283 * Get the index and bit position for a MSR in permission bitmap. 284 * Two bits are used for each MSR: lower bit for read and higher bit for write. 285 */ 286static int 287svm_msr_index(uint64_t msr, int *index, int *bit) 288{ 289 uint32_t base, off; 290 291 *index = -1; 292 *bit = (msr % 4) * 2; 293 base = 0; 294 295 if (msr >= MSR_PENTIUM_START && msr <= MSR_PENTIUM_END) { 296 *index = msr / 4; 297 return (0); 298 } 299 300 base += (MSR_PENTIUM_END - MSR_PENTIUM_START + 1); 301 if (msr >= MSR_AMD6TH_START && msr <= MSR_AMD6TH_END) { 302 off = (msr - MSR_AMD6TH_START); 303 *index = (off + base) / 4; 304 return (0); 305 } 306 307 base += (MSR_AMD6TH_END - MSR_AMD6TH_START + 1); 308 if (msr >= MSR_AMD7TH_START && msr <= MSR_AMD7TH_END) { 309 off = (msr - MSR_AMD7TH_START); 310 *index = (off + base) / 4; 311 return (0); 312 } 313 314 return (EINVAL); 315} 316 317/* 318 * Allow vcpu to read or write the 'msr' without trapping into the hypervisor. 319 */ 320static void 321svm_msr_perm(uint8_t *perm_bitmap, uint64_t msr, bool read, bool write) 322{ 323 int index, bit, error; 324 325 error = svm_msr_index(msr, &index, &bit); 326 KASSERT(error == 0, ("%s: invalid msr %#lx", __func__, msr)); 327 KASSERT(index >= 0 && index < SVM_MSR_BITMAP_SIZE, 328 ("%s: invalid index %d for msr %#lx", __func__, index, msr)); 329 KASSERT(bit >= 0 && bit <= 6, ("%s: invalid bit position %d " 330 "msr %#lx", __func__, bit, msr)); 331 332 if (read) 333 perm_bitmap[index] &= ~(1UL << bit); 334 335 if (write) 336 perm_bitmap[index] &= ~(2UL << bit); 337} 338 339static void 340svm_msr_rw_ok(uint8_t *perm_bitmap, uint64_t msr) 341{ 342 343 svm_msr_perm(perm_bitmap, msr, true, true); 344} 345 346static void 347svm_msr_rd_ok(uint8_t *perm_bitmap, uint64_t msr) 348{ 349 350 svm_msr_perm(perm_bitmap, msr, true, false); 351} 352 353static __inline int 354svm_get_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask) 355{ 356 struct vmcb_ctrl *ctrl; 357 358 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx)); 359 360 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 361 return (ctrl->intercept[idx] & bitmask ? 1 : 0); 362} 363 364static __inline void 365svm_set_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask, 366 int enabled) 367{ 368 struct vmcb_ctrl *ctrl; 369 uint32_t oldval; 370 371 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx)); 372 373 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 374 oldval = ctrl->intercept[idx]; 375 376 if (enabled) 377 ctrl->intercept[idx] |= bitmask; 378 else 379 ctrl->intercept[idx] &= ~bitmask; 380 381 if (ctrl->intercept[idx] != oldval) { 382 svm_set_dirty(sc, vcpu, VMCB_CACHE_I); 383 VCPU_CTR3(sc->vm, vcpu, "intercept[%d] modified " 384 "from %#x to %#x", idx, oldval, ctrl->intercept[idx]); 385 } 386} 387 388static __inline void 389svm_disable_intercept(struct svm_softc *sc, int vcpu, int off, uint32_t bitmask) 390{ 391 392 svm_set_intercept(sc, vcpu, off, bitmask, 0); 393} 394 395static __inline void 396svm_enable_intercept(struct svm_softc *sc, int vcpu, int off, uint32_t bitmask) 397{ 398 399 svm_set_intercept(sc, vcpu, off, bitmask, 1); 400} 401 402static void 403vmcb_init(struct svm_softc *sc, int vcpu, uint64_t iopm_base_pa, 404 uint64_t msrpm_base_pa, uint64_t np_pml4) 405{ 406 struct vmcb_ctrl *ctrl; 407 struct vmcb_state *state; 408 uint32_t mask; 409 int n; 410 411 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 412 state = svm_get_vmcb_state(sc, vcpu); 413 414 ctrl->iopm_base_pa = iopm_base_pa; 415 ctrl->msrpm_base_pa = msrpm_base_pa; 416 417 /* Enable nested paging */ 418 ctrl->np_enable = 1; 419 ctrl->n_cr3 = np_pml4; 420 421 /* 422 * Intercept accesses to the control registers that are not shadowed 423 * in the VMCB - i.e. all except cr0, cr2, cr3, cr4 and cr8. 424 */ 425 for (n = 0; n < 16; n++) { 426 mask = (BIT(n) << 16) | BIT(n); 427 if (n == 0 || n == 2 || n == 3 || n == 4 || n == 8) 428 svm_disable_intercept(sc, vcpu, VMCB_CR_INTCPT, mask); 429 else 430 svm_enable_intercept(sc, vcpu, VMCB_CR_INTCPT, mask); 431 } 432 433 434 /* 435 * Intercept everything when tracing guest exceptions otherwise 436 * just intercept machine check exception. 437 */ 438 if (vcpu_trace_exceptions(sc->vm, vcpu)) { 439 for (n = 0; n < 32; n++) { 440 /* 441 * Skip unimplemented vectors in the exception bitmap. 442 */ 443 if (n == 2 || n == 9) { 444 continue; 445 } 446 svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(n)); 447 } 448 } else { 449 svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(IDT_MC)); 450 } 451 452 /* Intercept various events (for e.g. I/O, MSR and CPUID accesses) */ 453 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IO); 454 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_MSR); 455 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_CPUID); 456 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INTR); 457 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INIT); 458 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_NMI); 459 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_SMI); 460 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_SHUTDOWN); 461 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 462 VMCB_INTCPT_FERR_FREEZE); 463 464 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_MONITOR); 465 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_MWAIT); 466 467 /* 468 * From section "Canonicalization and Consistency Checks" in APMv2 469 * the VMRUN intercept bit must be set to pass the consistency check. 470 */ 471 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_VMRUN); 472 473 /* 474 * The ASID will be set to a non-zero value just before VMRUN. 475 */ 476 ctrl->asid = 0; 477 478 /* 479 * Section 15.21.1, Interrupt Masking in EFLAGS 480 * Section 15.21.2, Virtualizing APIC.TPR 481 * 482 * This must be set for %rflag and %cr8 isolation of guest and host. 483 */ 484 ctrl->v_intr_masking = 1; 485 486 /* Enable Last Branch Record aka LBR for debugging */ 487 ctrl->lbr_virt_en = 1; 488 state->dbgctl = BIT(0); 489 490 /* EFER_SVM must always be set when the guest is executing */ 491 state->efer = EFER_SVM; 492 493 /* Set up the PAT to power-on state */ 494 state->g_pat = PAT_VALUE(0, PAT_WRITE_BACK) | 495 PAT_VALUE(1, PAT_WRITE_THROUGH) | 496 PAT_VALUE(2, PAT_UNCACHED) | 497 PAT_VALUE(3, PAT_UNCACHEABLE) | 498 PAT_VALUE(4, PAT_WRITE_BACK) | 499 PAT_VALUE(5, PAT_WRITE_THROUGH) | 500 PAT_VALUE(6, PAT_UNCACHED) | 501 PAT_VALUE(7, PAT_UNCACHEABLE); 502} 503 504/* 505 * Initialize a virtual machine. 506 */ 507static void * 508svm_vminit(struct vm *vm, pmap_t pmap) 509{ 510 struct svm_softc *svm_sc; 511 struct svm_vcpu *vcpu; 512 vm_paddr_t msrpm_pa, iopm_pa, pml4_pa; 513 int i; 514 515 svm_sc = malloc(sizeof (struct svm_softc), M_SVM, M_WAITOK | M_ZERO); 516 svm_sc->vm = vm; 517 svm_sc->nptp = (vm_offset_t)vtophys(pmap->pm_pml4); 518 519 /* 520 * Intercept read and write accesses to all MSRs. 521 */ 522 memset(svm_sc->msr_bitmap, 0xFF, sizeof(svm_sc->msr_bitmap)); 523 524 /* 525 * Access to the following MSRs is redirected to the VMCB when the 526 * guest is executing. Therefore it is safe to allow the guest to 527 * read/write these MSRs directly without hypervisor involvement. 528 */ 529 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_GSBASE); 530 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_FSBASE); 531 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_KGSBASE); 532 533 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_STAR); 534 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_LSTAR); 535 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_CSTAR); 536 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SF_MASK); 537 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_CS_MSR); 538 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_ESP_MSR); 539 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_EIP_MSR); 540 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_PAT); 541 542 svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_TSC); 543 544 /* 545 * Intercept writes to make sure that the EFER_SVM bit is not cleared. 546 */ 547 svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_EFER); 548 549 /* Intercept access to all I/O ports. */ 550 memset(svm_sc->iopm_bitmap, 0xFF, sizeof(svm_sc->iopm_bitmap)); 551 552 iopm_pa = vtophys(svm_sc->iopm_bitmap); 553 msrpm_pa = vtophys(svm_sc->msr_bitmap); 554 pml4_pa = svm_sc->nptp; 555 for (i = 0; i < VM_MAXCPU; i++) { 556 vcpu = svm_get_vcpu(svm_sc, i); 557 vcpu->lastcpu = NOCPU; 558 vcpu->vmcb_pa = vtophys(&vcpu->vmcb); 559 vmcb_init(svm_sc, i, iopm_pa, msrpm_pa, pml4_pa); 560 svm_msr_guest_init(svm_sc, i); 561 } 562 return (svm_sc); 563} 564 565static int 566svm_cpl(struct vmcb_state *state) 567{ 568 569 /* 570 * From APMv2: 571 * "Retrieve the CPL from the CPL field in the VMCB, not 572 * from any segment DPL" 573 */ 574 return (state->cpl); 575} 576 577static enum vm_cpu_mode 578svm_vcpu_mode(struct vmcb *vmcb) 579{ 580 struct vmcb_segment seg; 581 struct vmcb_state *state; 582 int error; 583 584 state = &vmcb->state; 585 586 if (state->efer & EFER_LMA) { 587 error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg); 588 KASSERT(error == 0, ("%s: vmcb_seg(cs) error %d", __func__, 589 error)); 590 591 /* 592 * Section 4.8.1 for APM2, check if Code Segment has 593 * Long attribute set in descriptor. 594 */ 595 if (seg.attrib & VMCB_CS_ATTRIB_L) 596 return (CPU_MODE_64BIT); 597 else 598 return (CPU_MODE_COMPATIBILITY); 599 } else if (state->cr0 & CR0_PE) { 600 return (CPU_MODE_PROTECTED); 601 } else { 602 return (CPU_MODE_REAL); 603 } 604} 605 606static enum vm_paging_mode 607svm_paging_mode(uint64_t cr0, uint64_t cr4, uint64_t efer) 608{ 609 610 if ((cr0 & CR0_PG) == 0) 611 return (PAGING_MODE_FLAT); 612 if ((cr4 & CR4_PAE) == 0) 613 return (PAGING_MODE_32); 614 if (efer & EFER_LME) 615 return (PAGING_MODE_64); 616 else 617 return (PAGING_MODE_PAE); 618} 619 620/* 621 * ins/outs utility routines 622 */ 623static uint64_t 624svm_inout_str_index(struct svm_regctx *regs, int in) 625{ 626 uint64_t val; 627 628 val = in ? regs->sctx_rdi : regs->sctx_rsi; 629 630 return (val); 631} 632 633static uint64_t 634svm_inout_str_count(struct svm_regctx *regs, int rep) 635{ 636 uint64_t val; 637 638 val = rep ? regs->sctx_rcx : 1; 639 640 return (val); 641} 642 643static void 644svm_inout_str_seginfo(struct svm_softc *svm_sc, int vcpu, int64_t info1, 645 int in, struct vm_inout_str *vis) 646{ 647 int error, s; 648 649 if (in) { 650 vis->seg_name = VM_REG_GUEST_ES; 651 } else { 652 /* The segment field has standard encoding */ 653 s = (info1 >> 10) & 0x7; 654 vis->seg_name = vm_segment_name(s); 655 } 656 657 error = vmcb_getdesc(svm_sc, vcpu, vis->seg_name, &vis->seg_desc); 658 KASSERT(error == 0, ("%s: svm_getdesc error %d", __func__, error)); 659} 660 661static int 662svm_inout_str_addrsize(uint64_t info1) 663{ 664 uint32_t size; 665 666 size = (info1 >> 7) & 0x7; 667 switch (size) { 668 case 1: 669 return (2); /* 16 bit */ 670 case 2: 671 return (4); /* 32 bit */ 672 case 4: 673 return (8); /* 64 bit */ 674 default: 675 panic("%s: invalid size encoding %d", __func__, size); 676 } 677} 678 679static void 680svm_paging_info(struct vmcb *vmcb, struct vm_guest_paging *paging) 681{ 682 struct vmcb_state *state; 683 684 state = &vmcb->state; 685 paging->cr3 = state->cr3; 686 paging->cpl = svm_cpl(state); 687 paging->cpu_mode = svm_vcpu_mode(vmcb); 688 paging->paging_mode = svm_paging_mode(state->cr0, state->cr4, 689 state->efer); 690} 691 692#define UNHANDLED 0 693 694/* 695 * Handle guest I/O intercept. 696 */ 697static int 698svm_handle_io(struct svm_softc *svm_sc, int vcpu, struct vm_exit *vmexit) 699{ 700 struct vmcb_ctrl *ctrl; 701 struct vmcb_state *state; 702 struct svm_regctx *regs; 703 struct vm_inout_str *vis; 704 uint64_t info1; 705 int inout_string; 706 707 state = svm_get_vmcb_state(svm_sc, vcpu); 708 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu); 709 regs = svm_get_guest_regctx(svm_sc, vcpu); 710 711 info1 = ctrl->exitinfo1; 712 inout_string = info1 & BIT(2) ? 1 : 0; 713 714 /* 715 * The effective segment number in EXITINFO1[12:10] is populated 716 * only if the processor has the DecodeAssist capability. 717 * 718 * XXX this is not specified explicitly in APMv2 but can be verified 719 * empirically. 720 */ 721 if (inout_string && !decode_assist()) 722 return (UNHANDLED); 723 724 vmexit->exitcode = VM_EXITCODE_INOUT; 725 vmexit->u.inout.in = (info1 & BIT(0)) ? 1 : 0; 726 vmexit->u.inout.string = inout_string; 727 vmexit->u.inout.rep = (info1 & BIT(3)) ? 1 : 0; 728 vmexit->u.inout.bytes = (info1 >> 4) & 0x7; 729 vmexit->u.inout.port = (uint16_t)(info1 >> 16); 730 vmexit->u.inout.eax = (uint32_t)(state->rax); 731 732 if (inout_string) { 733 vmexit->exitcode = VM_EXITCODE_INOUT_STR; 734 vis = &vmexit->u.inout_str; 735 svm_paging_info(svm_get_vmcb(svm_sc, vcpu), &vis->paging); 736 vis->rflags = state->rflags; 737 vis->cr0 = state->cr0; 738 vis->index = svm_inout_str_index(regs, vmexit->u.inout.in); 739 vis->count = svm_inout_str_count(regs, vmexit->u.inout.rep); 740 vis->addrsize = svm_inout_str_addrsize(info1); 741 svm_inout_str_seginfo(svm_sc, vcpu, info1, 742 vmexit->u.inout.in, vis); 743 } 744 745 return (UNHANDLED); 746} 747 748static int 749npf_fault_type(uint64_t exitinfo1) 750{ 751 752 if (exitinfo1 & VMCB_NPF_INFO1_W) 753 return (VM_PROT_WRITE); 754 else if (exitinfo1 & VMCB_NPF_INFO1_ID) 755 return (VM_PROT_EXECUTE); 756 else 757 return (VM_PROT_READ); 758} 759 760static bool 761svm_npf_emul_fault(uint64_t exitinfo1) 762{ 763 764 if (exitinfo1 & VMCB_NPF_INFO1_ID) { 765 return (false); 766 } 767 768 if (exitinfo1 & VMCB_NPF_INFO1_GPT) { 769 return (false); 770 } 771 772 if ((exitinfo1 & VMCB_NPF_INFO1_GPA) == 0) { 773 return (false); 774 } 775 776 return (true); 777} 778 779static void 780svm_handle_inst_emul(struct vmcb *vmcb, uint64_t gpa, struct vm_exit *vmexit) 781{ 782 struct vm_guest_paging *paging; 783 struct vmcb_segment seg; 784 struct vmcb_ctrl *ctrl; 785 char *inst_bytes; 786 int error, inst_len; 787 788 ctrl = &vmcb->ctrl; 789 paging = &vmexit->u.inst_emul.paging; 790 791 vmexit->exitcode = VM_EXITCODE_INST_EMUL; 792 vmexit->u.inst_emul.gpa = gpa; 793 vmexit->u.inst_emul.gla = VIE_INVALID_GLA; 794 svm_paging_info(vmcb, paging); 795 796 error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg); 797 KASSERT(error == 0, ("%s: vmcb_seg(CS) error %d", __func__, error)); 798 799 switch(paging->cpu_mode) { 800 case CPU_MODE_PROTECTED: 801 case CPU_MODE_COMPATIBILITY: 802 /* 803 * Section 4.8.1 of APM2, Default Operand Size or D bit. 804 */ 805 vmexit->u.inst_emul.cs_d = (seg.attrib & VMCB_CS_ATTRIB_D) ? 806 1 : 0; 807 break; 808 default: 809 vmexit->u.inst_emul.cs_d = 0; 810 break; 811 } 812 813 /* 814 * Copy the instruction bytes into 'vie' if available. 815 */ 816 if (decode_assist() && !disable_npf_assist) { 817 inst_len = ctrl->inst_len; 818 inst_bytes = ctrl->inst_bytes; 819 } else { 820 inst_len = 0; 821 inst_bytes = NULL; 822 } 823 vie_init(&vmexit->u.inst_emul.vie, inst_bytes, inst_len); 824} 825 826#ifdef KTR 827static const char * 828intrtype_to_str(int intr_type) 829{ 830 switch (intr_type) { 831 case VMCB_EVENTINJ_TYPE_INTR: 832 return ("hwintr"); 833 case VMCB_EVENTINJ_TYPE_NMI: 834 return ("nmi"); 835 case VMCB_EVENTINJ_TYPE_INTn: 836 return ("swintr"); 837 case VMCB_EVENTINJ_TYPE_EXCEPTION: 838 return ("exception"); 839 default: 840 panic("%s: unknown intr_type %d", __func__, intr_type); 841 } 842} 843#endif 844 845/* 846 * Inject an event to vcpu as described in section 15.20, "Event injection". 847 */ 848static void 849svm_eventinject(struct svm_softc *sc, int vcpu, int intr_type, int vector, 850 uint32_t error, bool ec_valid) 851{ 852 struct vmcb_ctrl *ctrl; 853 854 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 855 856 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0, 857 ("%s: event already pending %#lx", __func__, ctrl->eventinj)); 858 859 KASSERT(vector >=0 && vector <= 255, ("%s: invalid vector %d", 860 __func__, vector)); 861 862 switch (intr_type) { 863 case VMCB_EVENTINJ_TYPE_INTR: 864 case VMCB_EVENTINJ_TYPE_NMI: 865 case VMCB_EVENTINJ_TYPE_INTn: 866 break; 867 case VMCB_EVENTINJ_TYPE_EXCEPTION: 868 if (vector >= 0 && vector <= 31 && vector != 2) 869 break; 870 /* FALLTHROUGH */ 871 default: 872 panic("%s: invalid intr_type/vector: %d/%d", __func__, 873 intr_type, vector); 874 } 875 ctrl->eventinj = vector | (intr_type << 8) | VMCB_EVENTINJ_VALID; 876 if (ec_valid) { 877 ctrl->eventinj |= VMCB_EVENTINJ_EC_VALID; 878 ctrl->eventinj |= (uint64_t)error << 32; 879 VCPU_CTR3(sc->vm, vcpu, "Injecting %s at vector %d errcode %#x", 880 intrtype_to_str(intr_type), vector, error); 881 } else { 882 VCPU_CTR2(sc->vm, vcpu, "Injecting %s at vector %d", 883 intrtype_to_str(intr_type), vector); 884 } 885} 886 887static void 888svm_update_virqinfo(struct svm_softc *sc, int vcpu) 889{ 890 struct vm *vm; 891 struct vlapic *vlapic; 892 struct vmcb_ctrl *ctrl; 893 int pending; 894 895 vm = sc->vm; 896 vlapic = vm_lapic(vm, vcpu); 897 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 898 899 /* Update %cr8 in the emulated vlapic */ 900 vlapic_set_cr8(vlapic, ctrl->v_tpr); 901 902 /* 903 * If V_IRQ indicates that the interrupt injection attempted on then 904 * last VMRUN was successful then update the vlapic accordingly. 905 */ 906 if (ctrl->v_intr_vector != 0) { 907 pending = ctrl->v_irq; 908 KASSERT(ctrl->v_intr_vector >= 16, ("%s: invalid " 909 "v_intr_vector %d", __func__, ctrl->v_intr_vector)); 910 KASSERT(!ctrl->v_ign_tpr, ("%s: invalid v_ign_tpr", __func__)); 911 VCPU_CTR2(vm, vcpu, "v_intr_vector %d %s", ctrl->v_intr_vector, 912 pending ? "pending" : "accepted"); 913 if (!pending) 914 vlapic_intr_accepted(vlapic, ctrl->v_intr_vector); 915 } 916} 917 918static void 919svm_save_intinfo(struct svm_softc *svm_sc, int vcpu) 920{ 921 struct vmcb_ctrl *ctrl; 922 uint64_t intinfo; 923 924 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu); 925 intinfo = ctrl->exitintinfo; 926 if (!VMCB_EXITINTINFO_VALID(intinfo)) 927 return; 928 929 /* 930 * From APMv2, Section "Intercepts during IDT interrupt delivery" 931 * 932 * If a #VMEXIT happened during event delivery then record the event 933 * that was being delivered. 934 */ 935 VCPU_CTR2(svm_sc->vm, vcpu, "SVM:Pending INTINFO(0x%lx), vector=%d.\n", 936 intinfo, VMCB_EXITINTINFO_VECTOR(intinfo)); 937 vmm_stat_incr(svm_sc->vm, vcpu, VCPU_EXITINTINFO, 1); 938 vm_exit_intinfo(svm_sc->vm, vcpu, intinfo); 939} 940 941static __inline int 942vintr_intercept_enabled(struct svm_softc *sc, int vcpu) 943{ 944 945 return (svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 946 VMCB_INTCPT_VINTR)); 947} 948 949static __inline void 950enable_intr_window_exiting(struct svm_softc *sc, int vcpu) 951{ 952 struct vmcb_ctrl *ctrl; 953 954 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 955 956 if (ctrl->v_irq && ctrl->v_intr_vector == 0) { 957 KASSERT(ctrl->v_ign_tpr, ("%s: invalid v_ign_tpr", __func__)); 958 KASSERT(vintr_intercept_enabled(sc, vcpu), 959 ("%s: vintr intercept should be enabled", __func__)); 960 return; 961 } 962 963 VCPU_CTR0(sc->vm, vcpu, "Enable intr window exiting"); 964 ctrl->v_irq = 1; 965 ctrl->v_ign_tpr = 1; 966 ctrl->v_intr_vector = 0; 967 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 968 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR); 969} 970 971static __inline void 972disable_intr_window_exiting(struct svm_softc *sc, int vcpu) 973{ 974 struct vmcb_ctrl *ctrl; 975 976 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 977 978 if (!ctrl->v_irq && ctrl->v_intr_vector == 0) { 979 KASSERT(!vintr_intercept_enabled(sc, vcpu), 980 ("%s: vintr intercept should be disabled", __func__)); 981 return; 982 } 983 984#ifdef KTR 985 if (ctrl->v_intr_vector == 0) 986 VCPU_CTR0(sc->vm, vcpu, "Disable intr window exiting"); 987 else 988 VCPU_CTR0(sc->vm, vcpu, "Clearing V_IRQ interrupt injection"); 989#endif 990 ctrl->v_irq = 0; 991 ctrl->v_intr_vector = 0; 992 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 993 svm_disable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR); 994} 995 996static int 997svm_modify_intr_shadow(struct svm_softc *sc, int vcpu, uint64_t val) 998{ 999 struct vmcb_ctrl *ctrl; 1000 int oldval, newval; 1001 1002 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 1003 oldval = ctrl->intr_shadow; 1004 newval = val ? 1 : 0; 1005 if (newval != oldval) { 1006 ctrl->intr_shadow = newval; 1007 VCPU_CTR1(sc->vm, vcpu, "Setting intr_shadow to %d", newval); 1008 } 1009 return (0); 1010} 1011 1012static int 1013svm_get_intr_shadow(struct svm_softc *sc, int vcpu, uint64_t *val) 1014{ 1015 struct vmcb_ctrl *ctrl; 1016 1017 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 1018 *val = ctrl->intr_shadow; 1019 return (0); 1020} 1021 1022/* 1023 * Once an NMI is injected it blocks delivery of further NMIs until the handler 1024 * executes an IRET. The IRET intercept is enabled when an NMI is injected to 1025 * to track when the vcpu is done handling the NMI. 1026 */ 1027static int 1028nmi_blocked(struct svm_softc *sc, int vcpu) 1029{ 1030 int blocked; 1031 1032 blocked = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 1033 VMCB_INTCPT_IRET); 1034 return (blocked); 1035} 1036 1037static void 1038enable_nmi_blocking(struct svm_softc *sc, int vcpu) 1039{ 1040 1041 KASSERT(!nmi_blocked(sc, vcpu), ("vNMI already blocked")); 1042 VCPU_CTR0(sc->vm, vcpu, "vNMI blocking enabled"); 1043 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IRET); 1044} 1045 1046static void 1047clear_nmi_blocking(struct svm_softc *sc, int vcpu) 1048{ 1049 int error; 1050 1051 KASSERT(nmi_blocked(sc, vcpu), ("vNMI already unblocked")); 1052 VCPU_CTR0(sc->vm, vcpu, "vNMI blocking cleared"); 1053 /* 1054 * When the IRET intercept is cleared the vcpu will attempt to execute 1055 * the "iret" when it runs next. However, it is possible to inject 1056 * another NMI into the vcpu before the "iret" has actually executed. 1057 * 1058 * For e.g. if the "iret" encounters a #NPF when accessing the stack 1059 * it will trap back into the hypervisor. If an NMI is pending for 1060 * the vcpu it will be injected into the guest. 1061 * 1062 * XXX this needs to be fixed 1063 */ 1064 svm_disable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IRET); 1065 1066 /* 1067 * Set 'intr_shadow' to prevent an NMI from being injected on the 1068 * immediate VMRUN. 1069 */ 1070 error = svm_modify_intr_shadow(sc, vcpu, 1); 1071 KASSERT(!error, ("%s: error %d setting intr_shadow", __func__, error)); 1072} 1073 1074static int 1075emulate_wrmsr(struct svm_softc *sc, int vcpu, u_int num, uint64_t val, 1076 bool *retu) 1077{ 1078 int error; 1079 1080 if (lapic_msr(num)) 1081 error = lapic_wrmsr(sc->vm, vcpu, num, val, retu); 1082 else if (num == MSR_EFER) 1083 error = svm_setreg(sc, vcpu, VM_REG_GUEST_EFER, val); 1084 else 1085 error = svm_wrmsr(sc, vcpu, num, val, retu); 1086 1087 return (error); 1088} 1089 1090static int 1091emulate_rdmsr(struct svm_softc *sc, int vcpu, u_int num, bool *retu) 1092{ 1093 struct vmcb_state *state; 1094 struct svm_regctx *ctx; 1095 uint64_t result; 1096 int error; 1097 1098 if (lapic_msr(num)) 1099 error = lapic_rdmsr(sc->vm, vcpu, num, &result, retu); 1100 else 1101 error = svm_rdmsr(sc, vcpu, num, &result, retu); 1102 1103 if (error == 0) { 1104 state = svm_get_vmcb_state(sc, vcpu); 1105 ctx = svm_get_guest_regctx(sc, vcpu); 1106 state->rax = result & 0xffffffff; 1107 ctx->sctx_rdx = result >> 32; 1108 } 1109 1110 return (error); 1111} 1112 1113#ifdef KTR 1114static const char * 1115exit_reason_to_str(uint64_t reason) 1116{ 1117 static char reasonbuf[32]; 1118 1119 switch (reason) { 1120 case VMCB_EXIT_INVALID: 1121 return ("invalvmcb"); 1122 case VMCB_EXIT_SHUTDOWN: 1123 return ("shutdown"); 1124 case VMCB_EXIT_NPF: 1125 return ("nptfault"); 1126 case VMCB_EXIT_PAUSE: 1127 return ("pause"); 1128 case VMCB_EXIT_HLT: 1129 return ("hlt"); 1130 case VMCB_EXIT_CPUID: 1131 return ("cpuid"); 1132 case VMCB_EXIT_IO: 1133 return ("inout"); 1134 case VMCB_EXIT_MC: 1135 return ("mchk"); 1136 case VMCB_EXIT_INTR: 1137 return ("extintr"); 1138 case VMCB_EXIT_NMI: 1139 return ("nmi"); 1140 case VMCB_EXIT_VINTR: 1141 return ("vintr"); 1142 case VMCB_EXIT_MSR: 1143 return ("msr"); 1144 case VMCB_EXIT_IRET: 1145 return ("iret"); 1146 case VMCB_EXIT_MONITOR: 1147 return ("monitor"); 1148 case VMCB_EXIT_MWAIT: 1149 return ("mwait"); 1150 default: 1151 snprintf(reasonbuf, sizeof(reasonbuf), "%#lx", reason); 1152 return (reasonbuf); 1153 } 1154} 1155#endif /* KTR */ 1156 1157/* 1158 * From section "State Saved on Exit" in APMv2: nRIP is saved for all #VMEXITs 1159 * that are due to instruction intercepts as well as MSR and IOIO intercepts 1160 * and exceptions caused by INT3, INTO and BOUND instructions. 1161 * 1162 * Return 1 if the nRIP is valid and 0 otherwise. 1163 */ 1164static int 1165nrip_valid(uint64_t exitcode) 1166{ 1167 switch (exitcode) { 1168 case 0x00 ... 0x0F: /* read of CR0 through CR15 */ 1169 case 0x10 ... 0x1F: /* write of CR0 through CR15 */ 1170 case 0x20 ... 0x2F: /* read of DR0 through DR15 */ 1171 case 0x30 ... 0x3F: /* write of DR0 through DR15 */ 1172 case 0x43: /* INT3 */ 1173 case 0x44: /* INTO */ 1174 case 0x45: /* BOUND */ 1175 case 0x65 ... 0x7C: /* VMEXIT_CR0_SEL_WRITE ... VMEXIT_MSR */ 1176 case 0x80 ... 0x8D: /* VMEXIT_VMRUN ... VMEXIT_XSETBV */ 1177 return (1); 1178 default: 1179 return (0); 1180 } 1181} 1182 1183/* 1184 * Collateral for a generic SVM VM-exit. 1185 */ 1186static void 1187vm_exit_svm(struct vm_exit *vme, uint64_t code, uint64_t info1, uint64_t info2) 1188{ 1189 1190 vme->exitcode = VM_EXITCODE_SVM; 1191 vme->u.svm.exitcode = code; 1192 vme->u.svm.exitinfo1 = info1; 1193 vme->u.svm.exitinfo2 = info2; 1194} 1195 1196static int 1197svm_vmexit(struct svm_softc *svm_sc, int vcpu, struct vm_exit *vmexit) 1198{ 1199 struct vmcb *vmcb; 1200 struct vmcb_state *state; 1201 struct vmcb_ctrl *ctrl; 1202 struct svm_regctx *ctx; 1203 struct vm_exception exception; 1204 uint64_t code, info1, info2, val; 1205 uint32_t eax, ecx, edx; 1206 int error, errcode_valid, handled, idtvec, reflect; 1207 bool retu; 1208 1209 ctx = svm_get_guest_regctx(svm_sc, vcpu); 1210 vmcb = svm_get_vmcb(svm_sc, vcpu); 1211 state = &vmcb->state; 1212 ctrl = &vmcb->ctrl; 1213 1214 handled = 0; 1215 code = ctrl->exitcode; 1216 info1 = ctrl->exitinfo1; 1217 info2 = ctrl->exitinfo2; 1218 1219 vmexit->exitcode = VM_EXITCODE_BOGUS; 1220 vmexit->rip = state->rip; 1221 vmexit->inst_length = nrip_valid(code) ? ctrl->nrip - state->rip : 0; 1222 1223 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_COUNT, 1); 1224 1225 /* 1226 * #VMEXIT(INVALID) needs to be handled early because the VMCB is 1227 * in an inconsistent state and can trigger assertions that would 1228 * never happen otherwise. 1229 */ 1230 if (code == VMCB_EXIT_INVALID) { 1231 vm_exit_svm(vmexit, code, info1, info2); 1232 return (0); 1233 } 1234 1235 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0, ("%s: event " 1236 "injection valid bit is set %#lx", __func__, ctrl->eventinj)); 1237 1238 KASSERT(vmexit->inst_length >= 0 && vmexit->inst_length <= 15, 1239 ("invalid inst_length %d: code (%#lx), info1 (%#lx), info2 (%#lx)", 1240 vmexit->inst_length, code, info1, info2)); 1241 1242 svm_update_virqinfo(svm_sc, vcpu); 1243 svm_save_intinfo(svm_sc, vcpu); 1244 1245 switch (code) { 1246 case VMCB_EXIT_IRET: 1247 /* 1248 * Restart execution at "iret" but with the intercept cleared. 1249 */ 1250 vmexit->inst_length = 0; 1251 clear_nmi_blocking(svm_sc, vcpu); 1252 handled = 1; 1253 break; 1254 case VMCB_EXIT_VINTR: /* interrupt window exiting */ 1255 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_VINTR, 1); 1256 handled = 1; 1257 break; 1258 case VMCB_EXIT_INTR: /* external interrupt */ 1259 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_EXTINT, 1); 1260 handled = 1; 1261 break; 1262 case VMCB_EXIT_NMI: /* external NMI */ 1263 handled = 1; 1264 break; 1265 case 0x40 ... 0x5F: 1266 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_EXCEPTION, 1); 1267 reflect = 1; 1268 idtvec = code - 0x40; 1269 switch (idtvec) { 1270 case IDT_MC: 1271 /* 1272 * Call the machine check handler by hand. Also don't 1273 * reflect the machine check back into the guest. 1274 */ 1275 reflect = 0; 1276 VCPU_CTR0(svm_sc->vm, vcpu, "Vectoring to MCE handler"); 1277 __asm __volatile("int $18"); 1278 break; 1279 case IDT_PF: 1280 error = svm_setreg(svm_sc, vcpu, VM_REG_GUEST_CR2, 1281 info2); 1282 KASSERT(error == 0, ("%s: error %d updating cr2", 1283 __func__, error)); 1284 /* fallthru */ 1285 case IDT_NP: 1286 case IDT_SS: 1287 case IDT_GP: 1288 case IDT_AC: 1289 case IDT_TS: 1290 errcode_valid = 1; 1291 break; 1292 1293 case IDT_DF: 1294 errcode_valid = 1; 1295 info1 = 0; 1296 break; 1297 1298 case IDT_BP: 1299 case IDT_OF: 1300 case IDT_BR: 1301 /* 1302 * The 'nrip' field is populated for INT3, INTO and 1303 * BOUND exceptions and this also implies that 1304 * 'inst_length' is non-zero. 1305 * 1306 * Reset 'inst_length' to zero so the guest %rip at 1307 * event injection is identical to what it was when 1308 * the exception originally happened. 1309 */ 1310 VCPU_CTR2(svm_sc->vm, vcpu, "Reset inst_length from %d " 1311 "to zero before injecting exception %d", 1312 vmexit->inst_length, idtvec); 1313 vmexit->inst_length = 0; 1314 /* fallthru */ 1315 default: 1316 errcode_valid = 0; 1317 break; 1318 } 1319 KASSERT(vmexit->inst_length == 0, ("invalid inst_length (%d) " 1320 "when reflecting exception %d into guest", 1321 vmexit->inst_length, idtvec)); 1322 1323 if (reflect) { 1324 /* Reflect the exception back into the guest */ 1325 exception.vector = idtvec; 1326 exception.error_code_valid = errcode_valid; 1327 exception.error_code = errcode_valid ? info1 : 0; 1328 VCPU_CTR2(svm_sc->vm, vcpu, "Reflecting exception " 1329 "%d/%#x into the guest", exception.vector, 1330 exception.error_code); 1331 error = vm_inject_exception(svm_sc->vm, vcpu, 1332 &exception); 1333 KASSERT(error == 0, ("%s: vm_inject_exception error %d", 1334 __func__, error)); 1335 } 1336 handled = 1; 1337 break; 1338 case VMCB_EXIT_MSR: /* MSR access. */ 1339 eax = state->rax; 1340 ecx = ctx->sctx_rcx; 1341 edx = ctx->sctx_rdx; 1342 retu = false; 1343 1344 if (info1) { 1345 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_WRMSR, 1); 1346 val = (uint64_t)edx << 32 | eax; 1347 VCPU_CTR2(svm_sc->vm, vcpu, "wrmsr %#x val %#lx", 1348 ecx, val); 1349 if (emulate_wrmsr(svm_sc, vcpu, ecx, val, &retu)) { 1350 vmexit->exitcode = VM_EXITCODE_WRMSR; 1351 vmexit->u.msr.code = ecx; 1352 vmexit->u.msr.wval = val; 1353 } else if (!retu) { 1354 handled = 1; 1355 } else { 1356 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS, 1357 ("emulate_wrmsr retu with bogus exitcode")); 1358 } 1359 } else { 1360 VCPU_CTR1(svm_sc->vm, vcpu, "rdmsr %#x", ecx); 1361 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_RDMSR, 1); 1362 if (emulate_rdmsr(svm_sc, vcpu, ecx, &retu)) { 1363 vmexit->exitcode = VM_EXITCODE_RDMSR; 1364 vmexit->u.msr.code = ecx; 1365 } else if (!retu) { 1366 handled = 1; 1367 } else { 1368 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS, 1369 ("emulate_rdmsr retu with bogus exitcode")); 1370 } 1371 } 1372 break; 1373 case VMCB_EXIT_IO: 1374 handled = svm_handle_io(svm_sc, vcpu, vmexit); 1375 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_INOUT, 1); 1376 break; 1377 case VMCB_EXIT_CPUID: 1378 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_CPUID, 1); 1379 handled = x86_emulate_cpuid(svm_sc->vm, vcpu, 1380 (uint32_t *)&state->rax, 1381 (uint32_t *)&ctx->sctx_rbx, 1382 (uint32_t *)&ctx->sctx_rcx, 1383 (uint32_t *)&ctx->sctx_rdx); 1384 break; 1385 case VMCB_EXIT_HLT: 1386 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_HLT, 1); 1387 vmexit->exitcode = VM_EXITCODE_HLT; 1388 vmexit->u.hlt.rflags = state->rflags; 1389 break; 1390 case VMCB_EXIT_PAUSE: 1391 vmexit->exitcode = VM_EXITCODE_PAUSE; 1392 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_PAUSE, 1); 1393 break; 1394 case VMCB_EXIT_NPF: 1395 /* EXITINFO2 contains the faulting guest physical address */ 1396 if (info1 & VMCB_NPF_INFO1_RSV) { 1397 VCPU_CTR2(svm_sc->vm, vcpu, "nested page fault with " 1398 "reserved bits set: info1(%#lx) info2(%#lx)", 1399 info1, info2); 1400 } else if (vm_mem_allocated(svm_sc->vm, info2)) { 1401 vmexit->exitcode = VM_EXITCODE_PAGING; 1402 vmexit->u.paging.gpa = info2; 1403 vmexit->u.paging.fault_type = npf_fault_type(info1); 1404 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_NESTED_FAULT, 1); 1405 VCPU_CTR3(svm_sc->vm, vcpu, "nested page fault " 1406 "on gpa %#lx/%#lx at rip %#lx", 1407 info2, info1, state->rip); 1408 } else if (svm_npf_emul_fault(info1)) { 1409 svm_handle_inst_emul(vmcb, info2, vmexit); 1410 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_INST_EMUL, 1); 1411 VCPU_CTR3(svm_sc->vm, vcpu, "inst_emul fault " 1412 "for gpa %#lx/%#lx at rip %#lx", 1413 info2, info1, state->rip); 1414 } 1415 break; 1416 case VMCB_EXIT_MONITOR: 1417 vmexit->exitcode = VM_EXITCODE_MONITOR; 1418 break; 1419 case VMCB_EXIT_MWAIT: 1420 vmexit->exitcode = VM_EXITCODE_MWAIT; 1421 break; 1422 default: 1423 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_UNKNOWN, 1); 1424 break; 1425 } 1426 1427 VCPU_CTR4(svm_sc->vm, vcpu, "%s %s vmexit at %#lx/%d", 1428 handled ? "handled" : "unhandled", exit_reason_to_str(code), 1429 vmexit->rip, vmexit->inst_length); 1430 1431 if (handled) { 1432 vmexit->rip += vmexit->inst_length; 1433 vmexit->inst_length = 0; 1434 state->rip = vmexit->rip; 1435 } else { 1436 if (vmexit->exitcode == VM_EXITCODE_BOGUS) { 1437 /* 1438 * If this VM exit was not claimed by anybody then 1439 * treat it as a generic SVM exit. 1440 */ 1441 vm_exit_svm(vmexit, code, info1, info2); 1442 } else { 1443 /* 1444 * The exitcode and collateral have been populated. 1445 * The VM exit will be processed further in userland. 1446 */ 1447 } 1448 } 1449 return (handled); 1450} 1451 1452static void 1453svm_inj_intinfo(struct svm_softc *svm_sc, int vcpu) 1454{ 1455 uint64_t intinfo; 1456 1457 if (!vm_entry_intinfo(svm_sc->vm, vcpu, &intinfo)) 1458 return; 1459 1460 KASSERT(VMCB_EXITINTINFO_VALID(intinfo), ("%s: entry intinfo is not " 1461 "valid: %#lx", __func__, intinfo)); 1462 1463 svm_eventinject(svm_sc, vcpu, VMCB_EXITINTINFO_TYPE(intinfo), 1464 VMCB_EXITINTINFO_VECTOR(intinfo), 1465 VMCB_EXITINTINFO_EC(intinfo), 1466 VMCB_EXITINTINFO_EC_VALID(intinfo)); 1467 vmm_stat_incr(svm_sc->vm, vcpu, VCPU_INTINFO_INJECTED, 1); 1468 VCPU_CTR1(svm_sc->vm, vcpu, "Injected entry intinfo: %#lx", intinfo); 1469} 1470 1471/* 1472 * Inject event to virtual cpu. 1473 */ 1474static void 1475svm_inj_interrupts(struct svm_softc *sc, int vcpu, struct vlapic *vlapic) 1476{ 1477 struct vmcb_ctrl *ctrl; 1478 struct vmcb_state *state; 1479 uint8_t v_tpr; 1480 int vector, need_intr_window, pending_apic_vector; 1481 1482 state = svm_get_vmcb_state(sc, vcpu); 1483 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 1484 1485 need_intr_window = 0; 1486 pending_apic_vector = 0; 1487 1488 /* 1489 * Inject pending events or exceptions for this vcpu. 1490 * 1491 * An event might be pending because the previous #VMEXIT happened 1492 * during event delivery (i.e. ctrl->exitintinfo). 1493 * 1494 * An event might also be pending because an exception was injected 1495 * by the hypervisor (e.g. #PF during instruction emulation). 1496 */ 1497 svm_inj_intinfo(sc, vcpu); 1498 1499 /* NMI event has priority over interrupts. */ 1500 if (vm_nmi_pending(sc->vm, vcpu)) { 1501 if (nmi_blocked(sc, vcpu)) { 1502 /* 1503 * Can't inject another NMI if the guest has not 1504 * yet executed an "iret" after the last NMI. 1505 */ 1506 VCPU_CTR0(sc->vm, vcpu, "Cannot inject NMI due " 1507 "to NMI-blocking"); 1508 } else if (ctrl->intr_shadow) { 1509 /* 1510 * Can't inject an NMI if the vcpu is in an intr_shadow. 1511 */ 1512 VCPU_CTR0(sc->vm, vcpu, "Cannot inject NMI due to " 1513 "interrupt shadow"); 1514 need_intr_window = 1; 1515 goto done; 1516 } else if (ctrl->eventinj & VMCB_EVENTINJ_VALID) { 1517 /* 1518 * If there is already an exception/interrupt pending 1519 * then defer the NMI until after that. 1520 */ 1521 VCPU_CTR1(sc->vm, vcpu, "Cannot inject NMI due to " 1522 "eventinj %#lx", ctrl->eventinj); 1523 1524 /* 1525 * Use self-IPI to trigger a VM-exit as soon as 1526 * possible after the event injection is completed. 1527 * 1528 * This works only if the external interrupt exiting 1529 * is at a lower priority than the event injection. 1530 * 1531 * Although not explicitly specified in APMv2 the 1532 * relative priorities were verified empirically. 1533 */ 1534 ipi_cpu(curcpu, IPI_AST); /* XXX vmm_ipinum? */ 1535 } else { 1536 vm_nmi_clear(sc->vm, vcpu); 1537 1538 /* Inject NMI, vector number is not used */ 1539 svm_eventinject(sc, vcpu, VMCB_EVENTINJ_TYPE_NMI, 1540 IDT_NMI, 0, false); 1541 1542 /* virtual NMI blocking is now in effect */ 1543 enable_nmi_blocking(sc, vcpu); 1544 1545 VCPU_CTR0(sc->vm, vcpu, "Injecting vNMI"); 1546 } 1547 } 1548 1549 if (!vm_extint_pending(sc->vm, vcpu)) { 1550 /* 1551 * APIC interrupts are delivered using the V_IRQ offload. 1552 * 1553 * The primary benefit is that the hypervisor doesn't need to 1554 * deal with the various conditions that inhibit interrupts. 1555 * It also means that TPR changes via CR8 will be handled 1556 * without any hypervisor involvement. 1557 * 1558 * Note that the APIC vector must remain pending in the vIRR 1559 * until it is confirmed that it was delivered to the guest. 1560 * This can be confirmed based on the value of V_IRQ at the 1561 * next #VMEXIT (1 = pending, 0 = delivered). 1562 * 1563 * Also note that it is possible that another higher priority 1564 * vector can become pending before this vector is delivered 1565 * to the guest. This is alright because vcpu_notify_event() 1566 * will send an IPI and force the vcpu to trap back into the 1567 * hypervisor. The higher priority vector will be injected on 1568 * the next VMRUN. 1569 */ 1570 if (vlapic_pending_intr(vlapic, &vector)) { 1571 KASSERT(vector >= 16 && vector <= 255, 1572 ("invalid vector %d from local APIC", vector)); 1573 pending_apic_vector = vector; 1574 } 1575 goto done; 1576 } 1577 1578 /* Ask the legacy pic for a vector to inject */ 1579 vatpic_pending_intr(sc->vm, &vector); 1580 KASSERT(vector >= 0 && vector <= 255, ("invalid vector %d from INTR", 1581 vector)); 1582 1583 /* 1584 * If the guest has disabled interrupts or is in an interrupt shadow 1585 * then we cannot inject the pending interrupt. 1586 */ 1587 if ((state->rflags & PSL_I) == 0) { 1588 VCPU_CTR2(sc->vm, vcpu, "Cannot inject vector %d due to " 1589 "rflags %#lx", vector, state->rflags); 1590 need_intr_window = 1; 1591 goto done; 1592 } 1593 1594 if (ctrl->intr_shadow) { 1595 VCPU_CTR1(sc->vm, vcpu, "Cannot inject vector %d due to " 1596 "interrupt shadow", vector); 1597 need_intr_window = 1; 1598 goto done; 1599 } 1600 1601 if (ctrl->eventinj & VMCB_EVENTINJ_VALID) { 1602 VCPU_CTR2(sc->vm, vcpu, "Cannot inject vector %d due to " 1603 "eventinj %#lx", vector, ctrl->eventinj); 1604 need_intr_window = 1; 1605 goto done; 1606 } 1607 1608 /* 1609 * Legacy PIC interrupts are delivered via the event injection 1610 * mechanism. 1611 */ 1612 svm_eventinject(sc, vcpu, VMCB_EVENTINJ_TYPE_INTR, vector, 0, false); 1613 1614 vm_extint_clear(sc->vm, vcpu); 1615 vatpic_intr_accepted(sc->vm, vector); 1616 1617 /* 1618 * Force a VM-exit as soon as the vcpu is ready to accept another 1619 * interrupt. This is done because the PIC might have another vector 1620 * that it wants to inject. Also, if the APIC has a pending interrupt 1621 * that was preempted by the ExtInt then it allows us to inject the 1622 * APIC vector as soon as possible. 1623 */ 1624 need_intr_window = 1; 1625done: 1626 /* 1627 * The guest can modify the TPR by writing to %CR8. In guest mode 1628 * the processor reflects this write to V_TPR without hypervisor 1629 * intervention. 1630 * 1631 * The guest can also modify the TPR by writing to it via the memory 1632 * mapped APIC page. In this case, the write will be emulated by the 1633 * hypervisor. For this reason V_TPR must be updated before every 1634 * VMRUN. 1635 */ 1636 v_tpr = vlapic_get_cr8(vlapic); 1637 KASSERT(v_tpr >= 0 && v_tpr <= 15, ("invalid v_tpr %#x", v_tpr)); 1638 if (ctrl->v_tpr != v_tpr) { 1639 VCPU_CTR2(sc->vm, vcpu, "VMCB V_TPR changed from %#x to %#x", 1640 ctrl->v_tpr, v_tpr); 1641 ctrl->v_tpr = v_tpr; 1642 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 1643 } 1644 1645 if (pending_apic_vector) { 1646 /* 1647 * If an APIC vector is being injected then interrupt window 1648 * exiting is not possible on this VMRUN. 1649 */ 1650 KASSERT(!need_intr_window, ("intr_window exiting impossible")); 1651 VCPU_CTR1(sc->vm, vcpu, "Injecting vector %d using V_IRQ", 1652 pending_apic_vector); 1653 1654 ctrl->v_irq = 1; 1655 ctrl->v_ign_tpr = 0; 1656 ctrl->v_intr_vector = pending_apic_vector; 1657 ctrl->v_intr_prio = pending_apic_vector >> 4; 1658 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 1659 } else if (need_intr_window) { 1660 /* 1661 * We use V_IRQ in conjunction with the VINTR intercept to 1662 * trap into the hypervisor as soon as a virtual interrupt 1663 * can be delivered. 1664 * 1665 * Since injected events are not subject to intercept checks 1666 * we need to ensure that the V_IRQ is not actually going to 1667 * be delivered on VM entry. The KASSERT below enforces this. 1668 */ 1669 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) != 0 || 1670 (state->rflags & PSL_I) == 0 || ctrl->intr_shadow, 1671 ("Bogus intr_window_exiting: eventinj (%#lx), " 1672 "intr_shadow (%u), rflags (%#lx)", 1673 ctrl->eventinj, ctrl->intr_shadow, state->rflags)); 1674 enable_intr_window_exiting(sc, vcpu); 1675 } else { 1676 disable_intr_window_exiting(sc, vcpu); 1677 } 1678} 1679 1680static __inline void 1681restore_host_tss(void) 1682{ 1683 struct system_segment_descriptor *tss_sd; 1684 1685 /* 1686 * The TSS descriptor was in use prior to launching the guest so it 1687 * has been marked busy. 1688 * 1689 * 'ltr' requires the descriptor to be marked available so change the 1690 * type to "64-bit available TSS". 1691 */ 1692 tss_sd = PCPU_GET(tss); 1693 tss_sd->sd_type = SDT_SYSTSS; 1694 ltr(GSEL(GPROC0_SEL, SEL_KPL)); 1695} 1696 1697static void 1698check_asid(struct svm_softc *sc, int vcpuid, pmap_t pmap, u_int thiscpu) 1699{ 1700 struct svm_vcpu *vcpustate; 1701 struct vmcb_ctrl *ctrl; 1702 long eptgen; 1703 bool alloc_asid; 1704 1705 KASSERT(CPU_ISSET(thiscpu, &pmap->pm_active), ("%s: nested pmap not " 1706 "active on cpu %u", __func__, thiscpu)); 1707 1708 vcpustate = svm_get_vcpu(sc, vcpuid); 1709 ctrl = svm_get_vmcb_ctrl(sc, vcpuid); 1710 1711 /* 1712 * The TLB entries associated with the vcpu's ASID are not valid 1713 * if either of the following conditions is true: 1714 * 1715 * 1. The vcpu's ASID generation is different than the host cpu's 1716 * ASID generation. This happens when the vcpu migrates to a new 1717 * host cpu. It can also happen when the number of vcpus executing 1718 * on a host cpu is greater than the number of ASIDs available. 1719 * 1720 * 2. The pmap generation number is different than the value cached in 1721 * the 'vcpustate'. This happens when the host invalidates pages 1722 * belonging to the guest. 1723 * 1724 * asidgen eptgen Action 1725 * mismatch mismatch 1726 * 0 0 (a) 1727 * 0 1 (b1) or (b2) 1728 * 1 0 (c) 1729 * 1 1 (d) 1730 * 1731 * (a) There is no mismatch in eptgen or ASID generation and therefore 1732 * no further action is needed. 1733 * 1734 * (b1) If the cpu supports FlushByAsid then the vcpu's ASID is 1735 * retained and the TLB entries associated with this ASID 1736 * are flushed by VMRUN. 1737 * 1738 * (b2) If the cpu does not support FlushByAsid then a new ASID is 1739 * allocated. 1740 * 1741 * (c) A new ASID is allocated. 1742 * 1743 * (d) A new ASID is allocated. 1744 */ 1745 1746 alloc_asid = false; 1747 eptgen = pmap->pm_eptgen; 1748 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_NOTHING; 1749 1750 if (vcpustate->asid.gen != asid[thiscpu].gen) { 1751 alloc_asid = true; /* (c) and (d) */ 1752 } else if (vcpustate->eptgen != eptgen) { 1753 if (flush_by_asid()) 1754 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST; /* (b1) */ 1755 else 1756 alloc_asid = true; /* (b2) */ 1757 } else { 1758 /* 1759 * This is the common case (a). 1760 */ 1761 KASSERT(!alloc_asid, ("ASID allocation not necessary")); 1762 KASSERT(ctrl->tlb_ctrl == VMCB_TLB_FLUSH_NOTHING, 1763 ("Invalid VMCB tlb_ctrl: %#x", ctrl->tlb_ctrl)); 1764 } 1765 1766 if (alloc_asid) { 1767 if (++asid[thiscpu].num >= nasid) { 1768 asid[thiscpu].num = 1; 1769 if (++asid[thiscpu].gen == 0) 1770 asid[thiscpu].gen = 1; 1771 /* 1772 * If this cpu does not support "flush-by-asid" 1773 * then flush the entire TLB on a generation 1774 * bump. Subsequent ASID allocation in this 1775 * generation can be done without a TLB flush. 1776 */ 1777 if (!flush_by_asid()) 1778 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_ALL; 1779 } 1780 vcpustate->asid.gen = asid[thiscpu].gen; 1781 vcpustate->asid.num = asid[thiscpu].num; 1782 1783 ctrl->asid = vcpustate->asid.num; 1784 svm_set_dirty(sc, vcpuid, VMCB_CACHE_ASID); 1785 /* 1786 * If this cpu supports "flush-by-asid" then the TLB 1787 * was not flushed after the generation bump. The TLB 1788 * is flushed selectively after every new ASID allocation. 1789 */ 1790 if (flush_by_asid()) 1791 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST; 1792 } 1793 vcpustate->eptgen = eptgen; 1794 1795 KASSERT(ctrl->asid != 0, ("Guest ASID must be non-zero")); 1796 KASSERT(ctrl->asid == vcpustate->asid.num, 1797 ("ASID mismatch: %u/%u", ctrl->asid, vcpustate->asid.num)); 1798} 1799 1800static __inline void 1801disable_gintr(void) 1802{ 1803 1804 __asm __volatile("clgi" : : :); 1805} 1806 1807static __inline void 1808enable_gintr(void) 1809{ 1810 1811 __asm __volatile("stgi" : : :); 1812} 1813 1814/* 1815 * Start vcpu with specified RIP. 1816 */ 1817static int 1818svm_vmrun(void *arg, int vcpu, register_t rip, pmap_t pmap, 1819 void *rend_cookie, void *suspended_cookie) 1820{ 1821 struct svm_regctx *gctx; 1822 struct svm_softc *svm_sc; 1823 struct svm_vcpu *vcpustate; 1824 struct vmcb_state *state; 1825 struct vmcb_ctrl *ctrl; 1826 struct vm_exit *vmexit; 1827 struct vlapic *vlapic; 1828 struct vm *vm; 1829 uint64_t vmcb_pa; 1830 u_int thiscpu; 1831 int handled; 1832 1833 svm_sc = arg; 1834 vm = svm_sc->vm; 1835 1836 vcpustate = svm_get_vcpu(svm_sc, vcpu); 1837 state = svm_get_vmcb_state(svm_sc, vcpu); 1838 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu); 1839 vmexit = vm_exitinfo(vm, vcpu); 1840 vlapic = vm_lapic(vm, vcpu); 1841 1842 /* 1843 * Stash 'curcpu' on the stack as 'thiscpu'. 1844 * 1845 * The per-cpu data area is not accessible until MSR_GSBASE is restored 1846 * after the #VMEXIT. Since VMRUN is executed inside a critical section 1847 * 'curcpu' and 'thiscpu' are guaranteed to identical. 1848 */ 1849 thiscpu = curcpu; 1850 1851 gctx = svm_get_guest_regctx(svm_sc, vcpu); 1852 vmcb_pa = svm_sc->vcpu[vcpu].vmcb_pa; 1853 1854 if (vcpustate->lastcpu != thiscpu) { 1855 /* 1856 * Force new ASID allocation by invalidating the generation. 1857 */ 1858 vcpustate->asid.gen = 0; 1859 1860 /* 1861 * Invalidate the VMCB state cache by marking all fields dirty. 1862 */ 1863 svm_set_dirty(svm_sc, vcpu, 0xffffffff); 1864 1865 /* 1866 * XXX 1867 * Setting 'vcpustate->lastcpu' here is bit premature because 1868 * we may return from this function without actually executing 1869 * the VMRUN instruction. This could happen if a rendezvous 1870 * or an AST is pending on the first time through the loop. 1871 * 1872 * This works for now but any new side-effects of vcpu 1873 * migration should take this case into account. 1874 */ 1875 vcpustate->lastcpu = thiscpu; 1876 vmm_stat_incr(vm, vcpu, VCPU_MIGRATIONS, 1); 1877 } 1878 1879 svm_msr_guest_enter(svm_sc, vcpu); 1880 1881 /* Update Guest RIP */ 1882 state->rip = rip; 1883 1884 do { 1885 /* 1886 * Disable global interrupts to guarantee atomicity during 1887 * loading of guest state. This includes not only the state 1888 * loaded by the "vmrun" instruction but also software state 1889 * maintained by the hypervisor: suspended and rendezvous 1890 * state, NPT generation number, vlapic interrupts etc. 1891 */ 1892 disable_gintr(); 1893 1894 if (vcpu_suspended(suspended_cookie)) { 1895 enable_gintr(); 1896 vm_exit_suspended(vm, vcpu, state->rip); 1897 break; 1898 } 1899 1900 if (vcpu_rendezvous_pending(rend_cookie)) { 1901 enable_gintr(); 1902 vm_exit_rendezvous(vm, vcpu, state->rip); 1903 break; 1904 } 1905 1906 /* We are asked to give the cpu by scheduler. */ 1907 if (curthread->td_flags & (TDF_ASTPENDING | TDF_NEEDRESCHED)) { 1908 enable_gintr(); 1909 vm_exit_astpending(vm, vcpu, state->rip); 1910 break; 1911 } 1912 1913 svm_inj_interrupts(svm_sc, vcpu, vlapic); 1914 1915 /* Activate the nested pmap on 'thiscpu' */ 1916 CPU_SET_ATOMIC_ACQ(thiscpu, &pmap->pm_active); 1917 1918 /* 1919 * Check the pmap generation and the ASID generation to 1920 * ensure that the vcpu does not use stale TLB mappings. 1921 */ 1922 check_asid(svm_sc, vcpu, pmap, thiscpu); 1923 1924 ctrl->vmcb_clean = vmcb_clean & ~vcpustate->dirty; 1925 vcpustate->dirty = 0; 1926 VCPU_CTR1(vm, vcpu, "vmcb clean %#x", ctrl->vmcb_clean); 1927 1928 /* Launch Virtual Machine. */ 1929 VCPU_CTR1(vm, vcpu, "Resume execution at %#lx", state->rip); 1930 svm_launch(vmcb_pa, gctx); 1931 1932 CPU_CLR_ATOMIC(thiscpu, &pmap->pm_active); 1933 1934 /* 1935 * Restore MSR_GSBASE to point to the pcpu data area. 1936 * 1937 * Note that accesses done via PCPU_GET/PCPU_SET will work 1938 * only after MSR_GSBASE is restored. 1939 * 1940 * Also note that we don't bother restoring MSR_KGSBASE 1941 * since it is not used in the kernel and will be restored 1942 * when the VMRUN ioctl returns to userspace. 1943 */ 1944 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[thiscpu]); 1945 KASSERT(curcpu == thiscpu, ("thiscpu/curcpu (%u/%u) mismatch", 1946 thiscpu, curcpu)); 1947 1948 /* 1949 * The host GDTR and IDTR is saved by VMRUN and restored 1950 * automatically on #VMEXIT. However, the host TSS needs 1951 * to be restored explicitly. 1952 */ 1953 restore_host_tss(); 1954 1955 /* #VMEXIT disables interrupts so re-enable them here. */ 1956 enable_gintr(); 1957 1958 /* Handle #VMEXIT and if required return to user space. */ 1959 handled = svm_vmexit(svm_sc, vcpu, vmexit); 1960 } while (handled); 1961 1962 svm_msr_guest_exit(svm_sc, vcpu); 1963 1964 return (0); 1965} 1966 1967static void 1968svm_vmcleanup(void *arg) 1969{ 1970 struct svm_softc *sc = arg; 1971 1972 free(sc, M_SVM); 1973} 1974 1975static register_t * 1976swctx_regptr(struct svm_regctx *regctx, int reg) 1977{ 1978 1979 switch (reg) { 1980 case VM_REG_GUEST_RBX: 1981 return (®ctx->sctx_rbx); 1982 case VM_REG_GUEST_RCX: 1983 return (®ctx->sctx_rcx); 1984 case VM_REG_GUEST_RDX: 1985 return (®ctx->sctx_rdx); 1986 case VM_REG_GUEST_RDI: 1987 return (®ctx->sctx_rdi); 1988 case VM_REG_GUEST_RSI: 1989 return (®ctx->sctx_rsi); 1990 case VM_REG_GUEST_RBP: 1991 return (®ctx->sctx_rbp); 1992 case VM_REG_GUEST_R8: 1993 return (®ctx->sctx_r8); 1994 case VM_REG_GUEST_R9: 1995 return (®ctx->sctx_r9); 1996 case VM_REG_GUEST_R10: 1997 return (®ctx->sctx_r10); 1998 case VM_REG_GUEST_R11: 1999 return (®ctx->sctx_r11); 2000 case VM_REG_GUEST_R12: 2001 return (®ctx->sctx_r12); 2002 case VM_REG_GUEST_R13: 2003 return (®ctx->sctx_r13); 2004 case VM_REG_GUEST_R14: 2005 return (®ctx->sctx_r14); 2006 case VM_REG_GUEST_R15: 2007 return (®ctx->sctx_r15); 2008 default: 2009 return (NULL); 2010 } 2011} 2012 2013static int 2014svm_getreg(void *arg, int vcpu, int ident, uint64_t *val) 2015{ 2016 struct svm_softc *svm_sc; 2017 register_t *reg; 2018 2019 svm_sc = arg; 2020 2021 if (ident == VM_REG_GUEST_INTR_SHADOW) { 2022 return (svm_get_intr_shadow(svm_sc, vcpu, val)); 2023 } 2024 2025 if (vmcb_read(svm_sc, vcpu, ident, val) == 0) { 2026 return (0); 2027 } 2028 2029 reg = swctx_regptr(svm_get_guest_regctx(svm_sc, vcpu), ident); 2030 2031 if (reg != NULL) { 2032 *val = *reg; 2033 return (0); 2034 } 2035 2036 VCPU_CTR1(svm_sc->vm, vcpu, "svm_getreg: unknown register %#x", ident); 2037 return (EINVAL); 2038} 2039 2040static int 2041svm_setreg(void *arg, int vcpu, int ident, uint64_t val) 2042{ 2043 struct svm_softc *svm_sc; 2044 register_t *reg; 2045 2046 svm_sc = arg; 2047 2048 if (ident == VM_REG_GUEST_INTR_SHADOW) { 2049 return (svm_modify_intr_shadow(svm_sc, vcpu, val)); 2050 } 2051 2052 if (vmcb_write(svm_sc, vcpu, ident, val) == 0) { 2053 return (0); 2054 } 2055 2056 reg = swctx_regptr(svm_get_guest_regctx(svm_sc, vcpu), ident); 2057 2058 if (reg != NULL) { 2059 *reg = val; 2060 return (0); 2061 } 2062 2063 /* 2064 * XXX deal with CR3 and invalidate TLB entries tagged with the 2065 * vcpu's ASID. This needs to be treated differently depending on 2066 * whether 'running' is true/false. 2067 */ 2068 2069 VCPU_CTR1(svm_sc->vm, vcpu, "svm_setreg: unknown register %#x", ident); 2070 return (EINVAL); 2071} 2072 2073static int 2074svm_setcap(void *arg, int vcpu, int type, int val) 2075{ 2076 struct svm_softc *sc; 2077 int error; 2078 2079 sc = arg; 2080 error = 0; 2081 switch (type) { 2082 case VM_CAP_HALT_EXIT: 2083 svm_set_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2084 VMCB_INTCPT_HLT, val); 2085 break; 2086 case VM_CAP_PAUSE_EXIT: 2087 svm_set_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2088 VMCB_INTCPT_PAUSE, val); 2089 break; 2090 case VM_CAP_UNRESTRICTED_GUEST: 2091 /* Unrestricted guest execution cannot be disabled in SVM */ 2092 if (val == 0) 2093 error = EINVAL; 2094 break; 2095 default: 2096 error = ENOENT; 2097 break; 2098 } 2099 return (error); 2100} 2101 2102static int 2103svm_getcap(void *arg, int vcpu, int type, int *retval) 2104{ 2105 struct svm_softc *sc; 2106 int error; 2107 2108 sc = arg; 2109 error = 0; 2110 2111 switch (type) { 2112 case VM_CAP_HALT_EXIT: 2113 *retval = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2114 VMCB_INTCPT_HLT); 2115 break; 2116 case VM_CAP_PAUSE_EXIT: 2117 *retval = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2118 VMCB_INTCPT_PAUSE); 2119 break; 2120 case VM_CAP_UNRESTRICTED_GUEST: 2121 *retval = 1; /* unrestricted guest is always enabled */ 2122 break; 2123 default: 2124 error = ENOENT; 2125 break; 2126 } 2127 return (error); 2128} 2129 2130static struct vlapic * 2131svm_vlapic_init(void *arg, int vcpuid) 2132{ 2133 struct svm_softc *svm_sc; 2134 struct vlapic *vlapic; 2135 2136 svm_sc = arg; 2137 vlapic = malloc(sizeof(struct vlapic), M_SVM_VLAPIC, M_WAITOK | M_ZERO); 2138 vlapic->vm = svm_sc->vm; 2139 vlapic->vcpuid = vcpuid; 2140 vlapic->apic_page = (struct LAPIC *)&svm_sc->apic_page[vcpuid]; 2141 2142 vlapic_init(vlapic); 2143 2144 return (vlapic); 2145} 2146 2147static void 2148svm_vlapic_cleanup(void *arg, struct vlapic *vlapic) 2149{ 2150 2151 vlapic_cleanup(vlapic); 2152 free(vlapic, M_SVM_VLAPIC); 2153} 2154 2155struct vmm_ops vmm_ops_amd = { 2156 svm_init, 2157 svm_cleanup, 2158 svm_restore, 2159 svm_vminit, 2160 svm_vmrun, 2161 svm_vmcleanup, 2162 svm_getreg, 2163 svm_setreg, 2164 vmcb_getdesc, 2165 vmcb_setdesc, 2166 svm_getcap, 2167 svm_setcap, 2168 svm_npt_alloc, 2169 svm_npt_free, 2170 svm_vlapic_init, 2171 svm_vlapic_cleanup 2172}; 2173