vmm_instruction_emul.h revision 267399 
1/*-
2 * Copyright (c) 2012 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/sys/amd64/include/vmm_instruction_emul.h 267399 2014-06-12 15:20:59Z jhb $
27 */
28
29#ifndef	_VMM_INSTRUCTION_EMUL_H_
30#define	_VMM_INSTRUCTION_EMUL_H_
31
32enum vie_cpu_mode {
33	CPU_MODE_COMPATIBILITY,		/* IA-32E mode (CS.L = 0) */
34	CPU_MODE_64BIT,			/* IA-32E mode (CS.L = 1) */
35};
36
37enum vie_paging_mode {
38	PAGING_MODE_FLAT,
39	PAGING_MODE_32,
40	PAGING_MODE_PAE,
41	PAGING_MODE_64,
42};
43
44/*
45 * The data structures 'vie' and 'vie_op' are meant to be opaque to the
46 * consumers of instruction decoding. The only reason why their contents
47 * need to be exposed is because they are part of the 'vm_exit' structure.
48 */
49struct vie_op {
50	uint8_t		op_byte;	/* actual opcode byte */
51	uint8_t		op_type;	/* type of operation (e.g. MOV) */
52	uint16_t	op_flags;
53};
54
55#define	VIE_INST_SIZE	15
56struct vie {
57	uint8_t		inst[VIE_INST_SIZE];	/* instruction bytes */
58	uint8_t		num_valid;		/* size of the instruction */
59	uint8_t		num_processed;
60
61	uint8_t		rex_w:1,		/* REX prefix */
62			rex_r:1,
63			rex_x:1,
64			rex_b:1,
65			rex_present:1;
66
67	uint8_t		mod:2,			/* ModRM byte */
68			reg:4,
69			rm:4;
70
71	uint8_t		ss:2,			/* SIB byte */
72			index:4,
73			base:4;
74
75	uint8_t		disp_bytes;
76	uint8_t		imm_bytes;
77
78	uint8_t		scale;
79	int		base_register;		/* VM_REG_GUEST_xyz */
80	int		index_register;		/* VM_REG_GUEST_xyz */
81
82	int64_t		displacement;		/* optional addr displacement */
83	int64_t		immediate;		/* optional immediate operand */
84
85	uint8_t		decoded;	/* set to 1 if successfully decoded */
86
87	struct vie_op	op;			/* opcode description */
88};
89
90/*
91 * Callback functions to read and write memory regions.
92 */
93typedef int (*mem_region_read_t)(void *vm, int cpuid, uint64_t gpa,
94				 uint64_t *rval, int rsize, void *arg);
95
96typedef int (*mem_region_write_t)(void *vm, int cpuid, uint64_t gpa,
97				  uint64_t wval, int wsize, void *arg);
98
99/*
100 * Emulate the decoded 'vie' instruction.
101 *
102 * The callbacks 'mrr' and 'mrw' emulate reads and writes to the memory region
103 * containing 'gpa'. 'mrarg' is an opaque argument that is passed into the
104 * callback functions.
105 *
106 * 'void *vm' should be 'struct vm *' when called from kernel context and
107 * 'struct vmctx *' when called from user context.
108 * s
109 */
110int vmm_emulate_instruction(void *vm, int cpuid, uint64_t gpa, struct vie *vie,
111			    mem_region_read_t mrr, mem_region_write_t mrw,
112			    void *mrarg);
113
114#ifdef _KERNEL
115/*
116 * APIs to fetch and decode the instruction from nested page fault handler.
117 *
118 * 'vie' must be initialized before calling 'vmm_fetch_instruction()'
119 */
120int vmm_fetch_instruction(struct vm *vm, int cpuid,
121			  uint64_t rip, int inst_length, uint64_t cr3,
122			  enum vie_paging_mode paging_mode, struct vie *vie);
123
124void vie_init(struct vie *vie);
125
126/*
127 * Decode the instruction fetched into 'vie' so it can be emulated.
128 *
129 * 'gla' is the guest linear address provided by the hardware assist
130 * that caused the nested page table fault. It is used to verify that
131 * the software instruction decoding is in agreement with the hardware.
132 *
133 * Some hardware assists do not provide the 'gla' to the hypervisor.
134 * To skip the 'gla' verification for this or any other reason pass
135 * in VIE_INVALID_GLA instead.
136 */
137#define	VIE_INVALID_GLA		(1UL << 63)	/* a non-canonical address */
138int vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla,
139			   enum vie_cpu_mode cpu_mode, struct vie *vie);
140#endif	/* _KERNEL */
141
142#endif	/* _VMM_INSTRUCTION_EMUL_H_ */
143