vmm_instruction_emul.h revision 259073
1142425Snectar/*- 2160814Ssimon * Copyright (c) 2012 NetApp, Inc. 3142425Snectar * All rights reserved. 4142425Snectar * 5142425Snectar * Redistribution and use in source and binary forms, with or without 6142425Snectar * modification, are permitted provided that the following conditions 7142425Snectar * are met: 8142425Snectar * 1. Redistributions of source code must retain the above copyright 9142425Snectar * notice, this list of conditions and the following disclaimer. 10142425Snectar * 2. Redistributions in binary form must reproduce the above copyright 11142425Snectar * notice, this list of conditions and the following disclaimer in the 12142425Snectar * documentation and/or other materials provided with the distribution. 13142425Snectar * 14142425Snectar * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15142425Snectar * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16142425Snectar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17142425Snectar * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18142425Snectar * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19142425Snectar * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20142425Snectar * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21142425Snectar * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22142425Snectar * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23142425Snectar * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24142425Snectar * SUCH DAMAGE. 25142425Snectar * 26142425Snectar * $FreeBSD: stable/10/sys/amd64/include/vmm_instruction_emul.h 259073 2013-12-07 18:23:29Z peter $ 27142425Snectar */ 28142425Snectar 29142425Snectar#ifndef _VMM_INSTRUCTION_EMUL_H_ 30142425Snectar#define _VMM_INSTRUCTION_EMUL_H_ 31142425Snectar 32142425Snectar/* 33142425Snectar * The data structures 'vie' and 'vie_op' are meant to be opaque to the 34142425Snectar * consumers of instruction decoding. The only reason why their contents 35142425Snectar * need to be exposed is because they are part of the 'vm_exit' structure. 36142425Snectar */ 37142425Snectarstruct vie_op { 38142425Snectar uint8_t op_byte; /* actual opcode byte */ 39238405Sjkim uint8_t op_type; /* type of operation (e.g. MOV) */ 40142425Snectar uint16_t op_flags; 41142425Snectar}; 42142425Snectar 43142425Snectar#define VIE_INST_SIZE 15 44142425Snectarstruct vie { 45142425Snectar uint8_t inst[VIE_INST_SIZE]; /* instruction bytes */ 46142425Snectar uint8_t num_valid; /* size of the instruction */ 47142425Snectar uint8_t num_processed; 48142425Snectar 49142425Snectar uint8_t rex_w:1, /* REX prefix */ 50142425Snectar rex_r:1, 51142425Snectar rex_x:1, 52160814Ssimon rex_b:1, 53160814Ssimon rex_present:1; 54142425Snectar 55142425Snectar uint8_t mod:2, /* ModRM byte */ 56142425Snectar reg:4, 57142425Snectar rm:4; 58142425Snectar 59142425Snectar uint8_t ss:2, /* SIB byte */ 60142425Snectar index:4, 61142425Snectar base:4; 62142425Snectar 63142425Snectar uint8_t disp_bytes; 64142425Snectar uint8_t imm_bytes; 65142425Snectar 66142425Snectar uint8_t scale; 67284283Sjkim int base_register; /* VM_REG_GUEST_xyz */ 68284283Sjkim int index_register; /* VM_REG_GUEST_xyz */ 69142425Snectar 70160814Ssimon int64_t displacement; /* optional addr displacement */ 71142425Snectar int64_t immediate; /* optional immediate operand */ 72142425Snectar 73142425Snectar uint8_t decoded; /* set to 1 if successfully decoded */ 74142425Snectar 75142425Snectar struct vie_op op; /* opcode description */ 76142425Snectar}; 77142425Snectar 78142425Snectar/* 79142425Snectar * Callback functions to read and write memory regions. 80142425Snectar */ 81142425Snectartypedef int (*mem_region_read_t)(void *vm, int cpuid, uint64_t gpa, 82142425Snectar uint64_t *rval, int rsize, void *arg); 83160814Ssimon 84160814Ssimontypedef int (*mem_region_write_t)(void *vm, int cpuid, uint64_t gpa, 85160814Ssimon uint64_t wval, int wsize, void *arg); 86160814Ssimon 87160814Ssimon/* 88160814Ssimon * Emulate the decoded 'vie' instruction. 89142425Snectar * 90160814Ssimon * The callbacks 'mrr' and 'mrw' emulate reads and writes to the memory region 91160814Ssimon * containing 'gpa'. 'mrarg' is an opaque argument that is passed into the 92160814Ssimon * callback functions. 93160814Ssimon * 94160814Ssimon * 'void *vm' should be 'struct vm *' when called from kernel context and 95160814Ssimon * 'struct vmctx *' when called from user context. 96160814Ssimon * s 97142425Snectar */ 98142425Snectarint vmm_emulate_instruction(void *vm, int cpuid, uint64_t gpa, struct vie *vie, 99142425Snectar mem_region_read_t mrr, mem_region_write_t mrw, 100142425Snectar void *mrarg); 101160814Ssimon 102160814Ssimon#ifdef _KERNEL 103160814Ssimon/* 104142425Snectar * APIs to fetch and decode the instruction from nested page fault handler. 105160814Ssimon * 106160814Ssimon * 'vie' must be initialized before calling 'vmm_fetch_instruction()' 107160814Ssimon */ 108142425Snectarint vmm_fetch_instruction(struct vm *vm, int cpuid, 109142425Snectar uint64_t rip, int inst_length, uint64_t cr3, 110142425Snectar struct vie *vie); 111 112void vie_init(struct vie *vie); 113 114/* 115 * Decode the instruction fetched into 'vie' so it can be emulated. 116 * 117 * 'gla' is the guest linear address provided by the hardware assist 118 * that caused the nested page table fault. It is used to verify that 119 * the software instruction decoding is in agreement with the hardware. 120 * 121 * Some hardware assists do not provide the 'gla' to the hypervisor. 122 * To skip the 'gla' verification for this or any other reason pass 123 * in VIE_INVALID_GLA instead. 124 */ 125#define VIE_INVALID_GLA (1UL << 63) /* a non-canonical address */ 126int vmm_decode_instruction(struct vm *vm, int cpuid, 127 uint64_t gla, struct vie *vie); 128#endif /* _KERNEL */ 129 130#endif /* _VMM_INSTRUCTION_EMUL_H_ */ 131