apicvar.h revision 262192
1/*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/amd64/include/apicvar.h 262192 2014-02-18 20:27:17Z jhb $ 27 */ 28 29#ifndef _MACHINE_APICVAR_H_ 30#define _MACHINE_APICVAR_H_ 31 32#include <machine/segments.h> 33 34/* 35 * Local && I/O APIC variable definitions. 36 */ 37 38/* 39 * Layout of local APIC interrupt vectors: 40 * 41 * 0xff (255) +-------------+ 42 * | | 15 (Spurious / IPIs / Local Interrupts) 43 * 0xf0 (240) +-------------+ 44 * | | 14 (I/O Interrupts / Timer) 45 * 0xe0 (224) +-------------+ 46 * | | 13 (I/O Interrupts) 47 * 0xd0 (208) +-------------+ 48 * | | 12 (I/O Interrupts) 49 * 0xc0 (192) +-------------+ 50 * | | 11 (I/O Interrupts) 51 * 0xb0 (176) +-------------+ 52 * | | 10 (I/O Interrupts) 53 * 0xa0 (160) +-------------+ 54 * | | 9 (I/O Interrupts) 55 * 0x90 (144) +-------------+ 56 * | | 8 (I/O Interrupts / System Calls) 57 * 0x80 (128) +-------------+ 58 * | | 7 (I/O Interrupts) 59 * 0x70 (112) +-------------+ 60 * | | 6 (I/O Interrupts) 61 * 0x60 (96) +-------------+ 62 * | | 5 (I/O Interrupts) 63 * 0x50 (80) +-------------+ 64 * | | 4 (I/O Interrupts) 65 * 0x40 (64) +-------------+ 66 * | | 3 (I/O Interrupts) 67 * 0x30 (48) +-------------+ 68 * | | 2 (ATPIC Interrupts) 69 * 0x20 (32) +-------------+ 70 * | | 1 (Exceptions, traps, faults, etc.) 71 * 0x10 (16) +-------------+ 72 * | | 0 (Exceptions, traps, faults, etc.) 73 * 0x00 (0) +-------------+ 74 * 75 * Note: 0x80 needs to be handled specially and not allocated to an 76 * I/O device! 77 */ 78 79#define MAX_APIC_ID 0xfe 80#define APIC_ID_ALL 0xff 81 82/* I/O Interrupts are used for external devices such as ISA, PCI, etc. */ 83#define APIC_IO_INTS (IDT_IO_INTS + 16) 84#define APIC_NUM_IOINTS 191 85 86/* The timer interrupt is used for clock handling and drives hardclock, etc. */ 87#define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS) 88 89/* 90 ********************* !!! WARNING !!! ****************************** 91 * Each local apic has an interrupt receive fifo that is two entries deep 92 * for each interrupt priority class (higher 4 bits of interrupt vector). 93 * Once the fifo is full the APIC can no longer receive interrupts for this 94 * class and sending IPIs from other CPUs will be blocked. 95 * To avoid deadlocks there should be no more than two IPI interrupts 96 * pending at the same time. 97 * Currently this is guaranteed by dividing the IPIs in two groups that have 98 * each at most one IPI interrupt pending. The first group is protected by the 99 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 100 * at a time) The second group uses a single interrupt and a bitmap to avoid 101 * redundant IPI interrupts. 102 */ 103 104/* Interrupts for local APIC LVT entries other than the timer. */ 105#define APIC_LOCAL_INTS 240 106#define APIC_ERROR_INT APIC_LOCAL_INTS 107#define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 108#define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 109 110#define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 111#define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 112#define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */ 113#define IPI_INVLPG (APIC_IPI_INTS + 2) 114#define IPI_INVLRNG (APIC_IPI_INTS + 3) 115#define IPI_INVLCACHE (APIC_IPI_INTS + 4) 116/* Vector to handle bitmap based IPIs */ 117#define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 6) 118 119/* IPIs handled by IPI_BITMAPED_VECTOR (XXX ups is there a better place?) */ 120#define IPI_AST 0 /* Generate software trap. */ 121#define IPI_PREEMPT 1 122#define IPI_HARDCLOCK 2 123#define IPI_BITMAP_LAST IPI_HARDCLOCK 124#define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 125 126#define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */ 127#define IPI_SUSPEND (APIC_IPI_INTS + 8) /* Suspend CPU until restarted. */ 128#define IPI_STOP_HARD (APIC_IPI_INTS + 9) /* Stop CPU with a NMI. */ 129 130/* 131 * The spurious interrupt can share the priority class with the IPIs since 132 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo) 133 */ 134#define APIC_SPURIOUS_INT 255 135 136#ifndef LOCORE 137 138#define APIC_IPI_DEST_SELF -1 139#define APIC_IPI_DEST_ALL -2 140#define APIC_IPI_DEST_OTHERS -3 141 142#define APIC_BUS_UNKNOWN -1 143#define APIC_BUS_ISA 0 144#define APIC_BUS_EISA 1 145#define APIC_BUS_PCI 2 146#define APIC_BUS_MAX APIC_BUS_PCI 147 148/* 149 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including 150 * CPU's and I/O APIC's. 151 */ 152struct apic_enumerator { 153 const char *apic_name; 154 int (*apic_probe)(void); 155 int (*apic_probe_cpus)(void); 156 int (*apic_setup_local)(void); 157 int (*apic_setup_io)(void); 158 SLIST_ENTRY(apic_enumerator) apic_next; 159}; 160 161inthand_t 162 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), 163 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), 164 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), 165 IDTVEC(spuriousint), IDTVEC(timerint); 166 167extern vm_paddr_t lapic_paddr; 168extern int apic_cpuids[]; 169 170u_int apic_alloc_vector(u_int apic_id, u_int irq); 171u_int apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, 172 u_int align); 173void apic_disable_vector(u_int apic_id, u_int vector); 174void apic_enable_vector(u_int apic_id, u_int vector); 175void apic_free_vector(u_int apic_id, u_int vector, u_int irq); 176u_int apic_idt_to_irq(u_int apic_id, u_int vector); 177void apic_register_enumerator(struct apic_enumerator *enumerator); 178u_int apic_cpuid(u_int apic_id); 179void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase); 180int ioapic_disable_pin(void *cookie, u_int pin); 181int ioapic_get_vector(void *cookie, u_int pin); 182void ioapic_register(void *cookie); 183int ioapic_remap_vector(void *cookie, u_int pin, int vector); 184int ioapic_set_bus(void *cookie, u_int pin, int bus_type); 185int ioapic_set_extint(void *cookie, u_int pin); 186int ioapic_set_nmi(void *cookie, u_int pin); 187int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol); 188int ioapic_set_triggermode(void *cookie, u_int pin, 189 enum intr_trigger trigger); 190int ioapic_set_smi(void *cookie, u_int pin); 191void lapic_create(u_int apic_id, int boot_cpu); 192void lapic_disable(void); 193void lapic_disable_pmc(void); 194void lapic_dump(const char *str); 195void lapic_enable_cmc(void); 196int lapic_enable_pmc(void); 197void lapic_eoi(void); 198int lapic_id(void); 199void lapic_init(vm_paddr_t addr); 200int lapic_intr_pending(u_int vector); 201void lapic_ipi_raw(register_t icrlo, u_int dest); 202void lapic_ipi_vectored(u_int vector, int dest); 203int lapic_ipi_wait(int delay); 204void lapic_handle_cmc(void); 205void lapic_handle_error(void); 206void lapic_handle_intr(int vector, struct trapframe *frame); 207void lapic_handle_timer(struct trapframe *frame); 208void lapic_reenable_pmc(void); 209void lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id); 210int lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked); 211int lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode); 212int lapic_set_lvt_polarity(u_int apic_id, u_int lvt, 213 enum intr_polarity pol); 214int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, 215 enum intr_trigger trigger); 216void lapic_set_tpr(u_int vector); 217void lapic_setup(int boot); 218void xen_intr_handle_upcall(struct trapframe *frame); 219 220#endif /* !LOCORE */ 221#endif /* _MACHINE_APICVAR_H_ */ 222