mp_machdep.c revision 264118
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * Copyright (c) 2003, by Peter Wemm 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/amd64/amd64/mp_machdep.c 264118 2014-04-04 14:54:54Z royger $"); 29 30#include "opt_cpu.h" 31#include "opt_ddb.h" 32#include "opt_kstack_pages.h" 33#include "opt_sched.h" 34#include "opt_smp.h" 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/cpuset.h> 40#ifdef GPROF 41#include <sys/gmon.h> 42#endif 43#include <sys/kernel.h> 44#include <sys/ktr.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/memrange.h> 48#include <sys/mutex.h> 49#include <sys/pcpu.h> 50#include <sys/proc.h> 51#include <sys/sched.h> 52#include <sys/smp.h> 53#include <sys/sysctl.h> 54 55#include <vm/vm.h> 56#include <vm/vm_param.h> 57#include <vm/pmap.h> 58#include <vm/vm_kern.h> 59#include <vm/vm_extern.h> 60 61#include <x86/apicreg.h> 62#include <machine/clock.h> 63#include <machine/cputypes.h> 64#include <machine/cpufunc.h> 65#include <x86/mca.h> 66#include <machine/md_var.h> 67#include <machine/pcb.h> 68#include <machine/psl.h> 69#include <machine/smp.h> 70#include <machine/specialreg.h> 71#include <machine/tss.h> 72#include <machine/cpu.h> 73 74#define WARMBOOT_TARGET 0 75#define WARMBOOT_OFF (KERNBASE + 0x0467) 76#define WARMBOOT_SEG (KERNBASE + 0x0469) 77 78#define CMOS_REG (0x70) 79#define CMOS_DATA (0x71) 80#define BIOS_RESET (0x0f) 81#define BIOS_WARM (0x0a) 82 83/* lock region used by kernel profiling */ 84int mcount_lock; 85 86int mp_naps; /* # of Applications processors */ 87int boot_cpu_id = -1; /* designated BSP */ 88 89extern struct pcpu __pcpu[]; 90 91/* AP uses this during bootstrap. Do not staticize. */ 92char *bootSTK; 93static int bootAP; 94 95/* Free these after use */ 96void *bootstacks[MAXCPU]; 97 98/* Temporary variables for init_secondary() */ 99char *doublefault_stack; 100char *nmi_stack; 101void *dpcpu; 102 103struct pcb stoppcbs[MAXCPU]; 104struct pcb **susppcbs; 105 106/* Variables needed for SMP tlb shootdown. */ 107vm_offset_t smp_tlb_addr2; 108struct invpcid_descr smp_tlb_invpcid; 109volatile int smp_tlb_wait; 110uint64_t pcid_cr3; 111pmap_t smp_tlb_pmap; 112extern int invpcid_works; 113 114#ifdef COUNT_IPIS 115/* Interrupt counts. */ 116static u_long *ipi_preempt_counts[MAXCPU]; 117static u_long *ipi_ast_counts[MAXCPU]; 118u_long *ipi_invltlb_counts[MAXCPU]; 119u_long *ipi_invlrng_counts[MAXCPU]; 120u_long *ipi_invlpg_counts[MAXCPU]; 121u_long *ipi_invlcache_counts[MAXCPU]; 122u_long *ipi_rendezvous_counts[MAXCPU]; 123static u_long *ipi_hardclock_counts[MAXCPU]; 124#endif 125 126/* Default cpu_ops implementation. */ 127struct cpu_ops cpu_ops = { 128 .ipi_vectored = lapic_ipi_vectored 129}; 130 131extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 132 133extern int pmap_pcid_enabled; 134 135/* 136 * Local data and functions. 137 */ 138 139static volatile cpuset_t ipi_nmi_pending; 140 141/* used to hold the AP's until we are ready to release them */ 142static struct mtx ap_boot_mtx; 143 144/* Set to 1 once we're ready to let the APs out of the pen. */ 145static volatile int aps_ready = 0; 146 147/* 148 * Store data from cpu_add() until later in the boot when we actually setup 149 * the APs. 150 */ 151struct cpu_info { 152 int cpu_present:1; 153 int cpu_bsp:1; 154 int cpu_disabled:1; 155 int cpu_hyperthread:1; 156} static cpu_info[MAX_APIC_ID + 1]; 157int cpu_apic_ids[MAXCPU]; 158int apic_cpuids[MAX_APIC_ID + 1]; 159 160/* Holds pending bitmap based IPIs per CPU */ 161volatile u_int cpu_ipi_pending[MAXCPU]; 162 163static u_int boot_address; 164static int cpu_logical; /* logical cpus per core */ 165static int cpu_cores; /* cores per package */ 166 167static void assign_cpu_ids(void); 168static void set_interrupt_apic_ids(void); 169static int start_all_aps(void); 170static int start_ap(int apic_id); 171static void release_aps(void *dummy); 172 173static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */ 174static int hyperthreading_allowed = 1; 175static u_int bootMP_size; 176 177static void 178mem_range_AP_init(void) 179{ 180 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 181 mem_range_softc.mr_op->initAP(&mem_range_softc); 182} 183 184static void 185topo_probe_amd(void) 186{ 187 int core_id_bits; 188 int id; 189 190 /* AMD processors do not support HTT. */ 191 cpu_logical = 1; 192 193 if ((amd_feature2 & AMDID2_CMP) == 0) { 194 cpu_cores = 1; 195 return; 196 } 197 198 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >> 199 AMDID_COREID_SIZE_SHIFT; 200 if (core_id_bits == 0) { 201 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 202 return; 203 } 204 205 /* Fam 10h and newer should get here. */ 206 for (id = 0; id <= MAX_APIC_ID; id++) { 207 /* Check logical CPU availability. */ 208 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 209 continue; 210 /* Check if logical CPU has the same package ID. */ 211 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits)) 212 continue; 213 cpu_cores++; 214 } 215} 216 217/* 218 * Round up to the next power of two, if necessary, and then 219 * take log2. 220 * Returns -1 if argument is zero. 221 */ 222static __inline int 223mask_width(u_int x) 224{ 225 226 return (fls(x << (1 - powerof2(x))) - 1); 227} 228 229static void 230topo_probe_0x4(void) 231{ 232 u_int p[4]; 233 int pkg_id_bits; 234 int core_id_bits; 235 int max_cores; 236 int max_logical; 237 int id; 238 239 /* Both zero and one here mean one logical processor per package. */ 240 max_logical = (cpu_feature & CPUID_HTT) != 0 ? 241 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1; 242 if (max_logical <= 1) 243 return; 244 245 /* 246 * Because of uniformity assumption we examine only 247 * those logical processors that belong to the same 248 * package as BSP. Further, we count number of 249 * logical processors that belong to the same core 250 * as BSP thus deducing number of threads per core. 251 */ 252 if (cpu_high >= 0x4) { 253 cpuid_count(0x04, 0, p); 254 max_cores = ((p[0] >> 26) & 0x3f) + 1; 255 } else 256 max_cores = 1; 257 core_id_bits = mask_width(max_logical/max_cores); 258 if (core_id_bits < 0) 259 return; 260 pkg_id_bits = core_id_bits + mask_width(max_cores); 261 262 for (id = 0; id <= MAX_APIC_ID; id++) { 263 /* Check logical CPU availability. */ 264 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 265 continue; 266 /* Check if logical CPU has the same package ID. */ 267 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits)) 268 continue; 269 cpu_cores++; 270 /* Check if logical CPU has the same package and core IDs. */ 271 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits)) 272 cpu_logical++; 273 } 274 275 KASSERT(cpu_cores >= 1 && cpu_logical >= 1, 276 ("topo_probe_0x4 couldn't find BSP")); 277 278 cpu_cores /= cpu_logical; 279 hyperthreading_cpus = cpu_logical; 280} 281 282static void 283topo_probe_0xb(void) 284{ 285 u_int p[4]; 286 int bits; 287 int cnt; 288 int i; 289 int logical; 290 int type; 291 int x; 292 293 /* We only support three levels for now. */ 294 for (i = 0; i < 3; i++) { 295 cpuid_count(0x0b, i, p); 296 297 /* Fall back if CPU leaf 11 doesn't really exist. */ 298 if (i == 0 && p[1] == 0) { 299 topo_probe_0x4(); 300 return; 301 } 302 303 bits = p[0] & 0x1f; 304 logical = p[1] &= 0xffff; 305 type = (p[2] >> 8) & 0xff; 306 if (type == 0 || logical == 0) 307 break; 308 /* 309 * Because of uniformity assumption we examine only 310 * those logical processors that belong to the same 311 * package as BSP. 312 */ 313 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) { 314 if (!cpu_info[x].cpu_present || 315 cpu_info[x].cpu_disabled) 316 continue; 317 if (x >> bits == boot_cpu_id >> bits) 318 cnt++; 319 } 320 if (type == CPUID_TYPE_SMT) 321 cpu_logical = cnt; 322 else if (type == CPUID_TYPE_CORE) 323 cpu_cores = cnt; 324 } 325 if (cpu_logical == 0) 326 cpu_logical = 1; 327 cpu_cores /= cpu_logical; 328} 329 330/* 331 * Both topology discovery code and code that consumes topology 332 * information assume top-down uniformity of the topology. 333 * That is, all physical packages must be identical and each 334 * core in a package must have the same number of threads. 335 * Topology information is queried only on BSP, on which this 336 * code runs and for which it can query CPUID information. 337 * Then topology is extrapolated on all packages using the 338 * uniformity assumption. 339 */ 340static void 341topo_probe(void) 342{ 343 static int cpu_topo_probed = 0; 344 345 if (cpu_topo_probed) 346 return; 347 348 CPU_ZERO(&logical_cpus_mask); 349 if (mp_ncpus <= 1) 350 cpu_cores = cpu_logical = 1; 351 else if (cpu_vendor_id == CPU_VENDOR_AMD) 352 topo_probe_amd(); 353 else if (cpu_vendor_id == CPU_VENDOR_INTEL) { 354 /* 355 * See Intel(R) 64 Architecture Processor 356 * Topology Enumeration article for details. 357 * 358 * Note that 0x1 <= cpu_high < 4 case should be 359 * compatible with topo_probe_0x4() logic when 360 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1) 361 * or it should trigger the fallback otherwise. 362 */ 363 if (cpu_high >= 0xb) 364 topo_probe_0xb(); 365 else if (cpu_high >= 0x1) 366 topo_probe_0x4(); 367 } 368 369 /* 370 * Fallback: assume each logical CPU is in separate 371 * physical package. That is, no multi-core, no SMT. 372 */ 373 if (cpu_cores == 0 || cpu_logical == 0) 374 cpu_cores = cpu_logical = 1; 375 cpu_topo_probed = 1; 376} 377 378struct cpu_group * 379cpu_topo(void) 380{ 381 int cg_flags; 382 383 /* 384 * Determine whether any threading flags are 385 * necessry. 386 */ 387 topo_probe(); 388 if (cpu_logical > 1 && hyperthreading_cpus) 389 cg_flags = CG_FLAG_HTT; 390 else if (cpu_logical > 1) 391 cg_flags = CG_FLAG_SMT; 392 else 393 cg_flags = 0; 394 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 395 printf("WARNING: Non-uniform processors.\n"); 396 printf("WARNING: Using suboptimal topology.\n"); 397 return (smp_topo_none()); 398 } 399 /* 400 * No multi-core or hyper-threaded. 401 */ 402 if (cpu_logical * cpu_cores == 1) 403 return (smp_topo_none()); 404 /* 405 * Only HTT no multi-core. 406 */ 407 if (cpu_logical > 1 && cpu_cores == 1) 408 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags)); 409 /* 410 * Only multi-core no HTT. 411 */ 412 if (cpu_cores > 1 && cpu_logical == 1) 413 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags)); 414 /* 415 * Both HTT and multi-core. 416 */ 417 return (smp_topo_2level(CG_SHARE_L2, cpu_cores, 418 CG_SHARE_L1, cpu_logical, cg_flags)); 419} 420 421/* 422 * Calculate usable address in base memory for AP trampoline code. 423 */ 424u_int 425mp_bootaddress(u_int basemem) 426{ 427 428 bootMP_size = mptramp_end - mptramp_start; 429 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 430 if (((basemem * 1024) - boot_address) < bootMP_size) 431 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 432 /* 3 levels of page table pages */ 433 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 434 435 return mptramp_pagetables; 436} 437 438void 439cpu_add(u_int apic_id, char boot_cpu) 440{ 441 442 if (apic_id > MAX_APIC_ID) { 443 panic("SMP: APIC ID %d too high", apic_id); 444 return; 445 } 446 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 447 apic_id)); 448 cpu_info[apic_id].cpu_present = 1; 449 if (boot_cpu) { 450 KASSERT(boot_cpu_id == -1, 451 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 452 boot_cpu_id)); 453 boot_cpu_id = apic_id; 454 cpu_info[apic_id].cpu_bsp = 1; 455 } 456 if (mp_ncpus < MAXCPU) { 457 mp_ncpus++; 458 mp_maxid = mp_ncpus - 1; 459 } 460 if (bootverbose) 461 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 462 "AP"); 463} 464 465void 466cpu_mp_setmaxid(void) 467{ 468 469 /* 470 * mp_maxid should be already set by calls to cpu_add(). 471 * Just sanity check its value here. 472 */ 473 if (mp_ncpus == 0) 474 KASSERT(mp_maxid == 0, 475 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 476 else if (mp_ncpus == 1) 477 mp_maxid = 0; 478 else 479 KASSERT(mp_maxid >= mp_ncpus - 1, 480 ("%s: counters out of sync: max %d, count %d", __func__, 481 mp_maxid, mp_ncpus)); 482} 483 484int 485cpu_mp_probe(void) 486{ 487 488 /* 489 * Always record BSP in CPU map so that the mbuf init code works 490 * correctly. 491 */ 492 CPU_SETOF(0, &all_cpus); 493 if (mp_ncpus == 0) { 494 /* 495 * No CPUs were found, so this must be a UP system. Setup 496 * the variables to represent a system with a single CPU 497 * with an id of 0. 498 */ 499 mp_ncpus = 1; 500 return (0); 501 } 502 503 /* At least one CPU was found. */ 504 if (mp_ncpus == 1) { 505 /* 506 * One CPU was found, so this must be a UP system with 507 * an I/O APIC. 508 */ 509 mp_maxid = 0; 510 return (0); 511 } 512 513 /* At least two CPUs were found. */ 514 return (1); 515} 516 517/* 518 * Initialize the IPI handlers and start up the AP's. 519 */ 520void 521cpu_mp_start(void) 522{ 523 int i; 524 525 /* Initialize the logical ID to APIC ID table. */ 526 for (i = 0; i < MAXCPU; i++) { 527 cpu_apic_ids[i] = -1; 528 cpu_ipi_pending[i] = 0; 529 } 530 531 /* Install an inter-CPU IPI for TLB invalidation */ 532 if (pmap_pcid_enabled) { 533 setidt(IPI_INVLTLB, IDTVEC(invltlb_pcid), SDT_SYSIGT, 534 SEL_KPL, 0); 535 setidt(IPI_INVLPG, IDTVEC(invlpg_pcid), SDT_SYSIGT, 536 SEL_KPL, 0); 537 } else { 538 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0); 539 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0); 540 } 541 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0); 542 543 /* Install an inter-CPU IPI for cache invalidation. */ 544 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0); 545 546 /* Install an inter-CPU IPI for all-CPU rendezvous */ 547 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0); 548 549 /* Install generic inter-CPU IPI handler */ 550 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 551 SDT_SYSIGT, SEL_KPL, 0); 552 553 /* Install an inter-CPU IPI for CPU stop/restart */ 554 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0); 555 556 /* Install an inter-CPU IPI for CPU suspend/resume */ 557 setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0); 558 559 /* Set boot_cpu_id if needed. */ 560 if (boot_cpu_id == -1) { 561 boot_cpu_id = PCPU_GET(apic_id); 562 cpu_info[boot_cpu_id].cpu_bsp = 1; 563 } else 564 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 565 ("BSP's APIC ID doesn't match boot_cpu_id")); 566 567 /* Probe logical/physical core configuration. */ 568 topo_probe(); 569 570 assign_cpu_ids(); 571 572 /* Start each Application Processor */ 573 start_all_aps(); 574 575 set_interrupt_apic_ids(); 576} 577 578 579/* 580 * Print various information about the SMP system hardware and setup. 581 */ 582void 583cpu_mp_announce(void) 584{ 585 const char *hyperthread; 586 int i; 587 588 printf("FreeBSD/SMP: %d package(s) x %d core(s)", 589 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores); 590 if (hyperthreading_cpus > 1) 591 printf(" x %d HTT threads", cpu_logical); 592 else if (cpu_logical > 1) 593 printf(" x %d SMT threads", cpu_logical); 594 printf("\n"); 595 596 /* List active CPUs first. */ 597 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 598 for (i = 1; i < mp_ncpus; i++) { 599 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread) 600 hyperthread = "/HT"; 601 else 602 hyperthread = ""; 603 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread, 604 cpu_apic_ids[i]); 605 } 606 607 /* List disabled CPUs last. */ 608 for (i = 0; i <= MAX_APIC_ID; i++) { 609 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled) 610 continue; 611 if (cpu_info[i].cpu_hyperthread) 612 hyperthread = "/HT"; 613 else 614 hyperthread = ""; 615 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread, 616 i); 617 } 618} 619 620/* 621 * AP CPU's call this to initialize themselves. 622 */ 623void 624init_secondary(void) 625{ 626 struct pcpu *pc; 627 struct nmi_pcpu *np; 628 u_int64_t msr, cr0; 629 u_int cpuid; 630 int cpu, gsel_tss, x; 631 struct region_descriptor ap_gdt; 632 633 /* Set by the startup code for us to use */ 634 cpu = bootAP; 635 636 /* Init tss */ 637 common_tss[cpu] = common_tss[0]; 638 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */ 639 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) + 640 IOPAGES * PAGE_SIZE; 641 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE]; 642 643 /* The NMI stack runs on IST2. */ 644 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1; 645 common_tss[cpu].tss_ist2 = (long) np; 646 647 /* Prepare private GDT */ 648 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu]; 649 for (x = 0; x < NGDT; x++) { 650 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 651 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1)) 652 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]); 653 } 654 ssdtosyssd(&gdt_segs[GPROC0_SEL], 655 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]); 656 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 657 ap_gdt.rd_base = (long) &gdt[NGDT * cpu]; 658 lgdt(&ap_gdt); /* does magic intra-segment return */ 659 660 /* Get per-cpu data */ 661 pc = &__pcpu[cpu]; 662 663 /* prime data page for it to use */ 664 pcpu_init(pc, cpu, sizeof(struct pcpu)); 665 dpcpu_init(dpcpu, cpu); 666 pc->pc_apic_id = cpu_apic_ids[cpu]; 667 pc->pc_prvspace = pc; 668 pc->pc_curthread = 0; 669 pc->pc_tssp = &common_tss[cpu]; 670 pc->pc_commontssp = &common_tss[cpu]; 671 pc->pc_rsp0 = 0; 672 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu + 673 GPROC0_SEL]; 674 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL]; 675 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL]; 676 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu + 677 GUSERLDT_SEL]; 678 679 /* Save the per-cpu pointer for use by the NMI handler. */ 680 np->np_pcpu = (register_t) pc; 681 682 wrmsr(MSR_FSBASE, 0); /* User value */ 683 wrmsr(MSR_GSBASE, (u_int64_t)pc); 684 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */ 685 686 lidt(&r_idt); 687 688 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 689 ltr(gsel_tss); 690 691 /* 692 * Set to a known state: 693 * Set by mpboot.s: CR0_PG, CR0_PE 694 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 695 */ 696 cr0 = rcr0(); 697 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 698 load_cr0(cr0); 699 700 /* Set up the fast syscall stuff */ 701 msr = rdmsr(MSR_EFER) | EFER_SCE; 702 wrmsr(MSR_EFER, msr); 703 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 704 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 705 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 706 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 707 wrmsr(MSR_STAR, msr); 708 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 709 710 /* Disable local APIC just to be sure. */ 711 lapic_disable(); 712 713 /* signal our startup to the BSP. */ 714 mp_naps++; 715 716 /* Spin until the BSP releases the AP's. */ 717 while (!aps_ready) 718 ia32_pause(); 719 720 /* Initialize the PAT MSR. */ 721 pmap_init_pat(); 722 723 /* set up CPU registers and state */ 724 cpu_setregs(); 725 726 /* set up SSE/NX registers */ 727 initializecpu(); 728 729 /* set up FPU state on the AP */ 730 fpuinit(); 731 732 if (cpu_ops.cpu_init) 733 cpu_ops.cpu_init(); 734 735 /* A quick check from sanity claus */ 736 cpuid = PCPU_GET(cpuid); 737 if (PCPU_GET(apic_id) != lapic_id()) { 738 printf("SMP: cpuid = %d\n", cpuid); 739 printf("SMP: actual apic_id = %d\n", lapic_id()); 740 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 741 panic("cpuid mismatch! boom!!"); 742 } 743 744 /* Initialize curthread. */ 745 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 746 PCPU_SET(curthread, PCPU_GET(idlethread)); 747 748 mca_init(); 749 750 mtx_lock_spin(&ap_boot_mtx); 751 752 /* Init local apic for irq's */ 753 lapic_setup(1); 754 755 /* Set memory range attributes for this CPU to match the BSP */ 756 mem_range_AP_init(); 757 758 smp_cpus++; 759 760 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid); 761 printf("SMP: AP CPU #%d Launched!\n", cpuid); 762 763 /* Determine if we are a logical CPU. */ 764 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */ 765 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0) 766 CPU_SET(cpuid, &logical_cpus_mask); 767 768 if (bootverbose) 769 lapic_dump("AP"); 770 771 if (smp_cpus == mp_ncpus) { 772 /* enable IPI's, tlb shootdown, freezes etc */ 773 atomic_store_rel_int(&smp_started, 1); 774 smp_active = 1; /* historic */ 775 } 776 777 /* 778 * Enable global pages TLB extension 779 * This also implicitly flushes the TLB 780 */ 781 782 load_cr4(rcr4() | CR4_PGE); 783 if (pmap_pcid_enabled) 784 load_cr4(rcr4() | CR4_PCIDE); 785 load_ds(_udatasel); 786 load_es(_udatasel); 787 load_fs(_ufssel); 788 mtx_unlock_spin(&ap_boot_mtx); 789 790 /* Wait until all the AP's are up. */ 791 while (smp_started == 0) 792 ia32_pause(); 793 794 /* Start per-CPU event timers. */ 795 cpu_initclocks_ap(); 796 797 sched_throw(NULL); 798 799 panic("scheduler returned us to %s", __func__); 800 /* NOTREACHED */ 801} 802 803/******************************************************************* 804 * local functions and data 805 */ 806 807/* 808 * We tell the I/O APIC code about all the CPUs we want to receive 809 * interrupts. If we don't want certain CPUs to receive IRQs we 810 * can simply not tell the I/O APIC code about them in this function. 811 * We also do not tell it about the BSP since it tells itself about 812 * the BSP internally to work with UP kernels and on UP machines. 813 */ 814static void 815set_interrupt_apic_ids(void) 816{ 817 u_int i, apic_id; 818 819 for (i = 0; i < MAXCPU; i++) { 820 apic_id = cpu_apic_ids[i]; 821 if (apic_id == -1) 822 continue; 823 if (cpu_info[apic_id].cpu_bsp) 824 continue; 825 if (cpu_info[apic_id].cpu_disabled) 826 continue; 827 828 /* Don't let hyperthreads service interrupts. */ 829 if (hyperthreading_cpus > 1 && 830 apic_id % hyperthreading_cpus != 0) 831 continue; 832 833 intr_add_cpu(i); 834 } 835} 836 837/* 838 * Assign logical CPU IDs to local APICs. 839 */ 840static void 841assign_cpu_ids(void) 842{ 843 u_int i; 844 845 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 846 &hyperthreading_allowed); 847 848 /* Check for explicitly disabled CPUs. */ 849 for (i = 0; i <= MAX_APIC_ID; i++) { 850 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 851 continue; 852 853 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) { 854 cpu_info[i].cpu_hyperthread = 1; 855 856 /* 857 * Don't use HT CPU if it has been disabled by a 858 * tunable. 859 */ 860 if (hyperthreading_allowed == 0) { 861 cpu_info[i].cpu_disabled = 1; 862 continue; 863 } 864 } 865 866 /* Don't use this CPU if it has been disabled by a tunable. */ 867 if (resource_disabled("lapic", i)) { 868 cpu_info[i].cpu_disabled = 1; 869 continue; 870 } 871 } 872 873 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) { 874 hyperthreading_cpus = 0; 875 cpu_logical = 1; 876 } 877 878 /* 879 * Assign CPU IDs to local APIC IDs and disable any CPUs 880 * beyond MAXCPU. CPU 0 is always assigned to the BSP. 881 * 882 * To minimize confusion for userland, we attempt to number 883 * CPUs such that all threads and cores in a package are 884 * grouped together. For now we assume that the BSP is always 885 * the first thread in a package and just start adding APs 886 * starting with the BSP's APIC ID. 887 */ 888 mp_ncpus = 1; 889 cpu_apic_ids[0] = boot_cpu_id; 890 apic_cpuids[boot_cpu_id] = 0; 891 for (i = boot_cpu_id + 1; i != boot_cpu_id; 892 i == MAX_APIC_ID ? i = 0 : i++) { 893 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 894 cpu_info[i].cpu_disabled) 895 continue; 896 897 if (mp_ncpus < MAXCPU) { 898 cpu_apic_ids[mp_ncpus] = i; 899 apic_cpuids[i] = mp_ncpus; 900 mp_ncpus++; 901 } else 902 cpu_info[i].cpu_disabled = 1; 903 } 904 KASSERT(mp_maxid >= mp_ncpus - 1, 905 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 906 mp_ncpus)); 907} 908 909/* 910 * start each AP in our list 911 */ 912static int 913start_all_aps(void) 914{ 915 vm_offset_t va = boot_address + KERNBASE; 916 u_int64_t *pt4, *pt3, *pt2; 917 u_int32_t mpbioswarmvec; 918 int apic_id, cpu, i; 919 u_char mpbiosreason; 920 921 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 922 923 /* install the AP 1st level boot code */ 924 pmap_kenter(va, boot_address); 925 pmap_invalidate_page(kernel_pmap, va); 926 bcopy(mptramp_start, (void *)va, bootMP_size); 927 928 /* Locate the page tables, they'll be below the trampoline */ 929 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 930 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 931 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 932 933 /* Create the initial 1GB replicated page tables */ 934 for (i = 0; i < 512; i++) { 935 /* Each slot of the level 4 pages points to the same level 3 page */ 936 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 937 pt4[i] |= PG_V | PG_RW | PG_U; 938 939 /* Each slot of the level 3 pages points to the same level 2 page */ 940 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 941 pt3[i] |= PG_V | PG_RW | PG_U; 942 943 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 944 pt2[i] = i * (2 * 1024 * 1024); 945 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; 946 } 947 948 /* save the current value of the warm-start vector */ 949 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 950 outb(CMOS_REG, BIOS_RESET); 951 mpbiosreason = inb(CMOS_DATA); 952 953 /* setup a vector to our boot code */ 954 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 955 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 956 outb(CMOS_REG, BIOS_RESET); 957 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 958 959 /* start each AP */ 960 for (cpu = 1; cpu < mp_ncpus; cpu++) { 961 apic_id = cpu_apic_ids[cpu]; 962 963 /* allocate and set up an idle stack data page */ 964 bootstacks[cpu] = (void *)kmem_malloc(kernel_arena, 965 KSTACK_PAGES * PAGE_SIZE, M_WAITOK | M_ZERO); 966 doublefault_stack = (char *)kmem_malloc(kernel_arena, 967 PAGE_SIZE, M_WAITOK | M_ZERO); 968 nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE, 969 M_WAITOK | M_ZERO); 970 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 971 M_WAITOK | M_ZERO); 972 973 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8; 974 bootAP = cpu; 975 976 /* attempt to start the Application Processor */ 977 if (!start_ap(apic_id)) { 978 /* restore the warmstart vector */ 979 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 980 panic("AP #%d (PHY# %d) failed!", cpu, apic_id); 981 } 982 983 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */ 984 } 985 986 /* restore the warmstart vector */ 987 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 988 989 outb(CMOS_REG, BIOS_RESET); 990 outb(CMOS_DATA, mpbiosreason); 991 992 /* number of APs actually started */ 993 return mp_naps; 994} 995 996 997/* 998 * This function starts the AP (application processor) identified 999 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1000 * to accomplish this. This is necessary because of the nuances 1001 * of the different hardware we might encounter. It isn't pretty, 1002 * but it seems to work. 1003 */ 1004static int 1005start_ap(int apic_id) 1006{ 1007 int vector, ms; 1008 int cpus; 1009 1010 /* calculate the vector */ 1011 vector = (boot_address >> 12) & 0xff; 1012 1013 /* used as a watchpoint to signal AP startup */ 1014 cpus = mp_naps; 1015 1016 ipi_startup(apic_id, vector); 1017 1018 /* Wait up to 5 seconds for it to start. */ 1019 for (ms = 0; ms < 5000; ms++) { 1020 if (mp_naps > cpus) 1021 return 1; /* return SUCCESS */ 1022 DELAY(1000); 1023 } 1024 return 0; /* return FAILURE */ 1025} 1026 1027#ifdef COUNT_XINVLTLB_HITS 1028u_int xhits_gbl[MAXCPU]; 1029u_int xhits_pg[MAXCPU]; 1030u_int xhits_rng[MAXCPU]; 1031static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 1032SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 1033 sizeof(xhits_gbl), "IU", ""); 1034SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 1035 sizeof(xhits_pg), "IU", ""); 1036SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 1037 sizeof(xhits_rng), "IU", ""); 1038 1039u_int ipi_global; 1040u_int ipi_page; 1041u_int ipi_range; 1042u_int ipi_range_size; 1043SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 1044SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 1045SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 1046SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, 1047 &ipi_range_size, 0, ""); 1048 1049u_int ipi_masked_global; 1050u_int ipi_masked_page; 1051u_int ipi_masked_range; 1052u_int ipi_masked_range_size; 1053SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 1054 &ipi_masked_global, 0, ""); 1055SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 1056 &ipi_masked_page, 0, ""); 1057SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 1058 &ipi_masked_range, 0, ""); 1059SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 1060 &ipi_masked_range_size, 0, ""); 1061#endif /* COUNT_XINVLTLB_HITS */ 1062 1063/* 1064 * Init and startup IPI. 1065 */ 1066void 1067ipi_startup(int apic_id, int vector) 1068{ 1069 1070 /* 1071 * first we do an INIT IPI: this INIT IPI might be run, resetting 1072 * and running the target CPU. OR this INIT IPI might be latched (P5 1073 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1074 * ignored. 1075 */ 1076 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1077 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 1078 lapic_ipi_wait(-1); 1079 DELAY(10000); /* wait ~10mS */ 1080 1081 /* 1082 * next we do a STARTUP IPI: the previous INIT IPI might still be 1083 * latched, (P5 bug) this 1st STARTUP would then terminate 1084 * immediately, and the previously started INIT IPI would continue. OR 1085 * the previous INIT IPI has already run. and this STARTUP IPI will 1086 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1087 * will run. 1088 */ 1089 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1090 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1091 vector, apic_id); 1092 lapic_ipi_wait(-1); 1093 DELAY(200); /* wait ~200uS */ 1094 1095 /* 1096 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1097 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1098 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1099 * recognized after hardware RESET or INIT IPI. 1100 */ 1101 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1102 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1103 vector, apic_id); 1104 lapic_ipi_wait(-1); 1105 DELAY(200); /* wait ~200uS */ 1106} 1107 1108/* 1109 * Send an IPI to specified CPU handling the bitmap logic. 1110 */ 1111static void 1112ipi_send_cpu(int cpu, u_int ipi) 1113{ 1114 u_int bitmap, old_pending, new_pending; 1115 1116 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu)); 1117 1118 if (IPI_IS_BITMAPED(ipi)) { 1119 bitmap = 1 << ipi; 1120 ipi = IPI_BITMAP_VECTOR; 1121 do { 1122 old_pending = cpu_ipi_pending[cpu]; 1123 new_pending = old_pending | bitmap; 1124 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu], 1125 old_pending, new_pending)); 1126 if (old_pending) 1127 return; 1128 } 1129 cpu_ops.ipi_vectored(ipi, cpu_apic_ids[cpu]); 1130} 1131 1132/* 1133 * Flush the TLB on all other CPU's 1134 */ 1135static void 1136smp_tlb_shootdown(u_int vector, pmap_t pmap, vm_offset_t addr1, 1137 vm_offset_t addr2) 1138{ 1139 u_int ncpu; 1140 1141 ncpu = mp_ncpus - 1; /* does not shootdown self */ 1142 if (ncpu < 1) 1143 return; /* no other cpus */ 1144 if (!(read_rflags() & PSL_I)) 1145 panic("%s: interrupts disabled", __func__); 1146 mtx_lock_spin(&smp_ipi_mtx); 1147 smp_tlb_invpcid.addr = addr1; 1148 if (pmap == NULL) { 1149 smp_tlb_invpcid.pcid = 0; 1150 } else { 1151 smp_tlb_invpcid.pcid = pmap->pm_pcid; 1152 pcid_cr3 = pmap->pm_cr3; 1153 } 1154 smp_tlb_addr2 = addr2; 1155 smp_tlb_pmap = pmap; 1156 atomic_store_rel_int(&smp_tlb_wait, 0); 1157 ipi_all_but_self(vector); 1158 while (smp_tlb_wait < ncpu) 1159 ia32_pause(); 1160 mtx_unlock_spin(&smp_ipi_mtx); 1161} 1162 1163static void 1164smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap, 1165 vm_offset_t addr1, vm_offset_t addr2) 1166{ 1167 int cpu, ncpu, othercpus; 1168 1169 othercpus = mp_ncpus - 1; 1170 if (CPU_ISFULLSET(&mask)) { 1171 if (othercpus < 1) 1172 return; 1173 } else { 1174 CPU_CLR(PCPU_GET(cpuid), &mask); 1175 if (CPU_EMPTY(&mask)) 1176 return; 1177 } 1178 if (!(read_rflags() & PSL_I)) 1179 panic("%s: interrupts disabled", __func__); 1180 mtx_lock_spin(&smp_ipi_mtx); 1181 smp_tlb_invpcid.addr = addr1; 1182 if (pmap == NULL) { 1183 smp_tlb_invpcid.pcid = 0; 1184 } else { 1185 smp_tlb_invpcid.pcid = pmap->pm_pcid; 1186 pcid_cr3 = pmap->pm_cr3; 1187 } 1188 smp_tlb_addr2 = addr2; 1189 smp_tlb_pmap = pmap; 1190 atomic_store_rel_int(&smp_tlb_wait, 0); 1191 if (CPU_ISFULLSET(&mask)) { 1192 ncpu = othercpus; 1193 ipi_all_but_self(vector); 1194 } else { 1195 ncpu = 0; 1196 while ((cpu = CPU_FFS(&mask)) != 0) { 1197 cpu--; 1198 CPU_CLR(cpu, &mask); 1199 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, 1200 cpu, vector); 1201 ipi_send_cpu(cpu, vector); 1202 ncpu++; 1203 } 1204 } 1205 while (smp_tlb_wait < ncpu) 1206 ia32_pause(); 1207 mtx_unlock_spin(&smp_ipi_mtx); 1208} 1209 1210void 1211smp_cache_flush(void) 1212{ 1213 1214 if (smp_started) 1215 smp_tlb_shootdown(IPI_INVLCACHE, NULL, 0, 0); 1216} 1217 1218void 1219smp_invltlb(pmap_t pmap) 1220{ 1221 1222 if (smp_started) { 1223 smp_tlb_shootdown(IPI_INVLTLB, pmap, 0, 0); 1224#ifdef COUNT_XINVLTLB_HITS 1225 ipi_global++; 1226#endif 1227 } 1228} 1229 1230void 1231smp_invlpg(pmap_t pmap, vm_offset_t addr) 1232{ 1233 1234 if (smp_started) { 1235 smp_tlb_shootdown(IPI_INVLPG, pmap, addr, 0); 1236#ifdef COUNT_XINVLTLB_HITS 1237 ipi_page++; 1238#endif 1239 } 1240} 1241 1242void 1243smp_invlpg_range(pmap_t pmap, vm_offset_t addr1, vm_offset_t addr2) 1244{ 1245 1246 if (smp_started) { 1247 smp_tlb_shootdown(IPI_INVLRNG, pmap, addr1, addr2); 1248#ifdef COUNT_XINVLTLB_HITS 1249 ipi_range++; 1250 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1251#endif 1252 } 1253} 1254 1255void 1256smp_masked_invltlb(cpuset_t mask, pmap_t pmap) 1257{ 1258 1259 if (smp_started) { 1260 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, NULL, 0, 0); 1261#ifdef COUNT_XINVLTLB_HITS 1262 ipi_masked_global++; 1263#endif 1264 } 1265} 1266 1267void 1268smp_masked_invlpg(cpuset_t mask, pmap_t pmap, vm_offset_t addr) 1269{ 1270 1271 if (smp_started) { 1272 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, pmap, addr, 0); 1273#ifdef COUNT_XINVLTLB_HITS 1274 ipi_masked_page++; 1275#endif 1276 } 1277} 1278 1279void 1280smp_masked_invlpg_range(cpuset_t mask, pmap_t pmap, vm_offset_t addr1, 1281 vm_offset_t addr2) 1282{ 1283 1284 if (smp_started) { 1285 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, pmap, addr1, 1286 addr2); 1287#ifdef COUNT_XINVLTLB_HITS 1288 ipi_masked_range++; 1289 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1290#endif 1291 } 1292} 1293 1294void 1295ipi_bitmap_handler(struct trapframe frame) 1296{ 1297 struct trapframe *oldframe; 1298 struct thread *td; 1299 int cpu = PCPU_GET(cpuid); 1300 u_int ipi_bitmap; 1301 1302 critical_enter(); 1303 td = curthread; 1304 td->td_intr_nesting_level++; 1305 oldframe = td->td_intr_frame; 1306 td->td_intr_frame = &frame; 1307 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1308 if (ipi_bitmap & (1 << IPI_PREEMPT)) { 1309#ifdef COUNT_IPIS 1310 (*ipi_preempt_counts[cpu])++; 1311#endif 1312 sched_preempt(td); 1313 } 1314 if (ipi_bitmap & (1 << IPI_AST)) { 1315#ifdef COUNT_IPIS 1316 (*ipi_ast_counts[cpu])++; 1317#endif 1318 /* Nothing to do for AST */ 1319 } 1320 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) { 1321#ifdef COUNT_IPIS 1322 (*ipi_hardclock_counts[cpu])++; 1323#endif 1324 hardclockintr(); 1325 } 1326 td->td_intr_frame = oldframe; 1327 td->td_intr_nesting_level--; 1328 critical_exit(); 1329} 1330 1331/* 1332 * send an IPI to a set of cpus. 1333 */ 1334void 1335ipi_selected(cpuset_t cpus, u_int ipi) 1336{ 1337 int cpu; 1338 1339 /* 1340 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1341 * of help in order to understand what is the source. 1342 * Set the mask of receiving CPUs for this purpose. 1343 */ 1344 if (ipi == IPI_STOP_HARD) 1345 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus); 1346 1347 while ((cpu = CPU_FFS(&cpus)) != 0) { 1348 cpu--; 1349 CPU_CLR(cpu, &cpus); 1350 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1351 ipi_send_cpu(cpu, ipi); 1352 } 1353} 1354 1355/* 1356 * send an IPI to a specific CPU. 1357 */ 1358void 1359ipi_cpu(int cpu, u_int ipi) 1360{ 1361 1362 /* 1363 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1364 * of help in order to understand what is the source. 1365 * Set the mask of receiving CPUs for this purpose. 1366 */ 1367 if (ipi == IPI_STOP_HARD) 1368 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending); 1369 1370 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1371 ipi_send_cpu(cpu, ipi); 1372} 1373 1374/* 1375 * send an IPI to all CPUs EXCEPT myself 1376 */ 1377void 1378ipi_all_but_self(u_int ipi) 1379{ 1380 cpuset_t other_cpus; 1381 1382 other_cpus = all_cpus; 1383 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 1384 1385 if (IPI_IS_BITMAPED(ipi)) { 1386 ipi_selected(other_cpus, ipi); 1387 return; 1388 } 1389 1390 /* 1391 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1392 * of help in order to understand what is the source. 1393 * Set the mask of receiving CPUs for this purpose. 1394 */ 1395 if (ipi == IPI_STOP_HARD) 1396 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus); 1397 1398 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1399 cpu_ops.ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1400} 1401 1402int 1403ipi_nmi_handler() 1404{ 1405 u_int cpuid; 1406 1407 /* 1408 * As long as there is not a simple way to know about a NMI's 1409 * source, if the bitmask for the current CPU is present in 1410 * the global pending bitword an IPI_STOP_HARD has been issued 1411 * and should be handled. 1412 */ 1413 cpuid = PCPU_GET(cpuid); 1414 if (!CPU_ISSET(cpuid, &ipi_nmi_pending)) 1415 return (1); 1416 1417 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending); 1418 cpustop_handler(); 1419 return (0); 1420} 1421 1422/* 1423 * Handle an IPI_STOP by saving our current context and spinning until we 1424 * are resumed. 1425 */ 1426void 1427cpustop_handler(void) 1428{ 1429 u_int cpu; 1430 1431 cpu = PCPU_GET(cpuid); 1432 1433 savectx(&stoppcbs[cpu]); 1434 1435 /* Indicate that we are stopped */ 1436 CPU_SET_ATOMIC(cpu, &stopped_cpus); 1437 1438 /* Wait for restart */ 1439 while (!CPU_ISSET(cpu, &started_cpus)) 1440 ia32_pause(); 1441 1442 CPU_CLR_ATOMIC(cpu, &started_cpus); 1443 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 1444 1445#ifdef DDB 1446 amd64_db_resume_dbreg(); 1447#endif 1448 1449 if (cpu == 0 && cpustop_restartfunc != NULL) { 1450 cpustop_restartfunc(); 1451 cpustop_restartfunc = NULL; 1452 } 1453} 1454 1455/* 1456 * Handle an IPI_SUSPEND by saving our current context and spinning until we 1457 * are resumed. 1458 */ 1459void 1460cpususpend_handler(void) 1461{ 1462 u_int cpu; 1463 1464 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED); 1465 1466 cpu = PCPU_GET(cpuid); 1467 if (savectx(susppcbs[cpu])) { 1468 fpususpend(susppcbs[cpu]->pcb_fpususpend); 1469 wbinvd(); 1470 CPU_SET_ATOMIC(cpu, &suspended_cpus); 1471 } else { 1472 pmap_init_pat(); 1473 initializecpu(); 1474 PCPU_SET(switchtime, 0); 1475 PCPU_SET(switchticks, ticks); 1476 1477 /* Indicate that we are resumed */ 1478 CPU_CLR_ATOMIC(cpu, &suspended_cpus); 1479 } 1480 1481 /* Wait for resume */ 1482 while (!CPU_ISSET(cpu, &started_cpus)) 1483 ia32_pause(); 1484 1485 if (cpu_ops.cpu_resume) 1486 cpu_ops.cpu_resume(); 1487 if (vmm_resume_p) 1488 vmm_resume_p(); 1489 1490 /* Resume MCA and local APIC */ 1491 mca_resume(); 1492 lapic_setup(0); 1493 1494 CPU_CLR_ATOMIC(cpu, &started_cpus); 1495 /* Indicate that we are resumed */ 1496 CPU_CLR_ATOMIC(cpu, &suspended_cpus); 1497} 1498 1499/* 1500 * Handlers for TLB related IPIs 1501 */ 1502void 1503invltlb_handler(void) 1504{ 1505#ifdef COUNT_XINVLTLB_HITS 1506 xhits_gbl[PCPU_GET(cpuid)]++; 1507#endif /* COUNT_XINVLTLB_HITS */ 1508#ifdef COUNT_IPIS 1509 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++; 1510#endif /* COUNT_IPIS */ 1511 1512 invltlb(); 1513 atomic_add_int(&smp_tlb_wait, 1); 1514} 1515 1516void 1517invltlb_pcid_handler(void) 1518{ 1519 uint64_t cr3; 1520#ifdef COUNT_XINVLTLB_HITS 1521 xhits_gbl[PCPU_GET(cpuid)]++; 1522#endif /* COUNT_XINVLTLB_HITS */ 1523#ifdef COUNT_IPIS 1524 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++; 1525#endif /* COUNT_IPIS */ 1526 1527 cr3 = rcr3(); 1528 if (smp_tlb_invpcid.pcid != (uint64_t)-1 && 1529 smp_tlb_invpcid.pcid != 0) { 1530 1531 if (invpcid_works) { 1532 invpcid(&smp_tlb_invpcid, INVPCID_CTX); 1533 } else { 1534 /* Otherwise reload %cr3 twice. */ 1535 if (cr3 != pcid_cr3) { 1536 load_cr3(pcid_cr3); 1537 cr3 |= CR3_PCID_SAVE; 1538 } 1539 load_cr3(cr3); 1540 } 1541 } else { 1542 invltlb_globpcid(); 1543 } 1544 if (smp_tlb_pmap != NULL) 1545 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &smp_tlb_pmap->pm_save); 1546 1547 atomic_add_int(&smp_tlb_wait, 1); 1548} 1549 1550void 1551invlpg_handler(void) 1552{ 1553#ifdef COUNT_XINVLTLB_HITS 1554 xhits_pg[PCPU_GET(cpuid)]++; 1555#endif /* COUNT_XINVLTLB_HITS */ 1556#ifdef COUNT_IPIS 1557 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++; 1558#endif /* COUNT_IPIS */ 1559 1560 invlpg(smp_tlb_invpcid.addr); 1561 atomic_add_int(&smp_tlb_wait, 1); 1562} 1563 1564void 1565invlpg_pcid_handler(void) 1566{ 1567#ifdef COUNT_XINVLTLB_HITS 1568 xhits_pg[PCPU_GET(cpuid)]++; 1569#endif /* COUNT_XINVLTLB_HITS */ 1570#ifdef COUNT_IPIS 1571 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++; 1572#endif /* COUNT_IPIS */ 1573 1574 if (invpcid_works) { 1575 invpcid(&smp_tlb_invpcid, INVPCID_ADDR); 1576 } else if (smp_tlb_invpcid.pcid == 0) { 1577 invlpg(smp_tlb_invpcid.addr); 1578 } else if (smp_tlb_invpcid.pcid == (uint64_t)-1) { 1579 invltlb_globpcid(); 1580 } else { 1581 uint64_t cr3; 1582 1583 /* 1584 * PCID supported, but INVPCID is not. 1585 * Temporarily switch to the target address 1586 * space and do INVLPG. 1587 */ 1588 cr3 = rcr3(); 1589 if (cr3 != pcid_cr3) 1590 load_cr3(pcid_cr3 | CR3_PCID_SAVE); 1591 invlpg(smp_tlb_invpcid.addr); 1592 load_cr3(cr3 | CR3_PCID_SAVE); 1593 } 1594 1595 atomic_add_int(&smp_tlb_wait, 1); 1596} 1597 1598static inline void 1599invlpg_range(vm_offset_t start, vm_offset_t end) 1600{ 1601 1602 do { 1603 invlpg(start); 1604 start += PAGE_SIZE; 1605 } while (start < end); 1606} 1607 1608void 1609invlrng_handler(void) 1610{ 1611 vm_offset_t addr; 1612#ifdef COUNT_XINVLTLB_HITS 1613 xhits_rng[PCPU_GET(cpuid)]++; 1614#endif /* COUNT_XINVLTLB_HITS */ 1615#ifdef COUNT_IPIS 1616 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++; 1617#endif /* COUNT_IPIS */ 1618 1619 addr = smp_tlb_invpcid.addr; 1620 if (pmap_pcid_enabled) { 1621 if (invpcid_works) { 1622 struct invpcid_descr d; 1623 1624 d = smp_tlb_invpcid; 1625 do { 1626 invpcid(&d, INVPCID_ADDR); 1627 d.addr += PAGE_SIZE; 1628 } while (d.addr < smp_tlb_addr2); 1629 } else if (smp_tlb_invpcid.pcid == 0) { 1630 /* 1631 * kernel pmap - use invlpg to invalidate 1632 * global mapping. 1633 */ 1634 invlpg_range(addr, smp_tlb_addr2); 1635 } else if (smp_tlb_invpcid.pcid == (uint64_t)-1) { 1636 invltlb_globpcid(); 1637 if (smp_tlb_pmap != NULL) { 1638 CPU_CLR_ATOMIC(PCPU_GET(cpuid), 1639 &smp_tlb_pmap->pm_save); 1640 } 1641 } else { 1642 uint64_t cr3; 1643 1644 cr3 = rcr3(); 1645 if (cr3 != pcid_cr3) 1646 load_cr3(pcid_cr3 | CR3_PCID_SAVE); 1647 invlpg_range(addr, smp_tlb_addr2); 1648 load_cr3(cr3 | CR3_PCID_SAVE); 1649 } 1650 } else { 1651 invlpg_range(addr, smp_tlb_addr2); 1652 } 1653 1654 atomic_add_int(&smp_tlb_wait, 1); 1655} 1656 1657void 1658invlcache_handler(void) 1659{ 1660#ifdef COUNT_IPIS 1661 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++; 1662#endif /* COUNT_IPIS */ 1663 1664 wbinvd(); 1665 atomic_add_int(&smp_tlb_wait, 1); 1666} 1667 1668/* 1669 * This is called once the rest of the system is up and running and we're 1670 * ready to let the AP's out of the pen. 1671 */ 1672static void 1673release_aps(void *dummy __unused) 1674{ 1675 1676 if (mp_ncpus == 1) 1677 return; 1678 atomic_store_rel_int(&aps_ready, 1); 1679 while (smp_started == 0) 1680 ia32_pause(); 1681} 1682SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1683 1684#ifdef COUNT_IPIS 1685/* 1686 * Setup interrupt counters for IPI handlers. 1687 */ 1688static void 1689mp_ipi_intrcnt(void *dummy) 1690{ 1691 char buf[64]; 1692 int i; 1693 1694 CPU_FOREACH(i) { 1695 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i); 1696 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1697 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i); 1698 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1699 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i); 1700 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1701 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i); 1702 intrcnt_add(buf, &ipi_invlcache_counts[i]); 1703 snprintf(buf, sizeof(buf), "cpu%d:preempt", i); 1704 intrcnt_add(buf, &ipi_preempt_counts[i]); 1705 snprintf(buf, sizeof(buf), "cpu%d:ast", i); 1706 intrcnt_add(buf, &ipi_ast_counts[i]); 1707 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i); 1708 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1709 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i); 1710 intrcnt_add(buf, &ipi_hardclock_counts[i]); 1711 } 1712} 1713SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL); 1714#endif 1715 1716