machdep.c revision 290731
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: stable/10/sys/amd64/amd64/machdep.c 290731 2015-11-12 23:49:47Z jhb $"); 43 44#include "opt_atalk.h" 45#include "opt_atpic.h" 46#include "opt_compat.h" 47#include "opt_cpu.h" 48#include "opt_ddb.h" 49#include "opt_inet.h" 50#include "opt_ipx.h" 51#include "opt_isa.h" 52#include "opt_kstack_pages.h" 53#include "opt_maxmem.h" 54#include "opt_mp_watchdog.h" 55#include "opt_perfmon.h" 56#include "opt_platform.h" 57#include "opt_sched.h" 58#include "opt_kdtrace.h" 59 60#include <sys/param.h> 61#include <sys/proc.h> 62#include <sys/systm.h> 63#include <sys/bio.h> 64#include <sys/buf.h> 65#include <sys/bus.h> 66#include <sys/callout.h> 67#include <sys/cons.h> 68#include <sys/cpu.h> 69#include <sys/efi.h> 70#include <sys/eventhandler.h> 71#include <sys/exec.h> 72#include <sys/imgact.h> 73#include <sys/kdb.h> 74#include <sys/kernel.h> 75#include <sys/ktr.h> 76#include <sys/linker.h> 77#include <sys/lock.h> 78#include <sys/malloc.h> 79#include <sys/memrange.h> 80#include <sys/msgbuf.h> 81#include <sys/mutex.h> 82#include <sys/pcpu.h> 83#include <sys/ptrace.h> 84#include <sys/reboot.h> 85#include <sys/rwlock.h> 86#include <sys/sched.h> 87#include <sys/signalvar.h> 88#ifdef SMP 89#include <sys/smp.h> 90#endif 91#include <sys/syscallsubr.h> 92#include <sys/sysctl.h> 93#include <sys/sysent.h> 94#include <sys/sysproto.h> 95#include <sys/ucontext.h> 96#include <sys/vmmeter.h> 97 98#include <vm/vm.h> 99#include <vm/vm_extern.h> 100#include <vm/vm_kern.h> 101#include <vm/vm_page.h> 102#include <vm/vm_map.h> 103#include <vm/vm_object.h> 104#include <vm/vm_pager.h> 105#include <vm/vm_param.h> 106 107#ifdef DDB 108#ifndef KDB 109#error KDB must be enabled in order for DDB to work! 110#endif 111#include <ddb/ddb.h> 112#include <ddb/db_sym.h> 113#endif 114 115#include <net/netisr.h> 116 117#include <machine/clock.h> 118#include <machine/cpu.h> 119#include <machine/cputypes.h> 120#include <machine/intr_machdep.h> 121#include <x86/mca.h> 122#include <machine/md_var.h> 123#include <machine/metadata.h> 124#include <machine/mp_watchdog.h> 125#include <machine/pc/bios.h> 126#include <machine/pcb.h> 127#include <machine/proc.h> 128#include <machine/reg.h> 129#include <machine/sigframe.h> 130#include <machine/specialreg.h> 131#ifdef PERFMON 132#include <machine/perfmon.h> 133#endif 134#include <machine/tss.h> 135#ifdef SMP 136#include <machine/smp.h> 137#endif 138#ifdef FDT 139#include <x86/fdt.h> 140#endif 141 142#ifdef DEV_ATPIC 143#include <x86/isa/icu.h> 144#else 145#include <machine/apicvar.h> 146#endif 147 148#include <isa/isareg.h> 149#include <isa/rtc.h> 150 151/* Sanity check for __curthread() */ 152CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 153 154extern u_int64_t hammer_time(u_int64_t, u_int64_t); 155 156#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 157#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 158 159static void cpu_startup(void *); 160static void get_fpcontext(struct thread *td, mcontext_t *mcp, 161 char *xfpusave, size_t xfpusave_len); 162static int set_fpcontext(struct thread *td, mcontext_t *mcp, 163 char *xfpustate, size_t xfpustate_len); 164SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 165 166/* 167 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 168 * the physical address at which the kernel is loaded. 169 */ 170extern char kernphys[]; 171#ifdef DDB 172extern vm_offset_t ksym_start, ksym_end; 173#endif 174 175struct msgbuf *msgbufp; 176 177/* Intel ICH registers */ 178#define ICH_PMBASE 0x400 179#define ICH_SMI_EN ICH_PMBASE + 0x30 180 181int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 182 183int cold = 1; 184 185long Maxmem = 0; 186long realmem = 0; 187 188/* 189 * The number of PHYSMAP entries must be one less than the number of 190 * PHYSSEG entries because the PHYSMAP entry that spans the largest 191 * physical address that is accessible by ISA DMA is split into two 192 * PHYSSEG entries. 193 */ 194#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 195 196vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 197vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 198 199/* must be 2 less so 0 0 can signal end of chunks */ 200#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 201#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 202 203struct kva_md_info kmi; 204 205static struct trapframe proc0_tf; 206struct region_descriptor r_gdt, r_idt; 207 208struct pcpu __pcpu[MAXCPU]; 209 210struct mtx icu_lock; 211 212struct mem_range_softc mem_range_softc; 213 214struct mtx dt_lock; /* lock for GDT and LDT */ 215 216void (*vmm_resume_p)(void); 217 218static void 219cpu_startup(dummy) 220 void *dummy; 221{ 222 uintmax_t memsize; 223 char *sysenv; 224 225 /* 226 * On MacBooks, we need to disallow the legacy USB circuit to 227 * generate an SMI# because this can cause several problems, 228 * namely: incorrect CPU frequency detection and failure to 229 * start the APs. 230 * We do this by disabling a bit in the SMI_EN (SMI Control and 231 * Enable register) of the Intel ICH LPC Interface Bridge. 232 */ 233 sysenv = getenv("smbios.system.product"); 234 if (sysenv != NULL) { 235 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 236 strncmp(sysenv, "MacBook3,1", 10) == 0 || 237 strncmp(sysenv, "MacBook4,1", 10) == 0 || 238 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 239 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 240 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 241 strncmp(sysenv, "MacBookPro4,1", 13) == 0 || 242 strncmp(sysenv, "Macmini1,1", 10) == 0) { 243 if (bootverbose) 244 printf("Disabling LEGACY_USB_EN bit on " 245 "Intel ICH.\n"); 246 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 247 } 248 freeenv(sysenv); 249 } 250 251 /* 252 * Good {morning,afternoon,evening,night}. 253 */ 254 startrtclock(); 255 printcpuinfo(); 256 panicifcpuunsupported(); 257#ifdef PERFMON 258 perfmon_init(); 259#endif 260 261 /* 262 * Display physical memory if SMBIOS reports reasonable amount. 263 */ 264 memsize = 0; 265 sysenv = getenv("smbios.memory.enabled"); 266 if (sysenv != NULL) { 267 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 268 freeenv(sysenv); 269 } 270 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 271 memsize = ptoa((uintmax_t)Maxmem); 272 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 273 realmem = atop(memsize); 274 275 /* 276 * Display any holes after the first chunk of extended memory. 277 */ 278 if (bootverbose) { 279 int indx; 280 281 printf("Physical memory chunk(s):\n"); 282 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 283 vm_paddr_t size; 284 285 size = phys_avail[indx + 1] - phys_avail[indx]; 286 printf( 287 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 288 (uintmax_t)phys_avail[indx], 289 (uintmax_t)phys_avail[indx + 1] - 1, 290 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 291 } 292 } 293 294 vm_ksubmap_init(&kmi); 295 296 printf("avail memory = %ju (%ju MB)\n", 297 ptoa((uintmax_t)cnt.v_free_count), 298 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 299 300 /* 301 * Set up buffers, so they can be used to read disk labels. 302 */ 303 bufinit(); 304 vm_pager_bufferinit(); 305 306 cpu_setregs(); 307} 308 309/* 310 * Send an interrupt to process. 311 * 312 * Stack is set up to allow sigcode stored 313 * at top to call routine, followed by call 314 * to sigreturn routine below. After sigreturn 315 * resets the signal mask, the stack, and the 316 * frame pointer, it returns to the user 317 * specified pc, psl. 318 */ 319void 320sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 321{ 322 struct sigframe sf, *sfp; 323 struct pcb *pcb; 324 struct proc *p; 325 struct thread *td; 326 struct sigacts *psp; 327 char *sp; 328 struct trapframe *regs; 329 char *xfpusave; 330 size_t xfpusave_len; 331 int sig; 332 int oonstack; 333 334 td = curthread; 335 pcb = td->td_pcb; 336 p = td->td_proc; 337 PROC_LOCK_ASSERT(p, MA_OWNED); 338 sig = ksi->ksi_signo; 339 psp = p->p_sigacts; 340 mtx_assert(&psp->ps_mtx, MA_OWNED); 341 regs = td->td_frame; 342 oonstack = sigonstack(regs->tf_rsp); 343 344 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) { 345 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu); 346 xfpusave = __builtin_alloca(xfpusave_len); 347 } else { 348 xfpusave_len = 0; 349 xfpusave = NULL; 350 } 351 352 /* Save user context. */ 353 bzero(&sf, sizeof(sf)); 354 sf.sf_uc.uc_sigmask = *mask; 355 sf.sf_uc.uc_stack = td->td_sigstk; 356 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 357 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 358 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 359 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 360 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 361 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len); 362 fpstate_drop(td); 363 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 364 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 365 bzero(sf.sf_uc.uc_mcontext.mc_spare, 366 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 367 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 368 369 /* Allocate space for the signal handler context. */ 370 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 371 SIGISMEMBER(psp->ps_sigonstack, sig)) { 372 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size; 373#if defined(COMPAT_43) 374 td->td_sigstk.ss_flags |= SS_ONSTACK; 375#endif 376 } else 377 sp = (char *)regs->tf_rsp - 128; 378 if (xfpusave != NULL) { 379 sp -= xfpusave_len; 380 sp = (char *)((unsigned long)sp & ~0x3Ful); 381 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp; 382 } 383 sp -= sizeof(struct sigframe); 384 /* Align to 16 bytes. */ 385 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 386 387 /* Translate the signal if appropriate. */ 388 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 389 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 390 391 /* Build the argument list for the signal handler. */ 392 regs->tf_rdi = sig; /* arg 1 in %rdi */ 393 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 394 bzero(&sf.sf_si, sizeof(sf.sf_si)); 395 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 396 /* Signal handler installed with SA_SIGINFO. */ 397 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 398 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 399 400 /* Fill in POSIX parts */ 401 sf.sf_si = ksi->ksi_info; 402 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 403 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 404 } else { 405 /* Old FreeBSD-style arguments. */ 406 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 407 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 408 sf.sf_ahu.sf_handler = catcher; 409 } 410 mtx_unlock(&psp->ps_mtx); 411 PROC_UNLOCK(p); 412 413 /* 414 * Copy the sigframe out to the user's stack. 415 */ 416 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 || 417 (xfpusave != NULL && copyout(xfpusave, 418 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len) 419 != 0)) { 420#ifdef DEBUG 421 printf("process %ld has trashed its stack\n", (long)p->p_pid); 422#endif 423 PROC_LOCK(p); 424 sigexit(td, SIGILL); 425 } 426 427 regs->tf_rsp = (long)sfp; 428 regs->tf_rip = p->p_sysent->sv_sigcode_base; 429 regs->tf_rflags &= ~(PSL_T | PSL_D); 430 regs->tf_cs = _ucodesel; 431 regs->tf_ds = _udatasel; 432 regs->tf_ss = _udatasel; 433 regs->tf_es = _udatasel; 434 regs->tf_fs = _ufssel; 435 regs->tf_gs = _ugssel; 436 regs->tf_flags = TF_HASSEGS; 437 set_pcb_flags(pcb, PCB_FULL_IRET); 438 PROC_LOCK(p); 439 mtx_lock(&psp->ps_mtx); 440} 441 442/* 443 * System call to cleanup state after a signal 444 * has been taken. Reset signal mask and 445 * stack state from context left by sendsig (above). 446 * Return to previous pc and psl as specified by 447 * context left by sendsig. Check carefully to 448 * make sure that the user has not modified the 449 * state to gain improper privileges. 450 * 451 * MPSAFE 452 */ 453int 454sys_sigreturn(td, uap) 455 struct thread *td; 456 struct sigreturn_args /* { 457 const struct __ucontext *sigcntxp; 458 } */ *uap; 459{ 460 ucontext_t uc; 461 struct pcb *pcb; 462 struct proc *p; 463 struct trapframe *regs; 464 ucontext_t *ucp; 465 char *xfpustate; 466 size_t xfpustate_len; 467 long rflags; 468 int cs, error, ret; 469 ksiginfo_t ksi; 470 471 pcb = td->td_pcb; 472 p = td->td_proc; 473 474 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 475 if (error != 0) { 476 uprintf("pid %d (%s): sigreturn copyin failed\n", 477 p->p_pid, td->td_name); 478 return (error); 479 } 480 ucp = &uc; 481 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 482 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 483 td->td_name, ucp->uc_mcontext.mc_flags); 484 return (EINVAL); 485 } 486 regs = td->td_frame; 487 rflags = ucp->uc_mcontext.mc_rflags; 488 /* 489 * Don't allow users to change privileged or reserved flags. 490 */ 491 if (!EFL_SECURE(rflags, regs->tf_rflags)) { 492 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 493 td->td_name, rflags); 494 return (EINVAL); 495 } 496 497 /* 498 * Don't allow users to load a valid privileged %cs. Let the 499 * hardware check for invalid selectors, excess privilege in 500 * other selectors, invalid %eip's and invalid %esp's. 501 */ 502 cs = ucp->uc_mcontext.mc_cs; 503 if (!CS_SECURE(cs)) { 504 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 505 td->td_name, cs); 506 ksiginfo_init_trap(&ksi); 507 ksi.ksi_signo = SIGBUS; 508 ksi.ksi_code = BUS_OBJERR; 509 ksi.ksi_trapno = T_PROTFLT; 510 ksi.ksi_addr = (void *)regs->tf_rip; 511 trapsignal(td, &ksi); 512 return (EINVAL); 513 } 514 515 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) { 516 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len; 517 if (xfpustate_len > cpu_max_ext_state_size - 518 sizeof(struct savefpu)) { 519 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n", 520 p->p_pid, td->td_name, xfpustate_len); 521 return (EINVAL); 522 } 523 xfpustate = __builtin_alloca(xfpustate_len); 524 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate, 525 xfpustate, xfpustate_len); 526 if (error != 0) { 527 uprintf( 528 "pid %d (%s): sigreturn copying xfpustate failed\n", 529 p->p_pid, td->td_name); 530 return (error); 531 } 532 } else { 533 xfpustate = NULL; 534 xfpustate_len = 0; 535 } 536 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len); 537 if (ret != 0) { 538 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 539 p->p_pid, td->td_name, ret); 540 return (ret); 541 } 542 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 543 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 544 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 545 546#if defined(COMPAT_43) 547 if (ucp->uc_mcontext.mc_onstack & 1) 548 td->td_sigstk.ss_flags |= SS_ONSTACK; 549 else 550 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 551#endif 552 553 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 554 set_pcb_flags(pcb, PCB_FULL_IRET); 555 return (EJUSTRETURN); 556} 557 558#ifdef COMPAT_FREEBSD4 559int 560freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 561{ 562 563 return sys_sigreturn(td, (struct sigreturn_args *)uap); 564} 565#endif 566 567 568/* 569 * Machine dependent boot() routine 570 * 571 * I haven't seen anything to put here yet 572 * Possibly some stuff might be grafted back here from boot() 573 */ 574void 575cpu_boot(int howto) 576{ 577} 578 579/* 580 * Flush the D-cache for non-DMA I/O so that the I-cache can 581 * be made coherent later. 582 */ 583void 584cpu_flush_dcache(void *ptr, size_t len) 585{ 586 /* Not applicable */ 587} 588 589/* Get current clock frequency for the given cpu id. */ 590int 591cpu_est_clockrate(int cpu_id, uint64_t *rate) 592{ 593 uint64_t tsc1, tsc2; 594 uint64_t acnt, mcnt, perf; 595 register_t reg; 596 597 if (pcpu_find(cpu_id) == NULL || rate == NULL) 598 return (EINVAL); 599 600 /* 601 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 602 * DELAY(9) based logic fails. 603 */ 604 if (tsc_is_invariant && !tsc_perf_stat) 605 return (EOPNOTSUPP); 606 607#ifdef SMP 608 if (smp_cpus > 1) { 609 /* Schedule ourselves on the indicated cpu. */ 610 thread_lock(curthread); 611 sched_bind(curthread, cpu_id); 612 thread_unlock(curthread); 613 } 614#endif 615 616 /* Calibrate by measuring a short delay. */ 617 reg = intr_disable(); 618 if (tsc_is_invariant) { 619 wrmsr(MSR_MPERF, 0); 620 wrmsr(MSR_APERF, 0); 621 tsc1 = rdtsc(); 622 DELAY(1000); 623 mcnt = rdmsr(MSR_MPERF); 624 acnt = rdmsr(MSR_APERF); 625 tsc2 = rdtsc(); 626 intr_restore(reg); 627 perf = 1000 * acnt / mcnt; 628 *rate = (tsc2 - tsc1) * perf; 629 } else { 630 tsc1 = rdtsc(); 631 DELAY(1000); 632 tsc2 = rdtsc(); 633 intr_restore(reg); 634 *rate = (tsc2 - tsc1) * 1000; 635 } 636 637#ifdef SMP 638 if (smp_cpus > 1) { 639 thread_lock(curthread); 640 sched_unbind(curthread); 641 thread_unlock(curthread); 642 } 643#endif 644 645 return (0); 646} 647 648/* 649 * Shutdown the CPU as much as possible 650 */ 651void 652cpu_halt(void) 653{ 654 for (;;) 655 halt(); 656} 657 658void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 659static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 660static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 661TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 662SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 663 0, "Use MONITOR/MWAIT for short idle"); 664 665#define STATE_RUNNING 0x0 666#define STATE_MWAIT 0x1 667#define STATE_SLEEPING 0x2 668 669static void 670cpu_idle_acpi(sbintime_t sbt) 671{ 672 int *state; 673 674 state = (int *)PCPU_PTR(monitorbuf); 675 *state = STATE_SLEEPING; 676 677 /* See comments in cpu_idle_hlt(). */ 678 disable_intr(); 679 if (sched_runnable()) 680 enable_intr(); 681 else if (cpu_idle_hook) 682 cpu_idle_hook(sbt); 683 else 684 __asm __volatile("sti; hlt"); 685 *state = STATE_RUNNING; 686} 687 688static void 689cpu_idle_hlt(sbintime_t sbt) 690{ 691 int *state; 692 693 state = (int *)PCPU_PTR(monitorbuf); 694 *state = STATE_SLEEPING; 695 696 /* 697 * Since we may be in a critical section from cpu_idle(), if 698 * an interrupt fires during that critical section we may have 699 * a pending preemption. If the CPU halts, then that thread 700 * may not execute until a later interrupt awakens the CPU. 701 * To handle this race, check for a runnable thread after 702 * disabling interrupts and immediately return if one is 703 * found. Also, we must absolutely guarentee that hlt is 704 * the next instruction after sti. This ensures that any 705 * interrupt that fires after the call to disable_intr() will 706 * immediately awaken the CPU from hlt. Finally, please note 707 * that on x86 this works fine because of interrupts enabled only 708 * after the instruction following sti takes place, while IF is set 709 * to 1 immediately, allowing hlt instruction to acknowledge the 710 * interrupt. 711 */ 712 disable_intr(); 713 if (sched_runnable()) 714 enable_intr(); 715 else 716 __asm __volatile("sti; hlt"); 717 *state = STATE_RUNNING; 718} 719 720static void 721cpu_idle_mwait(sbintime_t sbt) 722{ 723 int *state; 724 725 state = (int *)PCPU_PTR(monitorbuf); 726 *state = STATE_MWAIT; 727 728 /* See comments in cpu_idle_hlt(). */ 729 disable_intr(); 730 if (sched_runnable()) { 731 enable_intr(); 732 *state = STATE_RUNNING; 733 return; 734 } 735 cpu_monitor(state, 0, 0); 736 if (*state == STATE_MWAIT) 737 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 738 else 739 enable_intr(); 740 *state = STATE_RUNNING; 741} 742 743static void 744cpu_idle_spin(sbintime_t sbt) 745{ 746 int *state; 747 int i; 748 749 state = (int *)PCPU_PTR(monitorbuf); 750 *state = STATE_RUNNING; 751 752 /* 753 * The sched_runnable() call is racy but as long as there is 754 * a loop missing it one time will have just a little impact if any 755 * (and it is much better than missing the check at all). 756 */ 757 for (i = 0; i < 1000; i++) { 758 if (sched_runnable()) 759 return; 760 cpu_spinwait(); 761 } 762} 763 764/* 765 * C1E renders the local APIC timer dead, so we disable it by 766 * reading the Interrupt Pending Message register and clearing 767 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 768 * 769 * Reference: 770 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 771 * #32559 revision 3.00+ 772 */ 773#define MSR_AMDK8_IPM 0xc0010055 774#define AMDK8_SMIONCMPHALT (1ULL << 27) 775#define AMDK8_C1EONCMPHALT (1ULL << 28) 776#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 777 778static void 779cpu_probe_amdc1e(void) 780{ 781 782 /* 783 * Detect the presence of C1E capability mostly on latest 784 * dual-cores (or future) k8 family. 785 */ 786 if (cpu_vendor_id == CPU_VENDOR_AMD && 787 (cpu_id & 0x00000f00) == 0x00000f00 && 788 (cpu_id & 0x0fff0000) >= 0x00040000) { 789 cpu_ident_amdc1e = 1; 790 } 791} 792 793void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 794 795void 796cpu_idle(int busy) 797{ 798 uint64_t msr; 799 sbintime_t sbt = -1; 800 801 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 802 busy, curcpu); 803#ifdef MP_WATCHDOG 804 ap_watchdog(PCPU_GET(cpuid)); 805#endif 806 /* If we are busy - try to use fast methods. */ 807 if (busy) { 808 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 809 cpu_idle_mwait(busy); 810 goto out; 811 } 812 } 813 814 /* If we have time - switch timers into idle mode. */ 815 if (!busy) { 816 critical_enter(); 817 sbt = cpu_idleclock(); 818 } 819 820 /* Apply AMD APIC timer C1E workaround. */ 821 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) { 822 msr = rdmsr(MSR_AMDK8_IPM); 823 if (msr & AMDK8_CMPHALT) 824 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 825 } 826 827 /* Call main idle method. */ 828 cpu_idle_fn(sbt); 829 830 /* Switch timers mack into active mode. */ 831 if (!busy) { 832 cpu_activeclock(); 833 critical_exit(); 834 } 835out: 836 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 837 busy, curcpu); 838} 839 840int 841cpu_idle_wakeup(int cpu) 842{ 843 struct pcpu *pcpu; 844 int *state; 845 846 pcpu = pcpu_find(cpu); 847 state = (int *)pcpu->pc_monitorbuf; 848 /* 849 * This doesn't need to be atomic since missing the race will 850 * simply result in unnecessary IPIs. 851 */ 852 if (*state == STATE_SLEEPING) 853 return (0); 854 if (*state == STATE_MWAIT) 855 *state = STATE_RUNNING; 856 return (1); 857} 858 859/* 860 * Ordered by speed/power consumption. 861 */ 862struct { 863 void *id_fn; 864 char *id_name; 865} idle_tbl[] = { 866 { cpu_idle_spin, "spin" }, 867 { cpu_idle_mwait, "mwait" }, 868 { cpu_idle_hlt, "hlt" }, 869 { cpu_idle_acpi, "acpi" }, 870 { NULL, NULL } 871}; 872 873static int 874idle_sysctl_available(SYSCTL_HANDLER_ARGS) 875{ 876 char *avail, *p; 877 int error; 878 int i; 879 880 avail = malloc(256, M_TEMP, M_WAITOK); 881 p = avail; 882 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 883 if (strstr(idle_tbl[i].id_name, "mwait") && 884 (cpu_feature2 & CPUID2_MON) == 0) 885 continue; 886 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 887 cpu_idle_hook == NULL) 888 continue; 889 p += sprintf(p, "%s%s", p != avail ? ", " : "", 890 idle_tbl[i].id_name); 891 } 892 error = sysctl_handle_string(oidp, avail, 0, req); 893 free(avail, M_TEMP); 894 return (error); 895} 896 897SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 898 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 899 900static int 901idle_sysctl(SYSCTL_HANDLER_ARGS) 902{ 903 char buf[16]; 904 int error; 905 char *p; 906 int i; 907 908 p = "unknown"; 909 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 910 if (idle_tbl[i].id_fn == cpu_idle_fn) { 911 p = idle_tbl[i].id_name; 912 break; 913 } 914 } 915 strncpy(buf, p, sizeof(buf)); 916 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 917 if (error != 0 || req->newptr == NULL) 918 return (error); 919 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 920 if (strstr(idle_tbl[i].id_name, "mwait") && 921 (cpu_feature2 & CPUID2_MON) == 0) 922 continue; 923 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 924 cpu_idle_hook == NULL) 925 continue; 926 if (strcmp(idle_tbl[i].id_name, buf)) 927 continue; 928 cpu_idle_fn = idle_tbl[i].id_fn; 929 return (0); 930 } 931 return (EINVAL); 932} 933 934SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 935 idle_sysctl, "A", "currently selected idle function"); 936 937/* 938 * Reset registers to default values on exec. 939 */ 940void 941exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 942{ 943 struct trapframe *regs = td->td_frame; 944 struct pcb *pcb = td->td_pcb; 945 946 mtx_lock(&dt_lock); 947 if (td->td_proc->p_md.md_ldt != NULL) 948 user_ldt_free(td); 949 else 950 mtx_unlock(&dt_lock); 951 952 pcb->pcb_fsbase = 0; 953 pcb->pcb_gsbase = 0; 954 clear_pcb_flags(pcb, PCB_32BIT); 955 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 956 set_pcb_flags(pcb, PCB_FULL_IRET); 957 958 bzero((char *)regs, sizeof(struct trapframe)); 959 regs->tf_rip = imgp->entry_addr; 960 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 961 regs->tf_rdi = stack; /* argv */ 962 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 963 regs->tf_ss = _udatasel; 964 regs->tf_cs = _ucodesel; 965 regs->tf_ds = _udatasel; 966 regs->tf_es = _udatasel; 967 regs->tf_fs = _ufssel; 968 regs->tf_gs = _ugssel; 969 regs->tf_flags = TF_HASSEGS; 970 td->td_retval[1] = 0; 971 972 /* 973 * Reset the hardware debug registers if they were in use. 974 * They won't have any meaning for the newly exec'd process. 975 */ 976 if (pcb->pcb_flags & PCB_DBREGS) { 977 pcb->pcb_dr0 = 0; 978 pcb->pcb_dr1 = 0; 979 pcb->pcb_dr2 = 0; 980 pcb->pcb_dr3 = 0; 981 pcb->pcb_dr6 = 0; 982 pcb->pcb_dr7 = 0; 983 if (pcb == curpcb) { 984 /* 985 * Clear the debug registers on the running 986 * CPU, otherwise they will end up affecting 987 * the next process we switch to. 988 */ 989 reset_dbregs(); 990 } 991 clear_pcb_flags(pcb, PCB_DBREGS); 992 } 993 994 /* 995 * Drop the FP state if we hold it, so that the process gets a 996 * clean FP state if it uses the FPU again. 997 */ 998 fpstate_drop(td); 999} 1000 1001void 1002cpu_setregs(void) 1003{ 1004 register_t cr0; 1005 1006 cr0 = rcr0(); 1007 /* 1008 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 1009 * BSP. See the comments there about why we set them. 1010 */ 1011 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 1012 load_cr0(cr0); 1013} 1014 1015/* 1016 * Initialize amd64 and configure to run kernel 1017 */ 1018 1019/* 1020 * Initialize segments & interrupt table 1021 */ 1022 1023struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 1024static struct gate_descriptor idt0[NIDT]; 1025struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 1026 1027static char dblfault_stack[PAGE_SIZE] __aligned(16); 1028 1029static char nmi0_stack[PAGE_SIZE] __aligned(16); 1030CTASSERT(sizeof(struct nmi_pcpu) == 16); 1031 1032struct amd64tss common_tss[MAXCPU]; 1033 1034/* 1035 * Software prototypes -- in more palatable form. 1036 * 1037 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 1038 * slots as corresponding segments for i386 kernel. 1039 */ 1040struct soft_segment_descriptor gdt_segs[] = { 1041/* GNULL_SEL 0 Null Descriptor */ 1042{ .ssd_base = 0x0, 1043 .ssd_limit = 0x0, 1044 .ssd_type = 0, 1045 .ssd_dpl = 0, 1046 .ssd_p = 0, 1047 .ssd_long = 0, 1048 .ssd_def32 = 0, 1049 .ssd_gran = 0 }, 1050/* GNULL2_SEL 1 Null Descriptor */ 1051{ .ssd_base = 0x0, 1052 .ssd_limit = 0x0, 1053 .ssd_type = 0, 1054 .ssd_dpl = 0, 1055 .ssd_p = 0, 1056 .ssd_long = 0, 1057 .ssd_def32 = 0, 1058 .ssd_gran = 0 }, 1059/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 1060{ .ssd_base = 0x0, 1061 .ssd_limit = 0xfffff, 1062 .ssd_type = SDT_MEMRWA, 1063 .ssd_dpl = SEL_UPL, 1064 .ssd_p = 1, 1065 .ssd_long = 0, 1066 .ssd_def32 = 1, 1067 .ssd_gran = 1 }, 1068/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1069{ .ssd_base = 0x0, 1070 .ssd_limit = 0xfffff, 1071 .ssd_type = SDT_MEMRWA, 1072 .ssd_dpl = SEL_UPL, 1073 .ssd_p = 1, 1074 .ssd_long = 0, 1075 .ssd_def32 = 1, 1076 .ssd_gran = 1 }, 1077/* GCODE_SEL 4 Code Descriptor for kernel */ 1078{ .ssd_base = 0x0, 1079 .ssd_limit = 0xfffff, 1080 .ssd_type = SDT_MEMERA, 1081 .ssd_dpl = SEL_KPL, 1082 .ssd_p = 1, 1083 .ssd_long = 1, 1084 .ssd_def32 = 0, 1085 .ssd_gran = 1 }, 1086/* GDATA_SEL 5 Data Descriptor for kernel */ 1087{ .ssd_base = 0x0, 1088 .ssd_limit = 0xfffff, 1089 .ssd_type = SDT_MEMRWA, 1090 .ssd_dpl = SEL_KPL, 1091 .ssd_p = 1, 1092 .ssd_long = 1, 1093 .ssd_def32 = 0, 1094 .ssd_gran = 1 }, 1095/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1096{ .ssd_base = 0x0, 1097 .ssd_limit = 0xfffff, 1098 .ssd_type = SDT_MEMERA, 1099 .ssd_dpl = SEL_UPL, 1100 .ssd_p = 1, 1101 .ssd_long = 0, 1102 .ssd_def32 = 1, 1103 .ssd_gran = 1 }, 1104/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1105{ .ssd_base = 0x0, 1106 .ssd_limit = 0xfffff, 1107 .ssd_type = SDT_MEMRWA, 1108 .ssd_dpl = SEL_UPL, 1109 .ssd_p = 1, 1110 .ssd_long = 0, 1111 .ssd_def32 = 1, 1112 .ssd_gran = 1 }, 1113/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1114{ .ssd_base = 0x0, 1115 .ssd_limit = 0xfffff, 1116 .ssd_type = SDT_MEMERA, 1117 .ssd_dpl = SEL_UPL, 1118 .ssd_p = 1, 1119 .ssd_long = 1, 1120 .ssd_def32 = 0, 1121 .ssd_gran = 1 }, 1122/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1123{ .ssd_base = 0x0, 1124 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1125 .ssd_type = SDT_SYSTSS, 1126 .ssd_dpl = SEL_KPL, 1127 .ssd_p = 1, 1128 .ssd_long = 0, 1129 .ssd_def32 = 0, 1130 .ssd_gran = 0 }, 1131/* Actually, the TSS is a system descriptor which is double size */ 1132{ .ssd_base = 0x0, 1133 .ssd_limit = 0x0, 1134 .ssd_type = 0, 1135 .ssd_dpl = 0, 1136 .ssd_p = 0, 1137 .ssd_long = 0, 1138 .ssd_def32 = 0, 1139 .ssd_gran = 0 }, 1140/* GUSERLDT_SEL 11 LDT Descriptor */ 1141{ .ssd_base = 0x0, 1142 .ssd_limit = 0x0, 1143 .ssd_type = 0, 1144 .ssd_dpl = 0, 1145 .ssd_p = 0, 1146 .ssd_long = 0, 1147 .ssd_def32 = 0, 1148 .ssd_gran = 0 }, 1149/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1150{ .ssd_base = 0x0, 1151 .ssd_limit = 0x0, 1152 .ssd_type = 0, 1153 .ssd_dpl = 0, 1154 .ssd_p = 0, 1155 .ssd_long = 0, 1156 .ssd_def32 = 0, 1157 .ssd_gran = 0 }, 1158}; 1159 1160void 1161setidt(idx, func, typ, dpl, ist) 1162 int idx; 1163 inthand_t *func; 1164 int typ; 1165 int dpl; 1166 int ist; 1167{ 1168 struct gate_descriptor *ip; 1169 1170 ip = idt + idx; 1171 ip->gd_looffset = (uintptr_t)func; 1172 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1173 ip->gd_ist = ist; 1174 ip->gd_xx = 0; 1175 ip->gd_type = typ; 1176 ip->gd_dpl = dpl; 1177 ip->gd_p = 1; 1178 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1179} 1180 1181extern inthand_t 1182 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1183 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1184 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1185 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1186 IDTVEC(xmm), IDTVEC(dblfault), 1187#ifdef KDTRACE_HOOKS 1188 IDTVEC(dtrace_ret), 1189#endif 1190#ifdef XENHVM 1191 IDTVEC(xen_intr_upcall), 1192#endif 1193 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1194 1195#ifdef DDB 1196/* 1197 * Display the index and function name of any IDT entries that don't use 1198 * the default 'rsvd' entry point. 1199 */ 1200DB_SHOW_COMMAND(idt, db_show_idt) 1201{ 1202 struct gate_descriptor *ip; 1203 int idx; 1204 uintptr_t func; 1205 1206 ip = idt; 1207 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1208 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1209 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1210 db_printf("%3d\t", idx); 1211 db_printsym(func, DB_STGY_PROC); 1212 db_printf("\n"); 1213 } 1214 ip++; 1215 } 1216} 1217 1218/* Show privileged registers. */ 1219DB_SHOW_COMMAND(sysregs, db_show_sysregs) 1220{ 1221 struct { 1222 uint16_t limit; 1223 uint64_t base; 1224 } __packed idtr, gdtr; 1225 uint16_t ldt, tr; 1226 1227 __asm __volatile("sidt %0" : "=m" (idtr)); 1228 db_printf("idtr\t0x%016lx/%04x\n", 1229 (u_long)idtr.base, (u_int)idtr.limit); 1230 __asm __volatile("sgdt %0" : "=m" (gdtr)); 1231 db_printf("gdtr\t0x%016lx/%04x\n", 1232 (u_long)gdtr.base, (u_int)gdtr.limit); 1233 __asm __volatile("sldt %0" : "=r" (ldt)); 1234 db_printf("ldtr\t0x%04x\n", ldt); 1235 __asm __volatile("str %0" : "=r" (tr)); 1236 db_printf("tr\t0x%04x\n", tr); 1237 db_printf("cr0\t0x%016lx\n", rcr0()); 1238 db_printf("cr2\t0x%016lx\n", rcr2()); 1239 db_printf("cr3\t0x%016lx\n", rcr3()); 1240 db_printf("cr4\t0x%016lx\n", rcr4()); 1241 if (rcr4() & CR4_XSAVE) 1242 db_printf("xcr0\t0x%016lx\n", rxcr(0)); 1243 db_printf("EFER\t0x%016lx\n", rdmsr(MSR_EFER)); 1244 if (cpu_feature2 & (CPUID2_VMX | CPUID2_SMX)) 1245 db_printf("FEATURES_CTL\t%016lx\n", 1246 rdmsr(MSR_IA32_FEATURE_CONTROL)); 1247 db_printf("DEBUG_CTL\t0x%016lx\n", rdmsr(MSR_DEBUGCTLMSR)); 1248 db_printf("PAT\t0x%016lx\n", rdmsr(MSR_PAT)); 1249 db_printf("GSBASE\t0x%016lx\n", rdmsr(MSR_GSBASE)); 1250} 1251 1252DB_SHOW_COMMAND(dbregs, db_show_dbregs) 1253{ 1254 1255 db_printf("dr0\t0x%016lx\n", rdr0()); 1256 db_printf("dr1\t0x%016lx\n", rdr1()); 1257 db_printf("dr2\t0x%016lx\n", rdr2()); 1258 db_printf("dr3\t0x%016lx\n", rdr3()); 1259 db_printf("dr6\t0x%016lx\n", rdr6()); 1260 db_printf("dr7\t0x%016lx\n", rdr7()); 1261} 1262#endif 1263 1264void 1265sdtossd(sd, ssd) 1266 struct user_segment_descriptor *sd; 1267 struct soft_segment_descriptor *ssd; 1268{ 1269 1270 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1271 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1272 ssd->ssd_type = sd->sd_type; 1273 ssd->ssd_dpl = sd->sd_dpl; 1274 ssd->ssd_p = sd->sd_p; 1275 ssd->ssd_long = sd->sd_long; 1276 ssd->ssd_def32 = sd->sd_def32; 1277 ssd->ssd_gran = sd->sd_gran; 1278} 1279 1280void 1281ssdtosd(ssd, sd) 1282 struct soft_segment_descriptor *ssd; 1283 struct user_segment_descriptor *sd; 1284{ 1285 1286 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1287 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1288 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1289 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1290 sd->sd_type = ssd->ssd_type; 1291 sd->sd_dpl = ssd->ssd_dpl; 1292 sd->sd_p = ssd->ssd_p; 1293 sd->sd_long = ssd->ssd_long; 1294 sd->sd_def32 = ssd->ssd_def32; 1295 sd->sd_gran = ssd->ssd_gran; 1296} 1297 1298void 1299ssdtosyssd(ssd, sd) 1300 struct soft_segment_descriptor *ssd; 1301 struct system_segment_descriptor *sd; 1302{ 1303 1304 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1305 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1306 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1307 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1308 sd->sd_type = ssd->ssd_type; 1309 sd->sd_dpl = ssd->ssd_dpl; 1310 sd->sd_p = ssd->ssd_p; 1311 sd->sd_gran = ssd->ssd_gran; 1312} 1313 1314#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1315#include <isa/isavar.h> 1316#include <isa/isareg.h> 1317/* 1318 * Return a bitmap of the current interrupt requests. This is 8259-specific 1319 * and is only suitable for use at probe time. 1320 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1321 * It shouldn't be here. There should probably be an APIC centric 1322 * implementation in the apic driver code, if at all. 1323 */ 1324intrmask_t 1325isa_irq_pending(void) 1326{ 1327 u_char irr1; 1328 u_char irr2; 1329 1330 irr1 = inb(IO_ICU1); 1331 irr2 = inb(IO_ICU2); 1332 return ((irr2 << 8) | irr1); 1333} 1334#endif 1335 1336u_int basemem; 1337 1338static int 1339add_physmap_entry(uint64_t base, uint64_t length, vm_paddr_t *physmap, 1340 int *physmap_idxp) 1341{ 1342 int i, insert_idx, physmap_idx; 1343 1344 physmap_idx = *physmap_idxp; 1345 1346 if (length == 0) 1347 return (1); 1348 1349 /* 1350 * Find insertion point while checking for overlap. Start off by 1351 * assuming the new entry will be added to the end. 1352 */ 1353 insert_idx = physmap_idx + 2; 1354 for (i = 0; i <= physmap_idx; i += 2) { 1355 if (base < physmap[i + 1]) { 1356 if (base + length <= physmap[i]) { 1357 insert_idx = i; 1358 break; 1359 } 1360 if (boothowto & RB_VERBOSE) 1361 printf( 1362 "Overlapping memory regions, ignoring second region\n"); 1363 return (1); 1364 } 1365 } 1366 1367 /* See if we can prepend to the next entry. */ 1368 if (insert_idx <= physmap_idx && base + length == physmap[insert_idx]) { 1369 physmap[insert_idx] = base; 1370 return (1); 1371 } 1372 1373 /* See if we can append to the previous entry. */ 1374 if (insert_idx > 0 && base == physmap[insert_idx - 1]) { 1375 physmap[insert_idx - 1] += length; 1376 return (1); 1377 } 1378 1379 physmap_idx += 2; 1380 *physmap_idxp = physmap_idx; 1381 if (physmap_idx == PHYSMAP_SIZE) { 1382 printf( 1383 "Too many segments in the physical address map, giving up\n"); 1384 return (0); 1385 } 1386 1387 /* 1388 * Move the last 'N' entries down to make room for the new 1389 * entry if needed. 1390 */ 1391 for (i = physmap_idx; i > insert_idx; i -= 2) { 1392 physmap[i] = physmap[i - 2]; 1393 physmap[i + 1] = physmap[i - 1]; 1394 } 1395 1396 /* Insert the new entry. */ 1397 physmap[insert_idx] = base; 1398 physmap[insert_idx + 1] = base + length; 1399 return (1); 1400} 1401 1402static void 1403add_smap_entries(struct bios_smap *smapbase, vm_paddr_t *physmap, 1404 int *physmap_idx) 1405{ 1406 struct bios_smap *smap, *smapend; 1407 u_int32_t smapsize; 1408 1409 /* 1410 * Memory map from INT 15:E820. 1411 * 1412 * subr_module.c says: 1413 * "Consumer may safely assume that size value precedes data." 1414 * ie: an int32_t immediately precedes smap. 1415 */ 1416 smapsize = *((u_int32_t *)smapbase - 1); 1417 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1418 1419 for (smap = smapbase; smap < smapend; smap++) { 1420 if (boothowto & RB_VERBOSE) 1421 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1422 smap->type, smap->base, smap->length); 1423 1424 if (smap->type != SMAP_TYPE_MEMORY) 1425 continue; 1426 1427 if (!add_physmap_entry(smap->base, smap->length, physmap, 1428 physmap_idx)) 1429 break; 1430 } 1431} 1432 1433#define efi_next_descriptor(ptr, size) \ 1434 ((struct efi_md *)(((uint8_t *) ptr) + size)) 1435 1436static void 1437add_efi_map_entries(struct efi_map_header *efihdr, vm_paddr_t *physmap, 1438 int *physmap_idx) 1439{ 1440 struct efi_md *map, *p; 1441 const char *type; 1442 size_t efisz; 1443 int ndesc, i; 1444 1445 static const char *types[] = { 1446 "Reserved", 1447 "LoaderCode", 1448 "LoaderData", 1449 "BootServicesCode", 1450 "BootServicesData", 1451 "RuntimeServicesCode", 1452 "RuntimeServicesData", 1453 "ConventionalMemory", 1454 "UnusableMemory", 1455 "ACPIReclaimMemory", 1456 "ACPIMemoryNVS", 1457 "MemoryMappedIO", 1458 "MemoryMappedIOPortSpace", 1459 "PalCode" 1460 }; 1461 1462 /* 1463 * Memory map data provided by UEFI via the GetMemoryMap 1464 * Boot Services API. 1465 */ 1466 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1467 map = (struct efi_md *)((uint8_t *)efihdr + efisz); 1468 1469 if (efihdr->descriptor_size == 0) 1470 return; 1471 ndesc = efihdr->memory_size / efihdr->descriptor_size; 1472 1473 if (boothowto & RB_VERBOSE) 1474 printf("%23s %12s %12s %8s %4s\n", 1475 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1476 1477 for (i = 0, p = map; i < ndesc; i++, 1478 p = efi_next_descriptor(p, efihdr->descriptor_size)) { 1479 if (boothowto & RB_VERBOSE) { 1480 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1481 type = types[p->md_type]; 1482 else 1483 type = "<INVALID>"; 1484 printf("%23s %012lx %12p %08lx ", type, p->md_phys, 1485 p->md_virt, p->md_pages); 1486 if (p->md_attr & EFI_MD_ATTR_UC) 1487 printf("UC "); 1488 if (p->md_attr & EFI_MD_ATTR_WC) 1489 printf("WC "); 1490 if (p->md_attr & EFI_MD_ATTR_WT) 1491 printf("WT "); 1492 if (p->md_attr & EFI_MD_ATTR_WB) 1493 printf("WB "); 1494 if (p->md_attr & EFI_MD_ATTR_UCE) 1495 printf("UCE "); 1496 if (p->md_attr & EFI_MD_ATTR_WP) 1497 printf("WP "); 1498 if (p->md_attr & EFI_MD_ATTR_RP) 1499 printf("RP "); 1500 if (p->md_attr & EFI_MD_ATTR_XP) 1501 printf("XP "); 1502 if (p->md_attr & EFI_MD_ATTR_RT) 1503 printf("RUNTIME"); 1504 printf("\n"); 1505 } 1506 1507 switch (p->md_type) { 1508 case EFI_MD_TYPE_CODE: 1509 case EFI_MD_TYPE_DATA: 1510 case EFI_MD_TYPE_BS_CODE: 1511 case EFI_MD_TYPE_BS_DATA: 1512 case EFI_MD_TYPE_FREE: 1513 /* 1514 * We're allowed to use any entry with these types. 1515 */ 1516 break; 1517 default: 1518 continue; 1519 } 1520 1521 if (!add_physmap_entry(p->md_phys, (p->md_pages * PAGE_SIZE), 1522 physmap, physmap_idx)) 1523 break; 1524 } 1525} 1526 1527static char bootmethod[16] = ""; 1528SYSCTL_STRING(_machdep, OID_AUTO, bootmethod, CTLFLAG_RD, bootmethod, 0, 1529 "System firmware boot method"); 1530 1531#define PAGES_PER_GB (1024 * 1024 * 1024 / PAGE_SIZE) 1532 1533/* 1534 * Populate the (physmap) array with base/bound pairs describing the 1535 * available physical memory in the system, then test this memory and 1536 * build the phys_avail array describing the actually-available memory. 1537 * 1538 * Total memory size may be set by the kernel environment variable 1539 * hw.physmem or the compile-time define MAXMEM. 1540 * 1541 * XXX first should be vm_paddr_t. 1542 */ 1543static void 1544getmemsize(caddr_t kmdp, u_int64_t first) 1545{ 1546 int i, physmap_idx, pa_indx, da_indx; 1547 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1548 u_long physmem_start, physmem_tunable, memtest; 1549 pt_entry_t *pte; 1550 struct bios_smap *smapbase; 1551 struct efi_map_header *efihdr; 1552 quad_t dcons_addr, dcons_size; 1553 int page_counter; 1554 1555 bzero(physmap, sizeof(physmap)); 1556 basemem = 0; 1557 physmap_idx = 0; 1558 1559 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1560 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1561 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1562 MODINFO_METADATA | MODINFOMD_SMAP); 1563 1564 if (efihdr != NULL) { 1565 add_efi_map_entries(efihdr, physmap, &physmap_idx); 1566 strlcpy(bootmethod, "UEFI", sizeof(bootmethod)); 1567 } else if (smapbase != NULL) { 1568 add_smap_entries(smapbase, physmap, &physmap_idx); 1569 strlcpy(bootmethod, "BIOS", sizeof(bootmethod)); 1570 } else { 1571 panic("No BIOS smap or EFI map info from loader!"); 1572 } 1573 1574 /* 1575 * Find the 'base memory' segment for SMP 1576 */ 1577 basemem = 0; 1578 for (i = 0; i <= physmap_idx; i += 2) { 1579 if (physmap[i] == 0x00000000) { 1580 basemem = physmap[i + 1] / 1024; 1581 break; 1582 } 1583 } 1584 if (basemem == 0) 1585 panic("BIOS smap did not include a basemem segment!"); 1586 1587#ifdef SMP 1588 /* make hole for AP bootstrap code */ 1589 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1590#endif 1591 1592 /* 1593 * Maxmem isn't the "maximum memory", it's one larger than the 1594 * highest page of the physical address space. It should be 1595 * called something like "Maxphyspage". We may adjust this 1596 * based on ``hw.physmem'' and the results of the memory test. 1597 */ 1598 Maxmem = atop(physmap[physmap_idx + 1]); 1599 1600#ifdef MAXMEM 1601 Maxmem = MAXMEM / 4; 1602#endif 1603 1604 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1605 Maxmem = atop(physmem_tunable); 1606 1607 /* 1608 * The boot memory test is disabled by default, as it takes a 1609 * significant amount of time on large-memory systems, and is 1610 * unfriendly to virtual machines as it unnecessarily touches all 1611 * pages. 1612 * 1613 * A general name is used as the code may be extended to support 1614 * additional tests beyond the current "page present" test. 1615 */ 1616 memtest = 0; 1617 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1618 1619 /* 1620 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1621 * in the system. 1622 */ 1623 if (Maxmem > atop(physmap[physmap_idx + 1])) 1624 Maxmem = atop(physmap[physmap_idx + 1]); 1625 1626 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1627 (boothowto & RB_VERBOSE)) 1628 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1629 1630 /* call pmap initialization to make new kernel address space */ 1631 pmap_bootstrap(&first); 1632 1633 /* 1634 * Size up each available chunk of physical memory. 1635 * 1636 * XXX Some BIOSes corrupt low 64KB between suspend and resume. 1637 * By default, mask off the first 16 pages unless we appear to be 1638 * running in a VM. 1639 */ 1640 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT; 1641 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start); 1642 if (physmem_start < PAGE_SIZE) 1643 physmap[0] = PAGE_SIZE; 1644 else if (physmem_start >= physmap[1]) 1645 physmap[0] = round_page(physmap[1] - PAGE_SIZE); 1646 else 1647 physmap[0] = round_page(physmem_start); 1648 pa_indx = 0; 1649 da_indx = 1; 1650 phys_avail[pa_indx++] = physmap[0]; 1651 phys_avail[pa_indx] = physmap[0]; 1652 dump_avail[da_indx] = physmap[0]; 1653 pte = CMAP1; 1654 1655 /* 1656 * Get dcons buffer address 1657 */ 1658 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1659 getenv_quad("dcons.size", &dcons_size) == 0) 1660 dcons_addr = 0; 1661 1662 /* 1663 * physmap is in bytes, so when converting to page boundaries, 1664 * round up the start address and round down the end address. 1665 */ 1666 page_counter = 0; 1667 if (memtest != 0) 1668 printf("Testing system memory"); 1669 for (i = 0; i <= physmap_idx; i += 2) { 1670 vm_paddr_t end; 1671 1672 end = ptoa((vm_paddr_t)Maxmem); 1673 if (physmap[i + 1] < end) 1674 end = trunc_page(physmap[i + 1]); 1675 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1676 int tmp, page_bad, full; 1677 int *ptr = (int *)CADDR1; 1678 1679 full = FALSE; 1680 /* 1681 * block out kernel memory as not available. 1682 */ 1683 if (pa >= (vm_paddr_t)kernphys && pa < first) 1684 goto do_dump_avail; 1685 1686 /* 1687 * block out dcons buffer 1688 */ 1689 if (dcons_addr > 0 1690 && pa >= trunc_page(dcons_addr) 1691 && pa < dcons_addr + dcons_size) 1692 goto do_dump_avail; 1693 1694 page_bad = FALSE; 1695 if (memtest == 0) 1696 goto skip_memtest; 1697 1698 /* 1699 * Print a "." every GB to show we're making 1700 * progress. 1701 */ 1702 page_counter++; 1703 if ((page_counter % PAGES_PER_GB) == 0) 1704 printf("."); 1705 1706 /* 1707 * map page into kernel: valid, read/write,non-cacheable 1708 */ 1709 *pte = pa | PG_V | PG_RW | PG_NC_PWT | PG_NC_PCD; 1710 invltlb(); 1711 1712 tmp = *(int *)ptr; 1713 /* 1714 * Test for alternating 1's and 0's 1715 */ 1716 *(volatile int *)ptr = 0xaaaaaaaa; 1717 if (*(volatile int *)ptr != 0xaaaaaaaa) 1718 page_bad = TRUE; 1719 /* 1720 * Test for alternating 0's and 1's 1721 */ 1722 *(volatile int *)ptr = 0x55555555; 1723 if (*(volatile int *)ptr != 0x55555555) 1724 page_bad = TRUE; 1725 /* 1726 * Test for all 1's 1727 */ 1728 *(volatile int *)ptr = 0xffffffff; 1729 if (*(volatile int *)ptr != 0xffffffff) 1730 page_bad = TRUE; 1731 /* 1732 * Test for all 0's 1733 */ 1734 *(volatile int *)ptr = 0x0; 1735 if (*(volatile int *)ptr != 0x0) 1736 page_bad = TRUE; 1737 /* 1738 * Restore original value. 1739 */ 1740 *(int *)ptr = tmp; 1741 1742skip_memtest: 1743 /* 1744 * Adjust array of valid/good pages. 1745 */ 1746 if (page_bad == TRUE) 1747 continue; 1748 /* 1749 * If this good page is a continuation of the 1750 * previous set of good pages, then just increase 1751 * the end pointer. Otherwise start a new chunk. 1752 * Note that "end" points one higher than end, 1753 * making the range >= start and < end. 1754 * If we're also doing a speculative memory 1755 * test and we at or past the end, bump up Maxmem 1756 * so that we keep going. The first bad page 1757 * will terminate the loop. 1758 */ 1759 if (phys_avail[pa_indx] == pa) { 1760 phys_avail[pa_indx] += PAGE_SIZE; 1761 } else { 1762 pa_indx++; 1763 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1764 printf( 1765 "Too many holes in the physical address space, giving up\n"); 1766 pa_indx--; 1767 full = TRUE; 1768 goto do_dump_avail; 1769 } 1770 phys_avail[pa_indx++] = pa; /* start */ 1771 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1772 } 1773 physmem++; 1774do_dump_avail: 1775 if (dump_avail[da_indx] == pa) { 1776 dump_avail[da_indx] += PAGE_SIZE; 1777 } else { 1778 da_indx++; 1779 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1780 da_indx--; 1781 goto do_next; 1782 } 1783 dump_avail[da_indx++] = pa; /* start */ 1784 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1785 } 1786do_next: 1787 if (full) 1788 break; 1789 } 1790 } 1791 *pte = 0; 1792 invltlb(); 1793 if (memtest != 0) 1794 printf("\n"); 1795 1796 /* 1797 * XXX 1798 * The last chunk must contain at least one page plus the message 1799 * buffer to avoid complicating other code (message buffer address 1800 * calculation, etc.). 1801 */ 1802 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1803 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1804 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1805 phys_avail[pa_indx--] = 0; 1806 phys_avail[pa_indx--] = 0; 1807 } 1808 1809 Maxmem = atop(phys_avail[pa_indx]); 1810 1811 /* Trim off space for the message buffer. */ 1812 phys_avail[pa_indx] -= round_page(msgbufsize); 1813 1814 /* Map the message buffer. */ 1815 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1816} 1817 1818u_int64_t 1819hammer_time(u_int64_t modulep, u_int64_t physfree) 1820{ 1821 caddr_t kmdp; 1822 int gsel_tss, x; 1823 struct pcpu *pc; 1824 struct nmi_pcpu *np; 1825 struct xstate_hdr *xhdr; 1826 u_int64_t msr; 1827 char *env; 1828 size_t kstack0_sz; 1829 1830 thread0.td_kstack = physfree + KERNBASE; 1831 thread0.td_kstack_pages = KSTACK_PAGES; 1832 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1833 bzero((void *)thread0.td_kstack, kstack0_sz); 1834 physfree += kstack0_sz; 1835 1836 /* 1837 * This may be done better later if it gets more high level 1838 * components in it. If so just link td->td_proc here. 1839 */ 1840 proc_linkup0(&proc0, &thread0); 1841 1842 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1843 preload_bootstrap_relocate(KERNBASE); 1844 kmdp = preload_search_by_type("elf kernel"); 1845 if (kmdp == NULL) 1846 kmdp = preload_search_by_type("elf64 kernel"); 1847 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1848 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1849#ifdef DDB 1850 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1851 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1852#endif 1853 1854 /* Init basic tunables, hz etc */ 1855 init_param1(); 1856 1857 /* 1858 * make gdt memory segments 1859 */ 1860 for (x = 0; x < NGDT; x++) { 1861 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1862 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1863 ssdtosd(&gdt_segs[x], &gdt[x]); 1864 } 1865 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1866 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1867 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1868 1869 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1870 r_gdt.rd_base = (long) gdt; 1871 lgdt(&r_gdt); 1872 pc = &__pcpu[0]; 1873 1874 wrmsr(MSR_FSBASE, 0); /* User value */ 1875 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1876 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1877 1878 pcpu_init(pc, 0, sizeof(struct pcpu)); 1879 dpcpu_init((void *)(physfree + KERNBASE), 0); 1880 physfree += DPCPU_SIZE; 1881 PCPU_SET(prvspace, pc); 1882 PCPU_SET(curthread, &thread0); 1883 PCPU_SET(tssp, &common_tss[0]); 1884 PCPU_SET(commontssp, &common_tss[0]); 1885 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1886 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1887 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1888 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1889 1890 /* 1891 * Initialize mutexes. 1892 * 1893 * icu_lock: in order to allow an interrupt to occur in a critical 1894 * section, to set pcpu->ipending (etc...) properly, we 1895 * must be able to get the icu lock, so it can't be 1896 * under witness. 1897 */ 1898 mutex_init(); 1899 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1900 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1901 1902 /* exceptions */ 1903 for (x = 0; x < NIDT; x++) 1904 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1905 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1906 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1907 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1908 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1909 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1910 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1911 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1912 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1913 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1914 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1915 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1916 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1917 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1918 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1919 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1920 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1921 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1922 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1923 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1924#ifdef KDTRACE_HOOKS 1925 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1926#endif 1927#ifdef XENHVM 1928 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall), SDT_SYSIGT, SEL_UPL, 0); 1929#endif 1930 1931 r_idt.rd_limit = sizeof(idt0) - 1; 1932 r_idt.rd_base = (long) idt; 1933 lidt(&r_idt); 1934 1935 /* 1936 * Initialize the i8254 before the console so that console 1937 * initialization can use DELAY(). 1938 */ 1939 i8254_init(); 1940 1941 /* 1942 * Use vt(4) by default for UEFI boot (during the sc(4)/vt(4) 1943 * transition). 1944 */ 1945 if (kmdp != NULL && preload_search_info(kmdp, 1946 MODINFO_METADATA | MODINFOMD_EFI_MAP) != NULL) 1947 vty_set_preferred(VTY_VT); 1948 1949 identify_cpu(); /* Final stage of CPU initialization */ 1950 initializecpu(); /* Initialize CPU registers */ 1951 initializecpucache(); 1952 1953 /* doublefault stack space, runs on ist1 */ 1954 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1955 1956 /* 1957 * NMI stack, runs on ist2. The pcpu pointer is stored just 1958 * above the start of the ist2 stack. 1959 */ 1960 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1961 np->np_pcpu = (register_t) pc; 1962 common_tss[0].tss_ist2 = (long) np; 1963 1964 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1965 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1966 IOPAGES * PAGE_SIZE; 1967 1968 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1969 ltr(gsel_tss); 1970 1971 /* Set up the fast syscall stuff */ 1972 msr = rdmsr(MSR_EFER) | EFER_SCE; 1973 wrmsr(MSR_EFER, msr); 1974 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1975 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1976 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1977 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1978 wrmsr(MSR_STAR, msr); 1979 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1980 1981 getmemsize(kmdp, physfree); 1982 init_param2(physmem); 1983 1984 /* now running on new page tables, configured,and u/iom is accessible */ 1985 1986 cninit(); 1987 1988#ifdef DEV_ISA 1989#ifdef DEV_ATPIC 1990 elcr_probe(); 1991 atpic_startup(); 1992#else 1993 /* Reset and mask the atpics and leave them shut down. */ 1994 atpic_reset(); 1995 1996 /* 1997 * Point the ICU spurious interrupt vectors at the APIC spurious 1998 * interrupt handler. 1999 */ 2000 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 2001 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 2002#endif 2003#else 2004#error "have you forgotten the isa device?"; 2005#endif 2006 2007 kdb_init(); 2008 2009#ifdef KDB 2010 if (boothowto & RB_KDB) 2011 kdb_enter(KDB_WHY_BOOTFLAGS, 2012 "Boot flags requested debugger"); 2013#endif 2014 2015 msgbufinit(msgbufp, msgbufsize); 2016 fpuinit(); 2017 2018 /* 2019 * Set up thread0 pcb after fpuinit calculated pcb + fpu save 2020 * area size. Zero out the extended state header in fpu save 2021 * area. 2022 */ 2023 thread0.td_pcb = get_pcb_td(&thread0); 2024 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size); 2025 if (use_xsave) { 2026 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) + 2027 1); 2028 xhdr->xstate_bv = xsave_mask; 2029 } 2030 /* make an initial tss so cpu can get interrupt stack on syscall! */ 2031 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb; 2032 /* Ensure the stack is aligned to 16 bytes */ 2033 common_tss[0].tss_rsp0 &= ~0xFul; 2034 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 2035 PCPU_SET(curpcb, thread0.td_pcb); 2036 2037 /* transfer to user mode */ 2038 2039 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2040 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2041 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2042 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 2043 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 2044 2045 load_ds(_udatasel); 2046 load_es(_udatasel); 2047 load_fs(_ufssel); 2048 2049 /* setup proc 0's pcb */ 2050 thread0.td_pcb->pcb_flags = 0; 2051 thread0.td_pcb->pcb_cr3 = KPML4phys; /* PCID 0 is reserved for kernel */ 2052 thread0.td_frame = &proc0_tf; 2053 2054 env = getenv("kernelname"); 2055 if (env != NULL) 2056 strlcpy(kernelname, env, sizeof(kernelname)); 2057 2058 cpu_probe_amdc1e(); 2059 2060#ifdef FDT 2061 x86_init_fdt(); 2062#endif 2063 2064 /* Location of kernel stack for locore */ 2065 return ((u_int64_t)thread0.td_pcb); 2066} 2067 2068void 2069cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 2070{ 2071 2072 pcpu->pc_acpi_id = 0xffffffff; 2073} 2074 2075static int 2076smap_sysctl_handler(SYSCTL_HANDLER_ARGS) 2077{ 2078 struct bios_smap *smapbase; 2079 struct bios_smap_xattr smap; 2080 caddr_t kmdp; 2081 uint32_t *smapattr; 2082 int count, error, i; 2083 2084 /* Retrieve the system memory map from the loader. */ 2085 kmdp = preload_search_by_type("elf kernel"); 2086 if (kmdp == NULL) 2087 kmdp = preload_search_by_type("elf64 kernel"); 2088 smapbase = (struct bios_smap *)preload_search_info(kmdp, 2089 MODINFO_METADATA | MODINFOMD_SMAP); 2090 if (smapbase == NULL) 2091 return (0); 2092 smapattr = (uint32_t *)preload_search_info(kmdp, 2093 MODINFO_METADATA | MODINFOMD_SMAP_XATTR); 2094 count = *((uint32_t *)smapbase - 1) / sizeof(*smapbase); 2095 error = 0; 2096 for (i = 0; i < count; i++) { 2097 smap.base = smapbase[i].base; 2098 smap.length = smapbase[i].length; 2099 smap.type = smapbase[i].type; 2100 if (smapattr != NULL) 2101 smap.xattr = smapattr[i]; 2102 else 2103 smap.xattr = 0; 2104 error = SYSCTL_OUT(req, &smap, sizeof(smap)); 2105 } 2106 return (error); 2107} 2108SYSCTL_PROC(_machdep, OID_AUTO, smap, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 2109 smap_sysctl_handler, "S,bios_smap_xattr", "Raw BIOS SMAP data"); 2110 2111static int 2112efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS) 2113{ 2114 struct efi_map_header *efihdr; 2115 caddr_t kmdp; 2116 uint32_t efisize; 2117 2118 kmdp = preload_search_by_type("elf kernel"); 2119 if (kmdp == NULL) 2120 kmdp = preload_search_by_type("elf64 kernel"); 2121 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 2122 MODINFO_METADATA | MODINFOMD_EFI_MAP); 2123 if (efihdr == NULL) 2124 return (0); 2125 efisize = *((uint32_t *)efihdr - 1); 2126 return (SYSCTL_OUT(req, efihdr, efisize)); 2127} 2128SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0, 2129 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map"); 2130 2131void 2132spinlock_enter(void) 2133{ 2134 struct thread *td; 2135 register_t flags; 2136 2137 td = curthread; 2138 if (td->td_md.md_spinlock_count == 0) { 2139 flags = intr_disable(); 2140 td->td_md.md_spinlock_count = 1; 2141 td->td_md.md_saved_flags = flags; 2142 } else 2143 td->td_md.md_spinlock_count++; 2144 critical_enter(); 2145} 2146 2147void 2148spinlock_exit(void) 2149{ 2150 struct thread *td; 2151 register_t flags; 2152 2153 td = curthread; 2154 critical_exit(); 2155 flags = td->td_md.md_saved_flags; 2156 td->td_md.md_spinlock_count--; 2157 if (td->td_md.md_spinlock_count == 0) 2158 intr_restore(flags); 2159} 2160 2161/* 2162 * Construct a PCB from a trapframe. This is called from kdb_trap() where 2163 * we want to start a backtrace from the function that caused us to enter 2164 * the debugger. We have the context in the trapframe, but base the trace 2165 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 2166 * enough for a backtrace. 2167 */ 2168void 2169makectx(struct trapframe *tf, struct pcb *pcb) 2170{ 2171 2172 pcb->pcb_r12 = tf->tf_r12; 2173 pcb->pcb_r13 = tf->tf_r13; 2174 pcb->pcb_r14 = tf->tf_r14; 2175 pcb->pcb_r15 = tf->tf_r15; 2176 pcb->pcb_rbp = tf->tf_rbp; 2177 pcb->pcb_rbx = tf->tf_rbx; 2178 pcb->pcb_rip = tf->tf_rip; 2179 pcb->pcb_rsp = tf->tf_rsp; 2180} 2181 2182int 2183ptrace_set_pc(struct thread *td, unsigned long addr) 2184{ 2185 2186 td->td_frame->tf_rip = addr; 2187 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2188 return (0); 2189} 2190 2191int 2192ptrace_single_step(struct thread *td) 2193{ 2194 td->td_frame->tf_rflags |= PSL_T; 2195 return (0); 2196} 2197 2198int 2199ptrace_clear_single_step(struct thread *td) 2200{ 2201 td->td_frame->tf_rflags &= ~PSL_T; 2202 return (0); 2203} 2204 2205int 2206fill_regs(struct thread *td, struct reg *regs) 2207{ 2208 struct trapframe *tp; 2209 2210 tp = td->td_frame; 2211 return (fill_frame_regs(tp, regs)); 2212} 2213 2214int 2215fill_frame_regs(struct trapframe *tp, struct reg *regs) 2216{ 2217 regs->r_r15 = tp->tf_r15; 2218 regs->r_r14 = tp->tf_r14; 2219 regs->r_r13 = tp->tf_r13; 2220 regs->r_r12 = tp->tf_r12; 2221 regs->r_r11 = tp->tf_r11; 2222 regs->r_r10 = tp->tf_r10; 2223 regs->r_r9 = tp->tf_r9; 2224 regs->r_r8 = tp->tf_r8; 2225 regs->r_rdi = tp->tf_rdi; 2226 regs->r_rsi = tp->tf_rsi; 2227 regs->r_rbp = tp->tf_rbp; 2228 regs->r_rbx = tp->tf_rbx; 2229 regs->r_rdx = tp->tf_rdx; 2230 regs->r_rcx = tp->tf_rcx; 2231 regs->r_rax = tp->tf_rax; 2232 regs->r_rip = tp->tf_rip; 2233 regs->r_cs = tp->tf_cs; 2234 regs->r_rflags = tp->tf_rflags; 2235 regs->r_rsp = tp->tf_rsp; 2236 regs->r_ss = tp->tf_ss; 2237 if (tp->tf_flags & TF_HASSEGS) { 2238 regs->r_ds = tp->tf_ds; 2239 regs->r_es = tp->tf_es; 2240 regs->r_fs = tp->tf_fs; 2241 regs->r_gs = tp->tf_gs; 2242 } else { 2243 regs->r_ds = 0; 2244 regs->r_es = 0; 2245 regs->r_fs = 0; 2246 regs->r_gs = 0; 2247 } 2248 return (0); 2249} 2250 2251int 2252set_regs(struct thread *td, struct reg *regs) 2253{ 2254 struct trapframe *tp; 2255 register_t rflags; 2256 2257 tp = td->td_frame; 2258 rflags = regs->r_rflags & 0xffffffff; 2259 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 2260 return (EINVAL); 2261 tp->tf_r15 = regs->r_r15; 2262 tp->tf_r14 = regs->r_r14; 2263 tp->tf_r13 = regs->r_r13; 2264 tp->tf_r12 = regs->r_r12; 2265 tp->tf_r11 = regs->r_r11; 2266 tp->tf_r10 = regs->r_r10; 2267 tp->tf_r9 = regs->r_r9; 2268 tp->tf_r8 = regs->r_r8; 2269 tp->tf_rdi = regs->r_rdi; 2270 tp->tf_rsi = regs->r_rsi; 2271 tp->tf_rbp = regs->r_rbp; 2272 tp->tf_rbx = regs->r_rbx; 2273 tp->tf_rdx = regs->r_rdx; 2274 tp->tf_rcx = regs->r_rcx; 2275 tp->tf_rax = regs->r_rax; 2276 tp->tf_rip = regs->r_rip; 2277 tp->tf_cs = regs->r_cs; 2278 tp->tf_rflags = rflags; 2279 tp->tf_rsp = regs->r_rsp; 2280 tp->tf_ss = regs->r_ss; 2281 if (0) { /* XXXKIB */ 2282 tp->tf_ds = regs->r_ds; 2283 tp->tf_es = regs->r_es; 2284 tp->tf_fs = regs->r_fs; 2285 tp->tf_gs = regs->r_gs; 2286 tp->tf_flags = TF_HASSEGS; 2287 } 2288 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2289 return (0); 2290} 2291 2292/* XXX check all this stuff! */ 2293/* externalize from sv_xmm */ 2294static void 2295fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 2296{ 2297 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2298 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2299 int i; 2300 2301 /* pcb -> fpregs */ 2302 bzero(fpregs, sizeof(*fpregs)); 2303 2304 /* FPU control/status */ 2305 penv_fpreg->en_cw = penv_xmm->en_cw; 2306 penv_fpreg->en_sw = penv_xmm->en_sw; 2307 penv_fpreg->en_tw = penv_xmm->en_tw; 2308 penv_fpreg->en_opcode = penv_xmm->en_opcode; 2309 penv_fpreg->en_rip = penv_xmm->en_rip; 2310 penv_fpreg->en_rdp = penv_xmm->en_rdp; 2311 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 2312 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 2313 2314 /* FPU registers */ 2315 for (i = 0; i < 8; ++i) 2316 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 2317 2318 /* SSE registers */ 2319 for (i = 0; i < 16; ++i) 2320 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 2321} 2322 2323/* internalize from fpregs into sv_xmm */ 2324static void 2325set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 2326{ 2327 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2328 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2329 int i; 2330 2331 /* fpregs -> pcb */ 2332 /* FPU control/status */ 2333 penv_xmm->en_cw = penv_fpreg->en_cw; 2334 penv_xmm->en_sw = penv_fpreg->en_sw; 2335 penv_xmm->en_tw = penv_fpreg->en_tw; 2336 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2337 penv_xmm->en_rip = penv_fpreg->en_rip; 2338 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2339 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2340 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2341 2342 /* FPU registers */ 2343 for (i = 0; i < 8; ++i) 2344 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2345 2346 /* SSE registers */ 2347 for (i = 0; i < 16; ++i) 2348 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2349} 2350 2351/* externalize from td->pcb */ 2352int 2353fill_fpregs(struct thread *td, struct fpreg *fpregs) 2354{ 2355 2356 KASSERT(td == curthread || TD_IS_SUSPENDED(td) || 2357 P_SHOULDSTOP(td->td_proc), 2358 ("not suspended thread %p", td)); 2359 fpugetregs(td); 2360 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs); 2361 return (0); 2362} 2363 2364/* internalize to td->pcb */ 2365int 2366set_fpregs(struct thread *td, struct fpreg *fpregs) 2367{ 2368 2369 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td)); 2370 fpuuserinited(td); 2371 return (0); 2372} 2373 2374/* 2375 * Get machine context. 2376 */ 2377int 2378get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2379{ 2380 struct pcb *pcb; 2381 struct trapframe *tp; 2382 2383 pcb = td->td_pcb; 2384 tp = td->td_frame; 2385 PROC_LOCK(curthread->td_proc); 2386 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2387 PROC_UNLOCK(curthread->td_proc); 2388 mcp->mc_r15 = tp->tf_r15; 2389 mcp->mc_r14 = tp->tf_r14; 2390 mcp->mc_r13 = tp->tf_r13; 2391 mcp->mc_r12 = tp->tf_r12; 2392 mcp->mc_r11 = tp->tf_r11; 2393 mcp->mc_r10 = tp->tf_r10; 2394 mcp->mc_r9 = tp->tf_r9; 2395 mcp->mc_r8 = tp->tf_r8; 2396 mcp->mc_rdi = tp->tf_rdi; 2397 mcp->mc_rsi = tp->tf_rsi; 2398 mcp->mc_rbp = tp->tf_rbp; 2399 mcp->mc_rbx = tp->tf_rbx; 2400 mcp->mc_rcx = tp->tf_rcx; 2401 mcp->mc_rflags = tp->tf_rflags; 2402 if (flags & GET_MC_CLEAR_RET) { 2403 mcp->mc_rax = 0; 2404 mcp->mc_rdx = 0; 2405 mcp->mc_rflags &= ~PSL_C; 2406 } else { 2407 mcp->mc_rax = tp->tf_rax; 2408 mcp->mc_rdx = tp->tf_rdx; 2409 } 2410 mcp->mc_rip = tp->tf_rip; 2411 mcp->mc_cs = tp->tf_cs; 2412 mcp->mc_rsp = tp->tf_rsp; 2413 mcp->mc_ss = tp->tf_ss; 2414 mcp->mc_ds = tp->tf_ds; 2415 mcp->mc_es = tp->tf_es; 2416 mcp->mc_fs = tp->tf_fs; 2417 mcp->mc_gs = tp->tf_gs; 2418 mcp->mc_flags = tp->tf_flags; 2419 mcp->mc_len = sizeof(*mcp); 2420 get_fpcontext(td, mcp, NULL, 0); 2421 mcp->mc_fsbase = pcb->pcb_fsbase; 2422 mcp->mc_gsbase = pcb->pcb_gsbase; 2423 mcp->mc_xfpustate = 0; 2424 mcp->mc_xfpustate_len = 0; 2425 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2426 return (0); 2427} 2428 2429/* 2430 * Set machine context. 2431 * 2432 * However, we don't set any but the user modifiable flags, and we won't 2433 * touch the cs selector. 2434 */ 2435int 2436set_mcontext(struct thread *td, mcontext_t *mcp) 2437{ 2438 struct pcb *pcb; 2439 struct trapframe *tp; 2440 char *xfpustate; 2441 long rflags; 2442 int ret; 2443 2444 pcb = td->td_pcb; 2445 tp = td->td_frame; 2446 if (mcp->mc_len != sizeof(*mcp) || 2447 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2448 return (EINVAL); 2449 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2450 (tp->tf_rflags & ~PSL_USERCHANGE); 2451 if (mcp->mc_flags & _MC_HASFPXSTATE) { 2452 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size - 2453 sizeof(struct savefpu)) 2454 return (EINVAL); 2455 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len); 2456 ret = copyin((void *)mcp->mc_xfpustate, xfpustate, 2457 mcp->mc_xfpustate_len); 2458 if (ret != 0) 2459 return (ret); 2460 } else 2461 xfpustate = NULL; 2462 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len); 2463 if (ret != 0) 2464 return (ret); 2465 tp->tf_r15 = mcp->mc_r15; 2466 tp->tf_r14 = mcp->mc_r14; 2467 tp->tf_r13 = mcp->mc_r13; 2468 tp->tf_r12 = mcp->mc_r12; 2469 tp->tf_r11 = mcp->mc_r11; 2470 tp->tf_r10 = mcp->mc_r10; 2471 tp->tf_r9 = mcp->mc_r9; 2472 tp->tf_r8 = mcp->mc_r8; 2473 tp->tf_rdi = mcp->mc_rdi; 2474 tp->tf_rsi = mcp->mc_rsi; 2475 tp->tf_rbp = mcp->mc_rbp; 2476 tp->tf_rbx = mcp->mc_rbx; 2477 tp->tf_rdx = mcp->mc_rdx; 2478 tp->tf_rcx = mcp->mc_rcx; 2479 tp->tf_rax = mcp->mc_rax; 2480 tp->tf_rip = mcp->mc_rip; 2481 tp->tf_rflags = rflags; 2482 tp->tf_rsp = mcp->mc_rsp; 2483 tp->tf_ss = mcp->mc_ss; 2484 tp->tf_flags = mcp->mc_flags; 2485 if (tp->tf_flags & TF_HASSEGS) { 2486 tp->tf_ds = mcp->mc_ds; 2487 tp->tf_es = mcp->mc_es; 2488 tp->tf_fs = mcp->mc_fs; 2489 tp->tf_gs = mcp->mc_gs; 2490 } 2491 if (mcp->mc_flags & _MC_HASBASES) { 2492 pcb->pcb_fsbase = mcp->mc_fsbase; 2493 pcb->pcb_gsbase = mcp->mc_gsbase; 2494 } 2495 set_pcb_flags(pcb, PCB_FULL_IRET); 2496 return (0); 2497} 2498 2499static void 2500get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave, 2501 size_t xfpusave_len) 2502{ 2503 size_t max_len, len; 2504 2505 mcp->mc_ownedfp = fpugetregs(td); 2506 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0], 2507 sizeof(mcp->mc_fpstate)); 2508 mcp->mc_fpformat = fpuformat(); 2509 if (!use_xsave || xfpusave_len == 0) 2510 return; 2511 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 2512 len = xfpusave_len; 2513 if (len > max_len) { 2514 len = max_len; 2515 bzero(xfpusave + max_len, len - max_len); 2516 } 2517 mcp->mc_flags |= _MC_HASFPXSTATE; 2518 mcp->mc_xfpustate_len = len; 2519 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len); 2520} 2521 2522static int 2523set_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpustate, 2524 size_t xfpustate_len) 2525{ 2526 struct savefpu *fpstate; 2527 int error; 2528 2529 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2530 return (0); 2531 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2532 return (EINVAL); 2533 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) { 2534 /* We don't care what state is left in the FPU or PCB. */ 2535 fpstate_drop(td); 2536 error = 0; 2537 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2538 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2539 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2540 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2541 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len); 2542 } else 2543 return (EINVAL); 2544 return (error); 2545} 2546 2547void 2548fpstate_drop(struct thread *td) 2549{ 2550 2551 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2552 critical_enter(); 2553 if (PCPU_GET(fpcurthread) == td) 2554 fpudrop(); 2555 /* 2556 * XXX force a full drop of the fpu. The above only drops it if we 2557 * owned it. 2558 * 2559 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2560 * drop. Dropping only to the pcb matches fnsave's behaviour. 2561 * We only need to drop to !PCB_INITDONE in sendsig(). But 2562 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2563 * have too many layers. 2564 */ 2565 clear_pcb_flags(curthread->td_pcb, 2566 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2567 critical_exit(); 2568} 2569 2570int 2571fill_dbregs(struct thread *td, struct dbreg *dbregs) 2572{ 2573 struct pcb *pcb; 2574 2575 if (td == NULL) { 2576 dbregs->dr[0] = rdr0(); 2577 dbregs->dr[1] = rdr1(); 2578 dbregs->dr[2] = rdr2(); 2579 dbregs->dr[3] = rdr3(); 2580 dbregs->dr[6] = rdr6(); 2581 dbregs->dr[7] = rdr7(); 2582 } else { 2583 pcb = td->td_pcb; 2584 dbregs->dr[0] = pcb->pcb_dr0; 2585 dbregs->dr[1] = pcb->pcb_dr1; 2586 dbregs->dr[2] = pcb->pcb_dr2; 2587 dbregs->dr[3] = pcb->pcb_dr3; 2588 dbregs->dr[6] = pcb->pcb_dr6; 2589 dbregs->dr[7] = pcb->pcb_dr7; 2590 } 2591 dbregs->dr[4] = 0; 2592 dbregs->dr[5] = 0; 2593 dbregs->dr[8] = 0; 2594 dbregs->dr[9] = 0; 2595 dbregs->dr[10] = 0; 2596 dbregs->dr[11] = 0; 2597 dbregs->dr[12] = 0; 2598 dbregs->dr[13] = 0; 2599 dbregs->dr[14] = 0; 2600 dbregs->dr[15] = 0; 2601 return (0); 2602} 2603 2604int 2605set_dbregs(struct thread *td, struct dbreg *dbregs) 2606{ 2607 struct pcb *pcb; 2608 int i; 2609 2610 if (td == NULL) { 2611 load_dr0(dbregs->dr[0]); 2612 load_dr1(dbregs->dr[1]); 2613 load_dr2(dbregs->dr[2]); 2614 load_dr3(dbregs->dr[3]); 2615 load_dr6(dbregs->dr[6]); 2616 load_dr7(dbregs->dr[7]); 2617 } else { 2618 /* 2619 * Don't let an illegal value for dr7 get set. Specifically, 2620 * check for undefined settings. Setting these bit patterns 2621 * result in undefined behaviour and can lead to an unexpected 2622 * TRCTRAP or a general protection fault right here. 2623 * Upper bits of dr6 and dr7 must not be set 2624 */ 2625 for (i = 0; i < 4; i++) { 2626 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2627 return (EINVAL); 2628 if (td->td_frame->tf_cs == _ucode32sel && 2629 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2630 return (EINVAL); 2631 } 2632 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2633 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2634 return (EINVAL); 2635 2636 pcb = td->td_pcb; 2637 2638 /* 2639 * Don't let a process set a breakpoint that is not within the 2640 * process's address space. If a process could do this, it 2641 * could halt the system by setting a breakpoint in the kernel 2642 * (if ddb was enabled). Thus, we need to check to make sure 2643 * that no breakpoints are being enabled for addresses outside 2644 * process's address space. 2645 * 2646 * XXX - what about when the watched area of the user's 2647 * address space is written into from within the kernel 2648 * ... wouldn't that still cause a breakpoint to be generated 2649 * from within kernel mode? 2650 */ 2651 2652 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2653 /* dr0 is enabled */ 2654 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2655 return (EINVAL); 2656 } 2657 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2658 /* dr1 is enabled */ 2659 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2660 return (EINVAL); 2661 } 2662 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2663 /* dr2 is enabled */ 2664 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2665 return (EINVAL); 2666 } 2667 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2668 /* dr3 is enabled */ 2669 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2670 return (EINVAL); 2671 } 2672 2673 pcb->pcb_dr0 = dbregs->dr[0]; 2674 pcb->pcb_dr1 = dbregs->dr[1]; 2675 pcb->pcb_dr2 = dbregs->dr[2]; 2676 pcb->pcb_dr3 = dbregs->dr[3]; 2677 pcb->pcb_dr6 = dbregs->dr[6]; 2678 pcb->pcb_dr7 = dbregs->dr[7]; 2679 2680 set_pcb_flags(pcb, PCB_DBREGS); 2681 } 2682 2683 return (0); 2684} 2685 2686void 2687reset_dbregs(void) 2688{ 2689 2690 load_dr7(0); /* Turn off the control bits first */ 2691 load_dr0(0); 2692 load_dr1(0); 2693 load_dr2(0); 2694 load_dr3(0); 2695 load_dr6(0); 2696} 2697 2698/* 2699 * Return > 0 if a hardware breakpoint has been hit, and the 2700 * breakpoint was in user space. Return 0, otherwise. 2701 */ 2702int 2703user_dbreg_trap(void) 2704{ 2705 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2706 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2707 int nbp; /* number of breakpoints that triggered */ 2708 caddr_t addr[4]; /* breakpoint addresses */ 2709 int i; 2710 2711 dr7 = rdr7(); 2712 if ((dr7 & 0x000000ff) == 0) { 2713 /* 2714 * all GE and LE bits in the dr7 register are zero, 2715 * thus the trap couldn't have been caused by the 2716 * hardware debug registers 2717 */ 2718 return 0; 2719 } 2720 2721 nbp = 0; 2722 dr6 = rdr6(); 2723 bp = dr6 & 0x0000000f; 2724 2725 if (!bp) { 2726 /* 2727 * None of the breakpoint bits are set meaning this 2728 * trap was not caused by any of the debug registers 2729 */ 2730 return 0; 2731 } 2732 2733 /* 2734 * at least one of the breakpoints were hit, check to see 2735 * which ones and if any of them are user space addresses 2736 */ 2737 2738 if (bp & 0x01) { 2739 addr[nbp++] = (caddr_t)rdr0(); 2740 } 2741 if (bp & 0x02) { 2742 addr[nbp++] = (caddr_t)rdr1(); 2743 } 2744 if (bp & 0x04) { 2745 addr[nbp++] = (caddr_t)rdr2(); 2746 } 2747 if (bp & 0x08) { 2748 addr[nbp++] = (caddr_t)rdr3(); 2749 } 2750 2751 for (i = 0; i < nbp; i++) { 2752 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2753 /* 2754 * addr[i] is in user space 2755 */ 2756 return nbp; 2757 } 2758 } 2759 2760 /* 2761 * None of the breakpoints are in user space. 2762 */ 2763 return 0; 2764} 2765 2766#ifdef KDB 2767 2768/* 2769 * Provide inb() and outb() as functions. They are normally only available as 2770 * inline functions, thus cannot be called from the debugger. 2771 */ 2772 2773/* silence compiler warnings */ 2774u_char inb_(u_short); 2775void outb_(u_short, u_char); 2776 2777u_char 2778inb_(u_short port) 2779{ 2780 return inb(port); 2781} 2782 2783void 2784outb_(u_short port, u_char data) 2785{ 2786 outb(port, data); 2787} 2788 2789#endif /* KDB */ 2790