machdep.c revision 261275
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: stable/10/sys/amd64/amd64/machdep.c 261275 2014-01-29 21:23:37Z jhb $"); 43 44#include "opt_atalk.h" 45#include "opt_atpic.h" 46#include "opt_compat.h" 47#include "opt_cpu.h" 48#include "opt_ddb.h" 49#include "opt_inet.h" 50#include "opt_ipx.h" 51#include "opt_isa.h" 52#include "opt_kstack_pages.h" 53#include "opt_maxmem.h" 54#include "opt_mp_watchdog.h" 55#include "opt_perfmon.h" 56#include "opt_platform.h" 57#include "opt_sched.h" 58#include "opt_kdtrace.h" 59 60#include <sys/param.h> 61#include <sys/proc.h> 62#include <sys/systm.h> 63#include <sys/bio.h> 64#include <sys/buf.h> 65#include <sys/bus.h> 66#include <sys/callout.h> 67#include <sys/cons.h> 68#include <sys/cpu.h> 69#include <sys/eventhandler.h> 70#include <sys/exec.h> 71#include <sys/imgact.h> 72#include <sys/kdb.h> 73#include <sys/kernel.h> 74#include <sys/ktr.h> 75#include <sys/linker.h> 76#include <sys/lock.h> 77#include <sys/malloc.h> 78#include <sys/memrange.h> 79#include <sys/msgbuf.h> 80#include <sys/mutex.h> 81#include <sys/pcpu.h> 82#include <sys/ptrace.h> 83#include <sys/reboot.h> 84#include <sys/rwlock.h> 85#include <sys/sched.h> 86#include <sys/signalvar.h> 87#ifdef SMP 88#include <sys/smp.h> 89#endif 90#include <sys/syscallsubr.h> 91#include <sys/sysctl.h> 92#include <sys/sysent.h> 93#include <sys/sysproto.h> 94#include <sys/ucontext.h> 95#include <sys/vmmeter.h> 96 97#include <vm/vm.h> 98#include <vm/vm_extern.h> 99#include <vm/vm_kern.h> 100#include <vm/vm_page.h> 101#include <vm/vm_map.h> 102#include <vm/vm_object.h> 103#include <vm/vm_pager.h> 104#include <vm/vm_param.h> 105 106#ifdef DDB 107#ifndef KDB 108#error KDB must be enabled in order for DDB to work! 109#endif 110#include <ddb/ddb.h> 111#include <ddb/db_sym.h> 112#endif 113 114#include <net/netisr.h> 115 116#include <machine/clock.h> 117#include <machine/cpu.h> 118#include <machine/cputypes.h> 119#include <machine/intr_machdep.h> 120#include <x86/mca.h> 121#include <machine/md_var.h> 122#include <machine/metadata.h> 123#include <machine/mp_watchdog.h> 124#include <machine/pc/bios.h> 125#include <machine/pcb.h> 126#include <machine/proc.h> 127#include <machine/reg.h> 128#include <machine/sigframe.h> 129#include <machine/specialreg.h> 130#ifdef PERFMON 131#include <machine/perfmon.h> 132#endif 133#include <machine/tss.h> 134#ifdef SMP 135#include <machine/smp.h> 136#endif 137#ifdef FDT 138#include <x86/fdt.h> 139#endif 140 141#ifdef DEV_ATPIC 142#include <x86/isa/icu.h> 143#else 144#include <machine/apicvar.h> 145#endif 146 147#include <isa/isareg.h> 148#include <isa/rtc.h> 149 150/* Sanity check for __curthread() */ 151CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 152 153extern u_int64_t hammer_time(u_int64_t, u_int64_t); 154 155extern void printcpuinfo(void); /* XXX header file */ 156extern void identify_cpu(void); 157extern void panicifcpuunsupported(void); 158 159#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 160#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 161 162static void cpu_startup(void *); 163static void get_fpcontext(struct thread *td, mcontext_t *mcp, 164 char *xfpusave, size_t xfpusave_len); 165static int set_fpcontext(struct thread *td, const mcontext_t *mcp, 166 char *xfpustate, size_t xfpustate_len); 167SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 168 169/* 170 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 171 * the physical address at which the kernel is loaded. 172 */ 173extern char kernphys[]; 174#ifdef DDB 175extern vm_offset_t ksym_start, ksym_end; 176#endif 177 178struct msgbuf *msgbufp; 179 180/* Intel ICH registers */ 181#define ICH_PMBASE 0x400 182#define ICH_SMI_EN ICH_PMBASE + 0x30 183 184int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 185 186int cold = 1; 187 188long Maxmem = 0; 189long realmem = 0; 190 191/* 192 * The number of PHYSMAP entries must be one less than the number of 193 * PHYSSEG entries because the PHYSMAP entry that spans the largest 194 * physical address that is accessible by ISA DMA is split into two 195 * PHYSSEG entries. 196 */ 197#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 198 199vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 200vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 201 202/* must be 2 less so 0 0 can signal end of chunks */ 203#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 204#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 205 206struct kva_md_info kmi; 207 208static struct trapframe proc0_tf; 209struct region_descriptor r_gdt, r_idt; 210 211struct pcpu __pcpu[MAXCPU]; 212 213struct mtx icu_lock; 214 215struct mem_range_softc mem_range_softc; 216 217struct mtx dt_lock; /* lock for GDT and LDT */ 218 219void (*vmm_resume_p)(void); 220 221static void 222cpu_startup(dummy) 223 void *dummy; 224{ 225 uintmax_t memsize; 226 char *sysenv; 227 228 /* 229 * On MacBooks, we need to disallow the legacy USB circuit to 230 * generate an SMI# because this can cause several problems, 231 * namely: incorrect CPU frequency detection and failure to 232 * start the APs. 233 * We do this by disabling a bit in the SMI_EN (SMI Control and 234 * Enable register) of the Intel ICH LPC Interface Bridge. 235 */ 236 sysenv = getenv("smbios.system.product"); 237 if (sysenv != NULL) { 238 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 239 strncmp(sysenv, "MacBook3,1", 10) == 0 || 240 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 241 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 242 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 243 strncmp(sysenv, "Macmini1,1", 10) == 0) { 244 if (bootverbose) 245 printf("Disabling LEGACY_USB_EN bit on " 246 "Intel ICH.\n"); 247 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 248 } 249 freeenv(sysenv); 250 } 251 252 /* 253 * Good {morning,afternoon,evening,night}. 254 */ 255 startrtclock(); 256 printcpuinfo(); 257 panicifcpuunsupported(); 258#ifdef PERFMON 259 perfmon_init(); 260#endif 261 262 /* 263 * Display physical memory if SMBIOS reports reasonable amount. 264 */ 265 memsize = 0; 266 sysenv = getenv("smbios.memory.enabled"); 267 if (sysenv != NULL) { 268 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 269 freeenv(sysenv); 270 } 271 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 272 memsize = ptoa((uintmax_t)Maxmem); 273 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 274 realmem = atop(memsize); 275 276 /* 277 * Display any holes after the first chunk of extended memory. 278 */ 279 if (bootverbose) { 280 int indx; 281 282 printf("Physical memory chunk(s):\n"); 283 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 284 vm_paddr_t size; 285 286 size = phys_avail[indx + 1] - phys_avail[indx]; 287 printf( 288 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 289 (uintmax_t)phys_avail[indx], 290 (uintmax_t)phys_avail[indx + 1] - 1, 291 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 292 } 293 } 294 295 vm_ksubmap_init(&kmi); 296 297 printf("avail memory = %ju (%ju MB)\n", 298 ptoa((uintmax_t)cnt.v_free_count), 299 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 300 301 /* 302 * Set up buffers, so they can be used to read disk labels. 303 */ 304 bufinit(); 305 vm_pager_bufferinit(); 306 307 cpu_setregs(); 308} 309 310/* 311 * Send an interrupt to process. 312 * 313 * Stack is set up to allow sigcode stored 314 * at top to call routine, followed by call 315 * to sigreturn routine below. After sigreturn 316 * resets the signal mask, the stack, and the 317 * frame pointer, it returns to the user 318 * specified pc, psl. 319 */ 320void 321sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 322{ 323 struct sigframe sf, *sfp; 324 struct pcb *pcb; 325 struct proc *p; 326 struct thread *td; 327 struct sigacts *psp; 328 char *sp; 329 struct trapframe *regs; 330 char *xfpusave; 331 size_t xfpusave_len; 332 int sig; 333 int oonstack; 334 335 td = curthread; 336 pcb = td->td_pcb; 337 p = td->td_proc; 338 PROC_LOCK_ASSERT(p, MA_OWNED); 339 sig = ksi->ksi_signo; 340 psp = p->p_sigacts; 341 mtx_assert(&psp->ps_mtx, MA_OWNED); 342 regs = td->td_frame; 343 oonstack = sigonstack(regs->tf_rsp); 344 345 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) { 346 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu); 347 xfpusave = __builtin_alloca(xfpusave_len); 348 } else { 349 xfpusave_len = 0; 350 xfpusave = NULL; 351 } 352 353 /* Save user context. */ 354 bzero(&sf, sizeof(sf)); 355 sf.sf_uc.uc_sigmask = *mask; 356 sf.sf_uc.uc_stack = td->td_sigstk; 357 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 358 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 359 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 360 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 361 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 362 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len); 363 fpstate_drop(td); 364 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 365 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 366 bzero(sf.sf_uc.uc_mcontext.mc_spare, 367 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 368 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 369 370 /* Allocate space for the signal handler context. */ 371 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 372 SIGISMEMBER(psp->ps_sigonstack, sig)) { 373 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size; 374#if defined(COMPAT_43) 375 td->td_sigstk.ss_flags |= SS_ONSTACK; 376#endif 377 } else 378 sp = (char *)regs->tf_rsp - 128; 379 if (xfpusave != NULL) { 380 sp -= xfpusave_len; 381 sp = (char *)((unsigned long)sp & ~0x3Ful); 382 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp; 383 } 384 sp -= sizeof(struct sigframe); 385 /* Align to 16 bytes. */ 386 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 387 388 /* Translate the signal if appropriate. */ 389 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 390 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 391 392 /* Build the argument list for the signal handler. */ 393 regs->tf_rdi = sig; /* arg 1 in %rdi */ 394 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 395 bzero(&sf.sf_si, sizeof(sf.sf_si)); 396 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 397 /* Signal handler installed with SA_SIGINFO. */ 398 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 399 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 400 401 /* Fill in POSIX parts */ 402 sf.sf_si = ksi->ksi_info; 403 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 404 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 405 } else { 406 /* Old FreeBSD-style arguments. */ 407 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 408 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 409 sf.sf_ahu.sf_handler = catcher; 410 } 411 mtx_unlock(&psp->ps_mtx); 412 PROC_UNLOCK(p); 413 414 /* 415 * Copy the sigframe out to the user's stack. 416 */ 417 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 || 418 (xfpusave != NULL && copyout(xfpusave, 419 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len) 420 != 0)) { 421#ifdef DEBUG 422 printf("process %ld has trashed its stack\n", (long)p->p_pid); 423#endif 424 PROC_LOCK(p); 425 sigexit(td, SIGILL); 426 } 427 428 regs->tf_rsp = (long)sfp; 429 regs->tf_rip = p->p_sysent->sv_sigcode_base; 430 regs->tf_rflags &= ~(PSL_T | PSL_D); 431 regs->tf_cs = _ucodesel; 432 regs->tf_ds = _udatasel; 433 regs->tf_es = _udatasel; 434 regs->tf_fs = _ufssel; 435 regs->tf_gs = _ugssel; 436 regs->tf_flags = TF_HASSEGS; 437 set_pcb_flags(pcb, PCB_FULL_IRET); 438 PROC_LOCK(p); 439 mtx_lock(&psp->ps_mtx); 440} 441 442/* 443 * System call to cleanup state after a signal 444 * has been taken. Reset signal mask and 445 * stack state from context left by sendsig (above). 446 * Return to previous pc and psl as specified by 447 * context left by sendsig. Check carefully to 448 * make sure that the user has not modified the 449 * state to gain improper privileges. 450 * 451 * MPSAFE 452 */ 453int 454sys_sigreturn(td, uap) 455 struct thread *td; 456 struct sigreturn_args /* { 457 const struct __ucontext *sigcntxp; 458 } */ *uap; 459{ 460 ucontext_t uc; 461 struct pcb *pcb; 462 struct proc *p; 463 struct trapframe *regs; 464 ucontext_t *ucp; 465 char *xfpustate; 466 size_t xfpustate_len; 467 long rflags; 468 int cs, error, ret; 469 ksiginfo_t ksi; 470 471 pcb = td->td_pcb; 472 p = td->td_proc; 473 474 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 475 if (error != 0) { 476 uprintf("pid %d (%s): sigreturn copyin failed\n", 477 p->p_pid, td->td_name); 478 return (error); 479 } 480 ucp = &uc; 481 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 482 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 483 td->td_name, ucp->uc_mcontext.mc_flags); 484 return (EINVAL); 485 } 486 regs = td->td_frame; 487 rflags = ucp->uc_mcontext.mc_rflags; 488 /* 489 * Don't allow users to change privileged or reserved flags. 490 */ 491 if (!EFL_SECURE(rflags, regs->tf_rflags)) { 492 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 493 td->td_name, rflags); 494 return (EINVAL); 495 } 496 497 /* 498 * Don't allow users to load a valid privileged %cs. Let the 499 * hardware check for invalid selectors, excess privilege in 500 * other selectors, invalid %eip's and invalid %esp's. 501 */ 502 cs = ucp->uc_mcontext.mc_cs; 503 if (!CS_SECURE(cs)) { 504 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 505 td->td_name, cs); 506 ksiginfo_init_trap(&ksi); 507 ksi.ksi_signo = SIGBUS; 508 ksi.ksi_code = BUS_OBJERR; 509 ksi.ksi_trapno = T_PROTFLT; 510 ksi.ksi_addr = (void *)regs->tf_rip; 511 trapsignal(td, &ksi); 512 return (EINVAL); 513 } 514 515 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) { 516 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len; 517 if (xfpustate_len > cpu_max_ext_state_size - 518 sizeof(struct savefpu)) { 519 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n", 520 p->p_pid, td->td_name, xfpustate_len); 521 return (EINVAL); 522 } 523 xfpustate = __builtin_alloca(xfpustate_len); 524 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate, 525 xfpustate, xfpustate_len); 526 if (error != 0) { 527 uprintf( 528 "pid %d (%s): sigreturn copying xfpustate failed\n", 529 p->p_pid, td->td_name); 530 return (error); 531 } 532 } else { 533 xfpustate = NULL; 534 xfpustate_len = 0; 535 } 536 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len); 537 if (ret != 0) { 538 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 539 p->p_pid, td->td_name, ret); 540 return (ret); 541 } 542 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 543 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 544 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 545 546#if defined(COMPAT_43) 547 if (ucp->uc_mcontext.mc_onstack & 1) 548 td->td_sigstk.ss_flags |= SS_ONSTACK; 549 else 550 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 551#endif 552 553 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 554 set_pcb_flags(pcb, PCB_FULL_IRET); 555 return (EJUSTRETURN); 556} 557 558#ifdef COMPAT_FREEBSD4 559int 560freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 561{ 562 563 return sys_sigreturn(td, (struct sigreturn_args *)uap); 564} 565#endif 566 567 568/* 569 * Machine dependent boot() routine 570 * 571 * I haven't seen anything to put here yet 572 * Possibly some stuff might be grafted back here from boot() 573 */ 574void 575cpu_boot(int howto) 576{ 577} 578 579/* 580 * Flush the D-cache for non-DMA I/O so that the I-cache can 581 * be made coherent later. 582 */ 583void 584cpu_flush_dcache(void *ptr, size_t len) 585{ 586 /* Not applicable */ 587} 588 589/* Get current clock frequency for the given cpu id. */ 590int 591cpu_est_clockrate(int cpu_id, uint64_t *rate) 592{ 593 uint64_t tsc1, tsc2; 594 uint64_t acnt, mcnt, perf; 595 register_t reg; 596 597 if (pcpu_find(cpu_id) == NULL || rate == NULL) 598 return (EINVAL); 599 600 /* 601 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 602 * DELAY(9) based logic fails. 603 */ 604 if (tsc_is_invariant && !tsc_perf_stat) 605 return (EOPNOTSUPP); 606 607#ifdef SMP 608 if (smp_cpus > 1) { 609 /* Schedule ourselves on the indicated cpu. */ 610 thread_lock(curthread); 611 sched_bind(curthread, cpu_id); 612 thread_unlock(curthread); 613 } 614#endif 615 616 /* Calibrate by measuring a short delay. */ 617 reg = intr_disable(); 618 if (tsc_is_invariant) { 619 wrmsr(MSR_MPERF, 0); 620 wrmsr(MSR_APERF, 0); 621 tsc1 = rdtsc(); 622 DELAY(1000); 623 mcnt = rdmsr(MSR_MPERF); 624 acnt = rdmsr(MSR_APERF); 625 tsc2 = rdtsc(); 626 intr_restore(reg); 627 perf = 1000 * acnt / mcnt; 628 *rate = (tsc2 - tsc1) * perf; 629 } else { 630 tsc1 = rdtsc(); 631 DELAY(1000); 632 tsc2 = rdtsc(); 633 intr_restore(reg); 634 *rate = (tsc2 - tsc1) * 1000; 635 } 636 637#ifdef SMP 638 if (smp_cpus > 1) { 639 thread_lock(curthread); 640 sched_unbind(curthread); 641 thread_unlock(curthread); 642 } 643#endif 644 645 return (0); 646} 647 648/* 649 * Shutdown the CPU as much as possible 650 */ 651void 652cpu_halt(void) 653{ 654 for (;;) 655 halt(); 656} 657 658void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 659static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 660static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 661TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 662SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 663 0, "Use MONITOR/MWAIT for short idle"); 664 665#define STATE_RUNNING 0x0 666#define STATE_MWAIT 0x1 667#define STATE_SLEEPING 0x2 668 669static void 670cpu_idle_acpi(sbintime_t sbt) 671{ 672 int *state; 673 674 state = (int *)PCPU_PTR(monitorbuf); 675 *state = STATE_SLEEPING; 676 677 /* See comments in cpu_idle_hlt(). */ 678 disable_intr(); 679 if (sched_runnable()) 680 enable_intr(); 681 else if (cpu_idle_hook) 682 cpu_idle_hook(sbt); 683 else 684 __asm __volatile("sti; hlt"); 685 *state = STATE_RUNNING; 686} 687 688static void 689cpu_idle_hlt(sbintime_t sbt) 690{ 691 int *state; 692 693 state = (int *)PCPU_PTR(monitorbuf); 694 *state = STATE_SLEEPING; 695 696 /* 697 * Since we may be in a critical section from cpu_idle(), if 698 * an interrupt fires during that critical section we may have 699 * a pending preemption. If the CPU halts, then that thread 700 * may not execute until a later interrupt awakens the CPU. 701 * To handle this race, check for a runnable thread after 702 * disabling interrupts and immediately return if one is 703 * found. Also, we must absolutely guarentee that hlt is 704 * the next instruction after sti. This ensures that any 705 * interrupt that fires after the call to disable_intr() will 706 * immediately awaken the CPU from hlt. Finally, please note 707 * that on x86 this works fine because of interrupts enabled only 708 * after the instruction following sti takes place, while IF is set 709 * to 1 immediately, allowing hlt instruction to acknowledge the 710 * interrupt. 711 */ 712 disable_intr(); 713 if (sched_runnable()) 714 enable_intr(); 715 else 716 __asm __volatile("sti; hlt"); 717 *state = STATE_RUNNING; 718} 719 720/* 721 * MWAIT cpu power states. Lower 4 bits are sub-states. 722 */ 723#define MWAIT_C0 0xf0 724#define MWAIT_C1 0x00 725#define MWAIT_C2 0x10 726#define MWAIT_C3 0x20 727#define MWAIT_C4 0x30 728 729static void 730cpu_idle_mwait(sbintime_t sbt) 731{ 732 int *state; 733 734 state = (int *)PCPU_PTR(monitorbuf); 735 *state = STATE_MWAIT; 736 737 /* See comments in cpu_idle_hlt(). */ 738 disable_intr(); 739 if (sched_runnable()) { 740 enable_intr(); 741 *state = STATE_RUNNING; 742 return; 743 } 744 cpu_monitor(state, 0, 0); 745 if (*state == STATE_MWAIT) 746 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 747 else 748 enable_intr(); 749 *state = STATE_RUNNING; 750} 751 752static void 753cpu_idle_spin(sbintime_t sbt) 754{ 755 int *state; 756 int i; 757 758 state = (int *)PCPU_PTR(monitorbuf); 759 *state = STATE_RUNNING; 760 761 /* 762 * The sched_runnable() call is racy but as long as there is 763 * a loop missing it one time will have just a little impact if any 764 * (and it is much better than missing the check at all). 765 */ 766 for (i = 0; i < 1000; i++) { 767 if (sched_runnable()) 768 return; 769 cpu_spinwait(); 770 } 771} 772 773/* 774 * C1E renders the local APIC timer dead, so we disable it by 775 * reading the Interrupt Pending Message register and clearing 776 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 777 * 778 * Reference: 779 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 780 * #32559 revision 3.00+ 781 */ 782#define MSR_AMDK8_IPM 0xc0010055 783#define AMDK8_SMIONCMPHALT (1ULL << 27) 784#define AMDK8_C1EONCMPHALT (1ULL << 28) 785#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 786 787static void 788cpu_probe_amdc1e(void) 789{ 790 791 /* 792 * Detect the presence of C1E capability mostly on latest 793 * dual-cores (or future) k8 family. 794 */ 795 if (cpu_vendor_id == CPU_VENDOR_AMD && 796 (cpu_id & 0x00000f00) == 0x00000f00 && 797 (cpu_id & 0x0fff0000) >= 0x00040000) { 798 cpu_ident_amdc1e = 1; 799 } 800} 801 802void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 803 804void 805cpu_idle(int busy) 806{ 807 uint64_t msr; 808 sbintime_t sbt = -1; 809 810 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 811 busy, curcpu); 812#ifdef MP_WATCHDOG 813 ap_watchdog(PCPU_GET(cpuid)); 814#endif 815 /* If we are busy - try to use fast methods. */ 816 if (busy) { 817 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 818 cpu_idle_mwait(busy); 819 goto out; 820 } 821 } 822 823 /* If we have time - switch timers into idle mode. */ 824 if (!busy) { 825 critical_enter(); 826 sbt = cpu_idleclock(); 827 } 828 829 /* Apply AMD APIC timer C1E workaround. */ 830 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { 831 msr = rdmsr(MSR_AMDK8_IPM); 832 if (msr & AMDK8_CMPHALT) 833 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 834 } 835 836 /* Call main idle method. */ 837 cpu_idle_fn(sbt); 838 839 /* Switch timers mack into active mode. */ 840 if (!busy) { 841 cpu_activeclock(); 842 critical_exit(); 843 } 844out: 845 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 846 busy, curcpu); 847} 848 849int 850cpu_idle_wakeup(int cpu) 851{ 852 struct pcpu *pcpu; 853 int *state; 854 855 pcpu = pcpu_find(cpu); 856 state = (int *)pcpu->pc_monitorbuf; 857 /* 858 * This doesn't need to be atomic since missing the race will 859 * simply result in unnecessary IPIs. 860 */ 861 if (*state == STATE_SLEEPING) 862 return (0); 863 if (*state == STATE_MWAIT) 864 *state = STATE_RUNNING; 865 return (1); 866} 867 868/* 869 * Ordered by speed/power consumption. 870 */ 871struct { 872 void *id_fn; 873 char *id_name; 874} idle_tbl[] = { 875 { cpu_idle_spin, "spin" }, 876 { cpu_idle_mwait, "mwait" }, 877 { cpu_idle_hlt, "hlt" }, 878 { cpu_idle_acpi, "acpi" }, 879 { NULL, NULL } 880}; 881 882static int 883idle_sysctl_available(SYSCTL_HANDLER_ARGS) 884{ 885 char *avail, *p; 886 int error; 887 int i; 888 889 avail = malloc(256, M_TEMP, M_WAITOK); 890 p = avail; 891 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 892 if (strstr(idle_tbl[i].id_name, "mwait") && 893 (cpu_feature2 & CPUID2_MON) == 0) 894 continue; 895 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 896 cpu_idle_hook == NULL) 897 continue; 898 p += sprintf(p, "%s%s", p != avail ? ", " : "", 899 idle_tbl[i].id_name); 900 } 901 error = sysctl_handle_string(oidp, avail, 0, req); 902 free(avail, M_TEMP); 903 return (error); 904} 905 906SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 907 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 908 909static int 910idle_sysctl(SYSCTL_HANDLER_ARGS) 911{ 912 char buf[16]; 913 int error; 914 char *p; 915 int i; 916 917 p = "unknown"; 918 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 919 if (idle_tbl[i].id_fn == cpu_idle_fn) { 920 p = idle_tbl[i].id_name; 921 break; 922 } 923 } 924 strncpy(buf, p, sizeof(buf)); 925 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 926 if (error != 0 || req->newptr == NULL) 927 return (error); 928 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 929 if (strstr(idle_tbl[i].id_name, "mwait") && 930 (cpu_feature2 & CPUID2_MON) == 0) 931 continue; 932 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 933 cpu_idle_hook == NULL) 934 continue; 935 if (strcmp(idle_tbl[i].id_name, buf)) 936 continue; 937 cpu_idle_fn = idle_tbl[i].id_fn; 938 return (0); 939 } 940 return (EINVAL); 941} 942 943SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 944 idle_sysctl, "A", "currently selected idle function"); 945 946/* 947 * Reset registers to default values on exec. 948 */ 949void 950exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 951{ 952 struct trapframe *regs = td->td_frame; 953 struct pcb *pcb = td->td_pcb; 954 955 mtx_lock(&dt_lock); 956 if (td->td_proc->p_md.md_ldt != NULL) 957 user_ldt_free(td); 958 else 959 mtx_unlock(&dt_lock); 960 961 pcb->pcb_fsbase = 0; 962 pcb->pcb_gsbase = 0; 963 clear_pcb_flags(pcb, PCB_32BIT); 964 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 965 set_pcb_flags(pcb, PCB_FULL_IRET); 966 967 bzero((char *)regs, sizeof(struct trapframe)); 968 regs->tf_rip = imgp->entry_addr; 969 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 970 regs->tf_rdi = stack; /* argv */ 971 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 972 regs->tf_ss = _udatasel; 973 regs->tf_cs = _ucodesel; 974 regs->tf_ds = _udatasel; 975 regs->tf_es = _udatasel; 976 regs->tf_fs = _ufssel; 977 regs->tf_gs = _ugssel; 978 regs->tf_flags = TF_HASSEGS; 979 td->td_retval[1] = 0; 980 981 /* 982 * Reset the hardware debug registers if they were in use. 983 * They won't have any meaning for the newly exec'd process. 984 */ 985 if (pcb->pcb_flags & PCB_DBREGS) { 986 pcb->pcb_dr0 = 0; 987 pcb->pcb_dr1 = 0; 988 pcb->pcb_dr2 = 0; 989 pcb->pcb_dr3 = 0; 990 pcb->pcb_dr6 = 0; 991 pcb->pcb_dr7 = 0; 992 if (pcb == curpcb) { 993 /* 994 * Clear the debug registers on the running 995 * CPU, otherwise they will end up affecting 996 * the next process we switch to. 997 */ 998 reset_dbregs(); 999 } 1000 clear_pcb_flags(pcb, PCB_DBREGS); 1001 } 1002 1003 /* 1004 * Drop the FP state if we hold it, so that the process gets a 1005 * clean FP state if it uses the FPU again. 1006 */ 1007 fpstate_drop(td); 1008} 1009 1010void 1011cpu_setregs(void) 1012{ 1013 register_t cr0; 1014 1015 cr0 = rcr0(); 1016 /* 1017 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 1018 * BSP. See the comments there about why we set them. 1019 */ 1020 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 1021 load_cr0(cr0); 1022} 1023 1024/* 1025 * Initialize amd64 and configure to run kernel 1026 */ 1027 1028/* 1029 * Initialize segments & interrupt table 1030 */ 1031 1032struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 1033static struct gate_descriptor idt0[NIDT]; 1034struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 1035 1036static char dblfault_stack[PAGE_SIZE] __aligned(16); 1037 1038static char nmi0_stack[PAGE_SIZE] __aligned(16); 1039CTASSERT(sizeof(struct nmi_pcpu) == 16); 1040 1041struct amd64tss common_tss[MAXCPU]; 1042 1043/* 1044 * Software prototypes -- in more palatable form. 1045 * 1046 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 1047 * slots as corresponding segments for i386 kernel. 1048 */ 1049struct soft_segment_descriptor gdt_segs[] = { 1050/* GNULL_SEL 0 Null Descriptor */ 1051{ .ssd_base = 0x0, 1052 .ssd_limit = 0x0, 1053 .ssd_type = 0, 1054 .ssd_dpl = 0, 1055 .ssd_p = 0, 1056 .ssd_long = 0, 1057 .ssd_def32 = 0, 1058 .ssd_gran = 0 }, 1059/* GNULL2_SEL 1 Null Descriptor */ 1060{ .ssd_base = 0x0, 1061 .ssd_limit = 0x0, 1062 .ssd_type = 0, 1063 .ssd_dpl = 0, 1064 .ssd_p = 0, 1065 .ssd_long = 0, 1066 .ssd_def32 = 0, 1067 .ssd_gran = 0 }, 1068/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 1069{ .ssd_base = 0x0, 1070 .ssd_limit = 0xfffff, 1071 .ssd_type = SDT_MEMRWA, 1072 .ssd_dpl = SEL_UPL, 1073 .ssd_p = 1, 1074 .ssd_long = 0, 1075 .ssd_def32 = 1, 1076 .ssd_gran = 1 }, 1077/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1078{ .ssd_base = 0x0, 1079 .ssd_limit = 0xfffff, 1080 .ssd_type = SDT_MEMRWA, 1081 .ssd_dpl = SEL_UPL, 1082 .ssd_p = 1, 1083 .ssd_long = 0, 1084 .ssd_def32 = 1, 1085 .ssd_gran = 1 }, 1086/* GCODE_SEL 4 Code Descriptor for kernel */ 1087{ .ssd_base = 0x0, 1088 .ssd_limit = 0xfffff, 1089 .ssd_type = SDT_MEMERA, 1090 .ssd_dpl = SEL_KPL, 1091 .ssd_p = 1, 1092 .ssd_long = 1, 1093 .ssd_def32 = 0, 1094 .ssd_gran = 1 }, 1095/* GDATA_SEL 5 Data Descriptor for kernel */ 1096{ .ssd_base = 0x0, 1097 .ssd_limit = 0xfffff, 1098 .ssd_type = SDT_MEMRWA, 1099 .ssd_dpl = SEL_KPL, 1100 .ssd_p = 1, 1101 .ssd_long = 1, 1102 .ssd_def32 = 0, 1103 .ssd_gran = 1 }, 1104/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1105{ .ssd_base = 0x0, 1106 .ssd_limit = 0xfffff, 1107 .ssd_type = SDT_MEMERA, 1108 .ssd_dpl = SEL_UPL, 1109 .ssd_p = 1, 1110 .ssd_long = 0, 1111 .ssd_def32 = 1, 1112 .ssd_gran = 1 }, 1113/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1114{ .ssd_base = 0x0, 1115 .ssd_limit = 0xfffff, 1116 .ssd_type = SDT_MEMRWA, 1117 .ssd_dpl = SEL_UPL, 1118 .ssd_p = 1, 1119 .ssd_long = 0, 1120 .ssd_def32 = 1, 1121 .ssd_gran = 1 }, 1122/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1123{ .ssd_base = 0x0, 1124 .ssd_limit = 0xfffff, 1125 .ssd_type = SDT_MEMERA, 1126 .ssd_dpl = SEL_UPL, 1127 .ssd_p = 1, 1128 .ssd_long = 1, 1129 .ssd_def32 = 0, 1130 .ssd_gran = 1 }, 1131/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1132{ .ssd_base = 0x0, 1133 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1134 .ssd_type = SDT_SYSTSS, 1135 .ssd_dpl = SEL_KPL, 1136 .ssd_p = 1, 1137 .ssd_long = 0, 1138 .ssd_def32 = 0, 1139 .ssd_gran = 0 }, 1140/* Actually, the TSS is a system descriptor which is double size */ 1141{ .ssd_base = 0x0, 1142 .ssd_limit = 0x0, 1143 .ssd_type = 0, 1144 .ssd_dpl = 0, 1145 .ssd_p = 0, 1146 .ssd_long = 0, 1147 .ssd_def32 = 0, 1148 .ssd_gran = 0 }, 1149/* GUSERLDT_SEL 11 LDT Descriptor */ 1150{ .ssd_base = 0x0, 1151 .ssd_limit = 0x0, 1152 .ssd_type = 0, 1153 .ssd_dpl = 0, 1154 .ssd_p = 0, 1155 .ssd_long = 0, 1156 .ssd_def32 = 0, 1157 .ssd_gran = 0 }, 1158/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1159{ .ssd_base = 0x0, 1160 .ssd_limit = 0x0, 1161 .ssd_type = 0, 1162 .ssd_dpl = 0, 1163 .ssd_p = 0, 1164 .ssd_long = 0, 1165 .ssd_def32 = 0, 1166 .ssd_gran = 0 }, 1167}; 1168 1169void 1170setidt(idx, func, typ, dpl, ist) 1171 int idx; 1172 inthand_t *func; 1173 int typ; 1174 int dpl; 1175 int ist; 1176{ 1177 struct gate_descriptor *ip; 1178 1179 ip = idt + idx; 1180 ip->gd_looffset = (uintptr_t)func; 1181 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1182 ip->gd_ist = ist; 1183 ip->gd_xx = 0; 1184 ip->gd_type = typ; 1185 ip->gd_dpl = dpl; 1186 ip->gd_p = 1; 1187 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1188} 1189 1190extern inthand_t 1191 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1192 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1193 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1194 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1195 IDTVEC(xmm), IDTVEC(dblfault), 1196#ifdef KDTRACE_HOOKS 1197 IDTVEC(dtrace_ret), 1198#endif 1199#ifdef XENHVM 1200 IDTVEC(xen_intr_upcall), 1201#endif 1202 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1203 1204#ifdef DDB 1205/* 1206 * Display the index and function name of any IDT entries that don't use 1207 * the default 'rsvd' entry point. 1208 */ 1209DB_SHOW_COMMAND(idt, db_show_idt) 1210{ 1211 struct gate_descriptor *ip; 1212 int idx; 1213 uintptr_t func; 1214 1215 ip = idt; 1216 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1217 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1218 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1219 db_printf("%3d\t", idx); 1220 db_printsym(func, DB_STGY_PROC); 1221 db_printf("\n"); 1222 } 1223 ip++; 1224 } 1225} 1226 1227/* Show privileged registers. */ 1228DB_SHOW_COMMAND(sysregs, db_show_sysregs) 1229{ 1230 struct { 1231 uint16_t limit; 1232 uint64_t base; 1233 } __packed idtr, gdtr; 1234 uint16_t ldt, tr; 1235 1236 __asm __volatile("sidt %0" : "=m" (idtr)); 1237 db_printf("idtr\t0x%016lx/%04x\n", 1238 (u_long)idtr.base, (u_int)idtr.limit); 1239 __asm __volatile("sgdt %0" : "=m" (gdtr)); 1240 db_printf("gdtr\t0x%016lx/%04x\n", 1241 (u_long)gdtr.base, (u_int)gdtr.limit); 1242 __asm __volatile("sldt %0" : "=r" (ldt)); 1243 db_printf("ldtr\t0x%04x\n", ldt); 1244 __asm __volatile("str %0" : "=r" (tr)); 1245 db_printf("tr\t0x%04x\n", tr); 1246 db_printf("cr0\t0x%016lx\n", rcr0()); 1247 db_printf("cr2\t0x%016lx\n", rcr2()); 1248 db_printf("cr3\t0x%016lx\n", rcr3()); 1249 db_printf("cr4\t0x%016lx\n", rcr4()); 1250 db_printf("EFER\t%016lx\n", rdmsr(MSR_EFER)); 1251 db_printf("FEATURES_CTL\t%016lx\n", rdmsr(MSR_IA32_FEATURE_CONTROL)); 1252 db_printf("DEBUG_CTL\t%016lx\n", rdmsr(MSR_DEBUGCTLMSR)); 1253 db_printf("PAT\t%016lx\n", rdmsr(MSR_PAT)); 1254 db_printf("GSBASE\t%016lx\n", rdmsr(MSR_GSBASE)); 1255} 1256#endif 1257 1258void 1259sdtossd(sd, ssd) 1260 struct user_segment_descriptor *sd; 1261 struct soft_segment_descriptor *ssd; 1262{ 1263 1264 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1265 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1266 ssd->ssd_type = sd->sd_type; 1267 ssd->ssd_dpl = sd->sd_dpl; 1268 ssd->ssd_p = sd->sd_p; 1269 ssd->ssd_long = sd->sd_long; 1270 ssd->ssd_def32 = sd->sd_def32; 1271 ssd->ssd_gran = sd->sd_gran; 1272} 1273 1274void 1275ssdtosd(ssd, sd) 1276 struct soft_segment_descriptor *ssd; 1277 struct user_segment_descriptor *sd; 1278{ 1279 1280 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1281 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1282 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1283 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1284 sd->sd_type = ssd->ssd_type; 1285 sd->sd_dpl = ssd->ssd_dpl; 1286 sd->sd_p = ssd->ssd_p; 1287 sd->sd_long = ssd->ssd_long; 1288 sd->sd_def32 = ssd->ssd_def32; 1289 sd->sd_gran = ssd->ssd_gran; 1290} 1291 1292void 1293ssdtosyssd(ssd, sd) 1294 struct soft_segment_descriptor *ssd; 1295 struct system_segment_descriptor *sd; 1296{ 1297 1298 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1299 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1300 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1301 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1302 sd->sd_type = ssd->ssd_type; 1303 sd->sd_dpl = ssd->ssd_dpl; 1304 sd->sd_p = ssd->ssd_p; 1305 sd->sd_gran = ssd->ssd_gran; 1306} 1307 1308#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1309#include <isa/isavar.h> 1310#include <isa/isareg.h> 1311/* 1312 * Return a bitmap of the current interrupt requests. This is 8259-specific 1313 * and is only suitable for use at probe time. 1314 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1315 * It shouldn't be here. There should probably be an APIC centric 1316 * implementation in the apic driver code, if at all. 1317 */ 1318intrmask_t 1319isa_irq_pending(void) 1320{ 1321 u_char irr1; 1322 u_char irr2; 1323 1324 irr1 = inb(IO_ICU1); 1325 irr2 = inb(IO_ICU2); 1326 return ((irr2 << 8) | irr1); 1327} 1328#endif 1329 1330u_int basemem; 1331 1332static int 1333add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp) 1334{ 1335 int i, insert_idx, physmap_idx; 1336 1337 physmap_idx = *physmap_idxp; 1338 1339 if (boothowto & RB_VERBOSE) 1340 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1341 smap->type, smap->base, smap->length); 1342 1343 if (smap->type != SMAP_TYPE_MEMORY) 1344 return (1); 1345 1346 if (smap->length == 0) 1347 return (0); 1348 1349 /* 1350 * Find insertion point while checking for overlap. Start off by 1351 * assuming the new entry will be added to the end. 1352 */ 1353 insert_idx = physmap_idx + 2; 1354 for (i = 0; i <= physmap_idx; i += 2) { 1355 if (smap->base < physmap[i + 1]) { 1356 if (smap->base + smap->length <= physmap[i]) { 1357 insert_idx = i; 1358 break; 1359 } 1360 if (boothowto & RB_VERBOSE) 1361 printf( 1362 "Overlapping memory regions, ignoring second region\n"); 1363 return (1); 1364 } 1365 } 1366 1367 /* See if we can prepend to the next entry. */ 1368 if (insert_idx <= physmap_idx && 1369 smap->base + smap->length == physmap[insert_idx]) { 1370 physmap[insert_idx] = smap->base; 1371 return (1); 1372 } 1373 1374 /* See if we can append to the previous entry. */ 1375 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) { 1376 physmap[insert_idx - 1] += smap->length; 1377 return (1); 1378 } 1379 1380 physmap_idx += 2; 1381 *physmap_idxp = physmap_idx; 1382 if (physmap_idx == PHYSMAP_SIZE) { 1383 printf( 1384 "Too many segments in the physical address map, giving up\n"); 1385 return (0); 1386 } 1387 1388 /* 1389 * Move the last 'N' entries down to make room for the new 1390 * entry if needed. 1391 */ 1392 for (i = physmap_idx; i > insert_idx; i -= 2) { 1393 physmap[i] = physmap[i - 2]; 1394 physmap[i + 1] = physmap[i - 1]; 1395 } 1396 1397 /* Insert the new entry. */ 1398 physmap[insert_idx] = smap->base; 1399 physmap[insert_idx + 1] = smap->base + smap->length; 1400 return (1); 1401} 1402 1403/* 1404 * Populate the (physmap) array with base/bound pairs describing the 1405 * available physical memory in the system, then test this memory and 1406 * build the phys_avail array describing the actually-available memory. 1407 * 1408 * Total memory size may be set by the kernel environment variable 1409 * hw.physmem or the compile-time define MAXMEM. 1410 * 1411 * XXX first should be vm_paddr_t. 1412 */ 1413static void 1414getmemsize(caddr_t kmdp, u_int64_t first) 1415{ 1416 int i, physmap_idx, pa_indx, da_indx; 1417 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1418 u_long physmem_start, physmem_tunable, memtest; 1419 pt_entry_t *pte; 1420 struct bios_smap *smapbase, *smap, *smapend; 1421 u_int32_t smapsize; 1422 quad_t dcons_addr, dcons_size; 1423 1424 bzero(physmap, sizeof(physmap)); 1425 basemem = 0; 1426 physmap_idx = 0; 1427 1428 /* 1429 * get memory map from INT 15:E820, kindly supplied by the loader. 1430 * 1431 * subr_module.c says: 1432 * "Consumer may safely assume that size value precedes data." 1433 * ie: an int32_t immediately precedes smap. 1434 */ 1435 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1436 MODINFO_METADATA | MODINFOMD_SMAP); 1437 if (smapbase == NULL) 1438 panic("No BIOS smap info from loader!"); 1439 1440 smapsize = *((u_int32_t *)smapbase - 1); 1441 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1442 1443 for (smap = smapbase; smap < smapend; smap++) 1444 if (!add_smap_entry(smap, physmap, &physmap_idx)) 1445 break; 1446 1447 /* 1448 * Find the 'base memory' segment for SMP 1449 */ 1450 basemem = 0; 1451 for (i = 0; i <= physmap_idx; i += 2) { 1452 if (physmap[i] == 0x00000000) { 1453 basemem = physmap[i + 1] / 1024; 1454 break; 1455 } 1456 } 1457 if (basemem == 0) 1458 panic("BIOS smap did not include a basemem segment!"); 1459 1460#ifdef SMP 1461 /* make hole for AP bootstrap code */ 1462 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1463#endif 1464 1465 /* 1466 * Maxmem isn't the "maximum memory", it's one larger than the 1467 * highest page of the physical address space. It should be 1468 * called something like "Maxphyspage". We may adjust this 1469 * based on ``hw.physmem'' and the results of the memory test. 1470 */ 1471 Maxmem = atop(physmap[physmap_idx + 1]); 1472 1473#ifdef MAXMEM 1474 Maxmem = MAXMEM / 4; 1475#endif 1476 1477 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1478 Maxmem = atop(physmem_tunable); 1479 1480 /* 1481 * By default enable the memory test on real hardware, and disable 1482 * it if we appear to be running in a VM. This avoids touching all 1483 * pages unnecessarily, which doesn't matter on real hardware but is 1484 * bad for shared VM hosts. Use a general name so that 1485 * one could eventually do more with the code than just disable it. 1486 */ 1487 memtest = (vm_guest > VM_GUEST_NO) ? 0 : 1; 1488 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1489 1490 /* 1491 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1492 * in the system. 1493 */ 1494 if (Maxmem > atop(physmap[physmap_idx + 1])) 1495 Maxmem = atop(physmap[physmap_idx + 1]); 1496 1497 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1498 (boothowto & RB_VERBOSE)) 1499 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1500 1501 /* call pmap initialization to make new kernel address space */ 1502 pmap_bootstrap(&first); 1503 1504 /* 1505 * Size up each available chunk of physical memory. 1506 * 1507 * XXX Some BIOSes corrupt low 64KB between suspend and resume. 1508 * By default, mask off the first 16 pages unless we appear to be 1509 * running in a VM. 1510 */ 1511 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT; 1512 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start); 1513 if (physmem_start < PAGE_SIZE) 1514 physmap[0] = PAGE_SIZE; 1515 else if (physmem_start >= physmap[1]) 1516 physmap[0] = round_page(physmap[1] - PAGE_SIZE); 1517 else 1518 physmap[0] = round_page(physmem_start); 1519 pa_indx = 0; 1520 da_indx = 1; 1521 phys_avail[pa_indx++] = physmap[0]; 1522 phys_avail[pa_indx] = physmap[0]; 1523 dump_avail[da_indx] = physmap[0]; 1524 pte = CMAP1; 1525 1526 /* 1527 * Get dcons buffer address 1528 */ 1529 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1530 getenv_quad("dcons.size", &dcons_size) == 0) 1531 dcons_addr = 0; 1532 1533 /* 1534 * physmap is in bytes, so when converting to page boundaries, 1535 * round up the start address and round down the end address. 1536 */ 1537 for (i = 0; i <= physmap_idx; i += 2) { 1538 vm_paddr_t end; 1539 1540 end = ptoa((vm_paddr_t)Maxmem); 1541 if (physmap[i + 1] < end) 1542 end = trunc_page(physmap[i + 1]); 1543 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1544 int tmp, page_bad, full; 1545 int *ptr = (int *)CADDR1; 1546 1547 full = FALSE; 1548 /* 1549 * block out kernel memory as not available. 1550 */ 1551 if (pa >= (vm_paddr_t)kernphys && pa < first) 1552 goto do_dump_avail; 1553 1554 /* 1555 * block out dcons buffer 1556 */ 1557 if (dcons_addr > 0 1558 && pa >= trunc_page(dcons_addr) 1559 && pa < dcons_addr + dcons_size) 1560 goto do_dump_avail; 1561 1562 page_bad = FALSE; 1563 if (memtest == 0) 1564 goto skip_memtest; 1565 1566 /* 1567 * map page into kernel: valid, read/write,non-cacheable 1568 */ 1569 *pte = pa | PG_V | PG_RW | PG_NC_PWT | PG_NC_PCD; 1570 invltlb(); 1571 1572 tmp = *(int *)ptr; 1573 /* 1574 * Test for alternating 1's and 0's 1575 */ 1576 *(volatile int *)ptr = 0xaaaaaaaa; 1577 if (*(volatile int *)ptr != 0xaaaaaaaa) 1578 page_bad = TRUE; 1579 /* 1580 * Test for alternating 0's and 1's 1581 */ 1582 *(volatile int *)ptr = 0x55555555; 1583 if (*(volatile int *)ptr != 0x55555555) 1584 page_bad = TRUE; 1585 /* 1586 * Test for all 1's 1587 */ 1588 *(volatile int *)ptr = 0xffffffff; 1589 if (*(volatile int *)ptr != 0xffffffff) 1590 page_bad = TRUE; 1591 /* 1592 * Test for all 0's 1593 */ 1594 *(volatile int *)ptr = 0x0; 1595 if (*(volatile int *)ptr != 0x0) 1596 page_bad = TRUE; 1597 /* 1598 * Restore original value. 1599 */ 1600 *(int *)ptr = tmp; 1601 1602skip_memtest: 1603 /* 1604 * Adjust array of valid/good pages. 1605 */ 1606 if (page_bad == TRUE) 1607 continue; 1608 /* 1609 * If this good page is a continuation of the 1610 * previous set of good pages, then just increase 1611 * the end pointer. Otherwise start a new chunk. 1612 * Note that "end" points one higher than end, 1613 * making the range >= start and < end. 1614 * If we're also doing a speculative memory 1615 * test and we at or past the end, bump up Maxmem 1616 * so that we keep going. The first bad page 1617 * will terminate the loop. 1618 */ 1619 if (phys_avail[pa_indx] == pa) { 1620 phys_avail[pa_indx] += PAGE_SIZE; 1621 } else { 1622 pa_indx++; 1623 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1624 printf( 1625 "Too many holes in the physical address space, giving up\n"); 1626 pa_indx--; 1627 full = TRUE; 1628 goto do_dump_avail; 1629 } 1630 phys_avail[pa_indx++] = pa; /* start */ 1631 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1632 } 1633 physmem++; 1634do_dump_avail: 1635 if (dump_avail[da_indx] == pa) { 1636 dump_avail[da_indx] += PAGE_SIZE; 1637 } else { 1638 da_indx++; 1639 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1640 da_indx--; 1641 goto do_next; 1642 } 1643 dump_avail[da_indx++] = pa; /* start */ 1644 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1645 } 1646do_next: 1647 if (full) 1648 break; 1649 } 1650 } 1651 *pte = 0; 1652 invltlb(); 1653 1654 /* 1655 * XXX 1656 * The last chunk must contain at least one page plus the message 1657 * buffer to avoid complicating other code (message buffer address 1658 * calculation, etc.). 1659 */ 1660 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1661 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1662 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1663 phys_avail[pa_indx--] = 0; 1664 phys_avail[pa_indx--] = 0; 1665 } 1666 1667 Maxmem = atop(phys_avail[pa_indx]); 1668 1669 /* Trim off space for the message buffer. */ 1670 phys_avail[pa_indx] -= round_page(msgbufsize); 1671 1672 /* Map the message buffer. */ 1673 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1674} 1675 1676u_int64_t 1677hammer_time(u_int64_t modulep, u_int64_t physfree) 1678{ 1679 caddr_t kmdp; 1680 int gsel_tss, x; 1681 struct pcpu *pc; 1682 struct nmi_pcpu *np; 1683 struct xstate_hdr *xhdr; 1684 u_int64_t msr; 1685 char *env; 1686 size_t kstack0_sz; 1687 1688 thread0.td_kstack = physfree + KERNBASE; 1689 thread0.td_kstack_pages = KSTACK_PAGES; 1690 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1691 bzero((void *)thread0.td_kstack, kstack0_sz); 1692 physfree += kstack0_sz; 1693 1694 /* 1695 * This may be done better later if it gets more high level 1696 * components in it. If so just link td->td_proc here. 1697 */ 1698 proc_linkup0(&proc0, &thread0); 1699 1700 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1701 preload_bootstrap_relocate(KERNBASE); 1702 kmdp = preload_search_by_type("elf kernel"); 1703 if (kmdp == NULL) 1704 kmdp = preload_search_by_type("elf64 kernel"); 1705 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1706 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1707#ifdef DDB 1708 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1709 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1710#endif 1711 1712 /* Init basic tunables, hz etc */ 1713 init_param1(); 1714 1715 /* 1716 * make gdt memory segments 1717 */ 1718 for (x = 0; x < NGDT; x++) { 1719 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1720 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1721 ssdtosd(&gdt_segs[x], &gdt[x]); 1722 } 1723 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1724 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1725 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1726 1727 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1728 r_gdt.rd_base = (long) gdt; 1729 lgdt(&r_gdt); 1730 pc = &__pcpu[0]; 1731 1732 wrmsr(MSR_FSBASE, 0); /* User value */ 1733 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1734 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1735 1736 pcpu_init(pc, 0, sizeof(struct pcpu)); 1737 dpcpu_init((void *)(physfree + KERNBASE), 0); 1738 physfree += DPCPU_SIZE; 1739 PCPU_SET(prvspace, pc); 1740 PCPU_SET(curthread, &thread0); 1741 PCPU_SET(tssp, &common_tss[0]); 1742 PCPU_SET(commontssp, &common_tss[0]); 1743 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1744 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1745 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1746 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1747 1748 /* 1749 * Initialize mutexes. 1750 * 1751 * icu_lock: in order to allow an interrupt to occur in a critical 1752 * section, to set pcpu->ipending (etc...) properly, we 1753 * must be able to get the icu lock, so it can't be 1754 * under witness. 1755 */ 1756 mutex_init(); 1757 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1758 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1759 1760 /* exceptions */ 1761 for (x = 0; x < NIDT; x++) 1762 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1763 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1764 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1765 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1766 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1767 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1768 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1769 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1770 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1771 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1772 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1773 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1774 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1775 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1776 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1777 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1778 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1779 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1780 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1781 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1782#ifdef KDTRACE_HOOKS 1783 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1784#endif 1785#ifdef XENHVM 1786 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall), SDT_SYSIGT, SEL_UPL, 0); 1787#endif 1788 1789 r_idt.rd_limit = sizeof(idt0) - 1; 1790 r_idt.rd_base = (long) idt; 1791 lidt(&r_idt); 1792 1793 /* 1794 * Initialize the i8254 before the console so that console 1795 * initialization can use DELAY(). 1796 */ 1797 i8254_init(); 1798 1799 /* 1800 * Initialize the console before we print anything out. 1801 */ 1802 cninit(); 1803 1804#ifdef DEV_ISA 1805#ifdef DEV_ATPIC 1806 elcr_probe(); 1807 atpic_startup(); 1808#else 1809 /* Reset and mask the atpics and leave them shut down. */ 1810 atpic_reset(); 1811 1812 /* 1813 * Point the ICU spurious interrupt vectors at the APIC spurious 1814 * interrupt handler. 1815 */ 1816 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1817 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1818#endif 1819#else 1820#error "have you forgotten the isa device?"; 1821#endif 1822 1823 kdb_init(); 1824 1825#ifdef KDB 1826 if (boothowto & RB_KDB) 1827 kdb_enter(KDB_WHY_BOOTFLAGS, 1828 "Boot flags requested debugger"); 1829#endif 1830 1831 identify_cpu(); /* Final stage of CPU initialization */ 1832 initializecpu(); /* Initialize CPU registers */ 1833 initializecpucache(); 1834 1835 /* doublefault stack space, runs on ist1 */ 1836 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1837 1838 /* 1839 * NMI stack, runs on ist2. The pcpu pointer is stored just 1840 * above the start of the ist2 stack. 1841 */ 1842 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1843 np->np_pcpu = (register_t) pc; 1844 common_tss[0].tss_ist2 = (long) np; 1845 1846 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1847 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1848 IOPAGES * PAGE_SIZE; 1849 1850 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1851 ltr(gsel_tss); 1852 1853 /* Set up the fast syscall stuff */ 1854 msr = rdmsr(MSR_EFER) | EFER_SCE; 1855 wrmsr(MSR_EFER, msr); 1856 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1857 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1858 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1859 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1860 wrmsr(MSR_STAR, msr); 1861 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1862 1863 getmemsize(kmdp, physfree); 1864 init_param2(physmem); 1865 1866 /* now running on new page tables, configured,and u/iom is accessible */ 1867 1868 msgbufinit(msgbufp, msgbufsize); 1869 fpuinit(); 1870 1871 /* 1872 * Set up thread0 pcb after fpuinit calculated pcb + fpu save 1873 * area size. Zero out the extended state header in fpu save 1874 * area. 1875 */ 1876 thread0.td_pcb = get_pcb_td(&thread0); 1877 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size); 1878 if (use_xsave) { 1879 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) + 1880 1); 1881 xhdr->xstate_bv = xsave_mask; 1882 } 1883 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1884 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb; 1885 /* Ensure the stack is aligned to 16 bytes */ 1886 common_tss[0].tss_rsp0 &= ~0xFul; 1887 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1888 PCPU_SET(curpcb, thread0.td_pcb); 1889 1890 /* transfer to user mode */ 1891 1892 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1893 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1894 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1895 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1896 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1897 1898 load_ds(_udatasel); 1899 load_es(_udatasel); 1900 load_fs(_ufssel); 1901 1902 /* setup proc 0's pcb */ 1903 thread0.td_pcb->pcb_flags = 0; 1904 thread0.td_pcb->pcb_cr3 = KPML4phys; /* PCID 0 is reserved for kernel */ 1905 thread0.td_frame = &proc0_tf; 1906 1907 env = getenv("kernelname"); 1908 if (env != NULL) 1909 strlcpy(kernelname, env, sizeof(kernelname)); 1910 1911 cpu_probe_amdc1e(); 1912 1913#ifdef FDT 1914 x86_init_fdt(); 1915#endif 1916 1917 /* Location of kernel stack for locore */ 1918 return ((u_int64_t)thread0.td_pcb); 1919} 1920 1921void 1922cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1923{ 1924 1925 pcpu->pc_acpi_id = 0xffffffff; 1926} 1927 1928void 1929spinlock_enter(void) 1930{ 1931 struct thread *td; 1932 register_t flags; 1933 1934 td = curthread; 1935 if (td->td_md.md_spinlock_count == 0) { 1936 flags = intr_disable(); 1937 td->td_md.md_spinlock_count = 1; 1938 td->td_md.md_saved_flags = flags; 1939 } else 1940 td->td_md.md_spinlock_count++; 1941 critical_enter(); 1942} 1943 1944void 1945spinlock_exit(void) 1946{ 1947 struct thread *td; 1948 register_t flags; 1949 1950 td = curthread; 1951 critical_exit(); 1952 flags = td->td_md.md_saved_flags; 1953 td->td_md.md_spinlock_count--; 1954 if (td->td_md.md_spinlock_count == 0) 1955 intr_restore(flags); 1956} 1957 1958/* 1959 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1960 * we want to start a backtrace from the function that caused us to enter 1961 * the debugger. We have the context in the trapframe, but base the trace 1962 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1963 * enough for a backtrace. 1964 */ 1965void 1966makectx(struct trapframe *tf, struct pcb *pcb) 1967{ 1968 1969 pcb->pcb_r12 = tf->tf_r12; 1970 pcb->pcb_r13 = tf->tf_r13; 1971 pcb->pcb_r14 = tf->tf_r14; 1972 pcb->pcb_r15 = tf->tf_r15; 1973 pcb->pcb_rbp = tf->tf_rbp; 1974 pcb->pcb_rbx = tf->tf_rbx; 1975 pcb->pcb_rip = tf->tf_rip; 1976 pcb->pcb_rsp = tf->tf_rsp; 1977} 1978 1979int 1980ptrace_set_pc(struct thread *td, unsigned long addr) 1981{ 1982 td->td_frame->tf_rip = addr; 1983 return (0); 1984} 1985 1986int 1987ptrace_single_step(struct thread *td) 1988{ 1989 td->td_frame->tf_rflags |= PSL_T; 1990 return (0); 1991} 1992 1993int 1994ptrace_clear_single_step(struct thread *td) 1995{ 1996 td->td_frame->tf_rflags &= ~PSL_T; 1997 return (0); 1998} 1999 2000int 2001fill_regs(struct thread *td, struct reg *regs) 2002{ 2003 struct trapframe *tp; 2004 2005 tp = td->td_frame; 2006 return (fill_frame_regs(tp, regs)); 2007} 2008 2009int 2010fill_frame_regs(struct trapframe *tp, struct reg *regs) 2011{ 2012 regs->r_r15 = tp->tf_r15; 2013 regs->r_r14 = tp->tf_r14; 2014 regs->r_r13 = tp->tf_r13; 2015 regs->r_r12 = tp->tf_r12; 2016 regs->r_r11 = tp->tf_r11; 2017 regs->r_r10 = tp->tf_r10; 2018 regs->r_r9 = tp->tf_r9; 2019 regs->r_r8 = tp->tf_r8; 2020 regs->r_rdi = tp->tf_rdi; 2021 regs->r_rsi = tp->tf_rsi; 2022 regs->r_rbp = tp->tf_rbp; 2023 regs->r_rbx = tp->tf_rbx; 2024 regs->r_rdx = tp->tf_rdx; 2025 regs->r_rcx = tp->tf_rcx; 2026 regs->r_rax = tp->tf_rax; 2027 regs->r_rip = tp->tf_rip; 2028 regs->r_cs = tp->tf_cs; 2029 regs->r_rflags = tp->tf_rflags; 2030 regs->r_rsp = tp->tf_rsp; 2031 regs->r_ss = tp->tf_ss; 2032 if (tp->tf_flags & TF_HASSEGS) { 2033 regs->r_ds = tp->tf_ds; 2034 regs->r_es = tp->tf_es; 2035 regs->r_fs = tp->tf_fs; 2036 regs->r_gs = tp->tf_gs; 2037 } else { 2038 regs->r_ds = 0; 2039 regs->r_es = 0; 2040 regs->r_fs = 0; 2041 regs->r_gs = 0; 2042 } 2043 return (0); 2044} 2045 2046int 2047set_regs(struct thread *td, struct reg *regs) 2048{ 2049 struct trapframe *tp; 2050 register_t rflags; 2051 2052 tp = td->td_frame; 2053 rflags = regs->r_rflags & 0xffffffff; 2054 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 2055 return (EINVAL); 2056 tp->tf_r15 = regs->r_r15; 2057 tp->tf_r14 = regs->r_r14; 2058 tp->tf_r13 = regs->r_r13; 2059 tp->tf_r12 = regs->r_r12; 2060 tp->tf_r11 = regs->r_r11; 2061 tp->tf_r10 = regs->r_r10; 2062 tp->tf_r9 = regs->r_r9; 2063 tp->tf_r8 = regs->r_r8; 2064 tp->tf_rdi = regs->r_rdi; 2065 tp->tf_rsi = regs->r_rsi; 2066 tp->tf_rbp = regs->r_rbp; 2067 tp->tf_rbx = regs->r_rbx; 2068 tp->tf_rdx = regs->r_rdx; 2069 tp->tf_rcx = regs->r_rcx; 2070 tp->tf_rax = regs->r_rax; 2071 tp->tf_rip = regs->r_rip; 2072 tp->tf_cs = regs->r_cs; 2073 tp->tf_rflags = rflags; 2074 tp->tf_rsp = regs->r_rsp; 2075 tp->tf_ss = regs->r_ss; 2076 if (0) { /* XXXKIB */ 2077 tp->tf_ds = regs->r_ds; 2078 tp->tf_es = regs->r_es; 2079 tp->tf_fs = regs->r_fs; 2080 tp->tf_gs = regs->r_gs; 2081 tp->tf_flags = TF_HASSEGS; 2082 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2083 } 2084 return (0); 2085} 2086 2087/* XXX check all this stuff! */ 2088/* externalize from sv_xmm */ 2089static void 2090fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 2091{ 2092 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2093 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2094 int i; 2095 2096 /* pcb -> fpregs */ 2097 bzero(fpregs, sizeof(*fpregs)); 2098 2099 /* FPU control/status */ 2100 penv_fpreg->en_cw = penv_xmm->en_cw; 2101 penv_fpreg->en_sw = penv_xmm->en_sw; 2102 penv_fpreg->en_tw = penv_xmm->en_tw; 2103 penv_fpreg->en_opcode = penv_xmm->en_opcode; 2104 penv_fpreg->en_rip = penv_xmm->en_rip; 2105 penv_fpreg->en_rdp = penv_xmm->en_rdp; 2106 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 2107 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 2108 2109 /* FPU registers */ 2110 for (i = 0; i < 8; ++i) 2111 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 2112 2113 /* SSE registers */ 2114 for (i = 0; i < 16; ++i) 2115 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 2116} 2117 2118/* internalize from fpregs into sv_xmm */ 2119static void 2120set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 2121{ 2122 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2123 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2124 int i; 2125 2126 /* fpregs -> pcb */ 2127 /* FPU control/status */ 2128 penv_xmm->en_cw = penv_fpreg->en_cw; 2129 penv_xmm->en_sw = penv_fpreg->en_sw; 2130 penv_xmm->en_tw = penv_fpreg->en_tw; 2131 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2132 penv_xmm->en_rip = penv_fpreg->en_rip; 2133 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2134 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2135 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2136 2137 /* FPU registers */ 2138 for (i = 0; i < 8; ++i) 2139 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2140 2141 /* SSE registers */ 2142 for (i = 0; i < 16; ++i) 2143 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2144} 2145 2146/* externalize from td->pcb */ 2147int 2148fill_fpregs(struct thread *td, struct fpreg *fpregs) 2149{ 2150 2151 KASSERT(td == curthread || TD_IS_SUSPENDED(td) || 2152 P_SHOULDSTOP(td->td_proc), 2153 ("not suspended thread %p", td)); 2154 fpugetregs(td); 2155 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs); 2156 return (0); 2157} 2158 2159/* internalize to td->pcb */ 2160int 2161set_fpregs(struct thread *td, struct fpreg *fpregs) 2162{ 2163 2164 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td)); 2165 fpuuserinited(td); 2166 return (0); 2167} 2168 2169/* 2170 * Get machine context. 2171 */ 2172int 2173get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2174{ 2175 struct pcb *pcb; 2176 struct trapframe *tp; 2177 2178 pcb = td->td_pcb; 2179 tp = td->td_frame; 2180 PROC_LOCK(curthread->td_proc); 2181 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2182 PROC_UNLOCK(curthread->td_proc); 2183 mcp->mc_r15 = tp->tf_r15; 2184 mcp->mc_r14 = tp->tf_r14; 2185 mcp->mc_r13 = tp->tf_r13; 2186 mcp->mc_r12 = tp->tf_r12; 2187 mcp->mc_r11 = tp->tf_r11; 2188 mcp->mc_r10 = tp->tf_r10; 2189 mcp->mc_r9 = tp->tf_r9; 2190 mcp->mc_r8 = tp->tf_r8; 2191 mcp->mc_rdi = tp->tf_rdi; 2192 mcp->mc_rsi = tp->tf_rsi; 2193 mcp->mc_rbp = tp->tf_rbp; 2194 mcp->mc_rbx = tp->tf_rbx; 2195 mcp->mc_rcx = tp->tf_rcx; 2196 mcp->mc_rflags = tp->tf_rflags; 2197 if (flags & GET_MC_CLEAR_RET) { 2198 mcp->mc_rax = 0; 2199 mcp->mc_rdx = 0; 2200 mcp->mc_rflags &= ~PSL_C; 2201 } else { 2202 mcp->mc_rax = tp->tf_rax; 2203 mcp->mc_rdx = tp->tf_rdx; 2204 } 2205 mcp->mc_rip = tp->tf_rip; 2206 mcp->mc_cs = tp->tf_cs; 2207 mcp->mc_rsp = tp->tf_rsp; 2208 mcp->mc_ss = tp->tf_ss; 2209 mcp->mc_ds = tp->tf_ds; 2210 mcp->mc_es = tp->tf_es; 2211 mcp->mc_fs = tp->tf_fs; 2212 mcp->mc_gs = tp->tf_gs; 2213 mcp->mc_flags = tp->tf_flags; 2214 mcp->mc_len = sizeof(*mcp); 2215 get_fpcontext(td, mcp, NULL, 0); 2216 mcp->mc_fsbase = pcb->pcb_fsbase; 2217 mcp->mc_gsbase = pcb->pcb_gsbase; 2218 mcp->mc_xfpustate = 0; 2219 mcp->mc_xfpustate_len = 0; 2220 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2221 return (0); 2222} 2223 2224/* 2225 * Set machine context. 2226 * 2227 * However, we don't set any but the user modifiable flags, and we won't 2228 * touch the cs selector. 2229 */ 2230int 2231set_mcontext(struct thread *td, const mcontext_t *mcp) 2232{ 2233 struct pcb *pcb; 2234 struct trapframe *tp; 2235 char *xfpustate; 2236 long rflags; 2237 int ret; 2238 2239 pcb = td->td_pcb; 2240 tp = td->td_frame; 2241 if (mcp->mc_len != sizeof(*mcp) || 2242 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2243 return (EINVAL); 2244 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2245 (tp->tf_rflags & ~PSL_USERCHANGE); 2246 if (mcp->mc_flags & _MC_HASFPXSTATE) { 2247 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size - 2248 sizeof(struct savefpu)) 2249 return (EINVAL); 2250 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len); 2251 ret = copyin((void *)mcp->mc_xfpustate, xfpustate, 2252 mcp->mc_xfpustate_len); 2253 if (ret != 0) 2254 return (ret); 2255 } else 2256 xfpustate = NULL; 2257 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len); 2258 if (ret != 0) 2259 return (ret); 2260 tp->tf_r15 = mcp->mc_r15; 2261 tp->tf_r14 = mcp->mc_r14; 2262 tp->tf_r13 = mcp->mc_r13; 2263 tp->tf_r12 = mcp->mc_r12; 2264 tp->tf_r11 = mcp->mc_r11; 2265 tp->tf_r10 = mcp->mc_r10; 2266 tp->tf_r9 = mcp->mc_r9; 2267 tp->tf_r8 = mcp->mc_r8; 2268 tp->tf_rdi = mcp->mc_rdi; 2269 tp->tf_rsi = mcp->mc_rsi; 2270 tp->tf_rbp = mcp->mc_rbp; 2271 tp->tf_rbx = mcp->mc_rbx; 2272 tp->tf_rdx = mcp->mc_rdx; 2273 tp->tf_rcx = mcp->mc_rcx; 2274 tp->tf_rax = mcp->mc_rax; 2275 tp->tf_rip = mcp->mc_rip; 2276 tp->tf_rflags = rflags; 2277 tp->tf_rsp = mcp->mc_rsp; 2278 tp->tf_ss = mcp->mc_ss; 2279 tp->tf_flags = mcp->mc_flags; 2280 if (tp->tf_flags & TF_HASSEGS) { 2281 tp->tf_ds = mcp->mc_ds; 2282 tp->tf_es = mcp->mc_es; 2283 tp->tf_fs = mcp->mc_fs; 2284 tp->tf_gs = mcp->mc_gs; 2285 } 2286 if (mcp->mc_flags & _MC_HASBASES) { 2287 pcb->pcb_fsbase = mcp->mc_fsbase; 2288 pcb->pcb_gsbase = mcp->mc_gsbase; 2289 } 2290 set_pcb_flags(pcb, PCB_FULL_IRET); 2291 return (0); 2292} 2293 2294static void 2295get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave, 2296 size_t xfpusave_len) 2297{ 2298 size_t max_len, len; 2299 2300 mcp->mc_ownedfp = fpugetregs(td); 2301 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0], 2302 sizeof(mcp->mc_fpstate)); 2303 mcp->mc_fpformat = fpuformat(); 2304 if (!use_xsave || xfpusave_len == 0) 2305 return; 2306 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 2307 len = xfpusave_len; 2308 if (len > max_len) { 2309 len = max_len; 2310 bzero(xfpusave + max_len, len - max_len); 2311 } 2312 mcp->mc_flags |= _MC_HASFPXSTATE; 2313 mcp->mc_xfpustate_len = len; 2314 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len); 2315} 2316 2317static int 2318set_fpcontext(struct thread *td, const mcontext_t *mcp, char *xfpustate, 2319 size_t xfpustate_len) 2320{ 2321 struct savefpu *fpstate; 2322 int error; 2323 2324 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2325 return (0); 2326 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2327 return (EINVAL); 2328 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) { 2329 /* We don't care what state is left in the FPU or PCB. */ 2330 fpstate_drop(td); 2331 error = 0; 2332 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2333 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2334 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2335 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2336 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len); 2337 } else 2338 return (EINVAL); 2339 return (error); 2340} 2341 2342void 2343fpstate_drop(struct thread *td) 2344{ 2345 2346 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2347 critical_enter(); 2348 if (PCPU_GET(fpcurthread) == td) 2349 fpudrop(); 2350 /* 2351 * XXX force a full drop of the fpu. The above only drops it if we 2352 * owned it. 2353 * 2354 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2355 * drop. Dropping only to the pcb matches fnsave's behaviour. 2356 * We only need to drop to !PCB_INITDONE in sendsig(). But 2357 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2358 * have too many layers. 2359 */ 2360 clear_pcb_flags(curthread->td_pcb, 2361 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2362 critical_exit(); 2363} 2364 2365int 2366fill_dbregs(struct thread *td, struct dbreg *dbregs) 2367{ 2368 struct pcb *pcb; 2369 2370 if (td == NULL) { 2371 dbregs->dr[0] = rdr0(); 2372 dbregs->dr[1] = rdr1(); 2373 dbregs->dr[2] = rdr2(); 2374 dbregs->dr[3] = rdr3(); 2375 dbregs->dr[6] = rdr6(); 2376 dbregs->dr[7] = rdr7(); 2377 } else { 2378 pcb = td->td_pcb; 2379 dbregs->dr[0] = pcb->pcb_dr0; 2380 dbregs->dr[1] = pcb->pcb_dr1; 2381 dbregs->dr[2] = pcb->pcb_dr2; 2382 dbregs->dr[3] = pcb->pcb_dr3; 2383 dbregs->dr[6] = pcb->pcb_dr6; 2384 dbregs->dr[7] = pcb->pcb_dr7; 2385 } 2386 dbregs->dr[4] = 0; 2387 dbregs->dr[5] = 0; 2388 dbregs->dr[8] = 0; 2389 dbregs->dr[9] = 0; 2390 dbregs->dr[10] = 0; 2391 dbregs->dr[11] = 0; 2392 dbregs->dr[12] = 0; 2393 dbregs->dr[13] = 0; 2394 dbregs->dr[14] = 0; 2395 dbregs->dr[15] = 0; 2396 return (0); 2397} 2398 2399int 2400set_dbregs(struct thread *td, struct dbreg *dbregs) 2401{ 2402 struct pcb *pcb; 2403 int i; 2404 2405 if (td == NULL) { 2406 load_dr0(dbregs->dr[0]); 2407 load_dr1(dbregs->dr[1]); 2408 load_dr2(dbregs->dr[2]); 2409 load_dr3(dbregs->dr[3]); 2410 load_dr6(dbregs->dr[6]); 2411 load_dr7(dbregs->dr[7]); 2412 } else { 2413 /* 2414 * Don't let an illegal value for dr7 get set. Specifically, 2415 * check for undefined settings. Setting these bit patterns 2416 * result in undefined behaviour and can lead to an unexpected 2417 * TRCTRAP or a general protection fault right here. 2418 * Upper bits of dr6 and dr7 must not be set 2419 */ 2420 for (i = 0; i < 4; i++) { 2421 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2422 return (EINVAL); 2423 if (td->td_frame->tf_cs == _ucode32sel && 2424 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2425 return (EINVAL); 2426 } 2427 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2428 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2429 return (EINVAL); 2430 2431 pcb = td->td_pcb; 2432 2433 /* 2434 * Don't let a process set a breakpoint that is not within the 2435 * process's address space. If a process could do this, it 2436 * could halt the system by setting a breakpoint in the kernel 2437 * (if ddb was enabled). Thus, we need to check to make sure 2438 * that no breakpoints are being enabled for addresses outside 2439 * process's address space. 2440 * 2441 * XXX - what about when the watched area of the user's 2442 * address space is written into from within the kernel 2443 * ... wouldn't that still cause a breakpoint to be generated 2444 * from within kernel mode? 2445 */ 2446 2447 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2448 /* dr0 is enabled */ 2449 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2450 return (EINVAL); 2451 } 2452 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2453 /* dr1 is enabled */ 2454 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2455 return (EINVAL); 2456 } 2457 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2458 /* dr2 is enabled */ 2459 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2460 return (EINVAL); 2461 } 2462 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2463 /* dr3 is enabled */ 2464 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2465 return (EINVAL); 2466 } 2467 2468 pcb->pcb_dr0 = dbregs->dr[0]; 2469 pcb->pcb_dr1 = dbregs->dr[1]; 2470 pcb->pcb_dr2 = dbregs->dr[2]; 2471 pcb->pcb_dr3 = dbregs->dr[3]; 2472 pcb->pcb_dr6 = dbregs->dr[6]; 2473 pcb->pcb_dr7 = dbregs->dr[7]; 2474 2475 set_pcb_flags(pcb, PCB_DBREGS); 2476 } 2477 2478 return (0); 2479} 2480 2481void 2482reset_dbregs(void) 2483{ 2484 2485 load_dr7(0); /* Turn off the control bits first */ 2486 load_dr0(0); 2487 load_dr1(0); 2488 load_dr2(0); 2489 load_dr3(0); 2490 load_dr6(0); 2491} 2492 2493/* 2494 * Return > 0 if a hardware breakpoint has been hit, and the 2495 * breakpoint was in user space. Return 0, otherwise. 2496 */ 2497int 2498user_dbreg_trap(void) 2499{ 2500 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2501 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2502 int nbp; /* number of breakpoints that triggered */ 2503 caddr_t addr[4]; /* breakpoint addresses */ 2504 int i; 2505 2506 dr7 = rdr7(); 2507 if ((dr7 & 0x000000ff) == 0) { 2508 /* 2509 * all GE and LE bits in the dr7 register are zero, 2510 * thus the trap couldn't have been caused by the 2511 * hardware debug registers 2512 */ 2513 return 0; 2514 } 2515 2516 nbp = 0; 2517 dr6 = rdr6(); 2518 bp = dr6 & 0x0000000f; 2519 2520 if (!bp) { 2521 /* 2522 * None of the breakpoint bits are set meaning this 2523 * trap was not caused by any of the debug registers 2524 */ 2525 return 0; 2526 } 2527 2528 /* 2529 * at least one of the breakpoints were hit, check to see 2530 * which ones and if any of them are user space addresses 2531 */ 2532 2533 if (bp & 0x01) { 2534 addr[nbp++] = (caddr_t)rdr0(); 2535 } 2536 if (bp & 0x02) { 2537 addr[nbp++] = (caddr_t)rdr1(); 2538 } 2539 if (bp & 0x04) { 2540 addr[nbp++] = (caddr_t)rdr2(); 2541 } 2542 if (bp & 0x08) { 2543 addr[nbp++] = (caddr_t)rdr3(); 2544 } 2545 2546 for (i = 0; i < nbp; i++) { 2547 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2548 /* 2549 * addr[i] is in user space 2550 */ 2551 return nbp; 2552 } 2553 } 2554 2555 /* 2556 * None of the breakpoints are in user space. 2557 */ 2558 return 0; 2559} 2560 2561#ifdef KDB 2562 2563/* 2564 * Provide inb() and outb() as functions. They are normally only available as 2565 * inline functions, thus cannot be called from the debugger. 2566 */ 2567 2568/* silence compiler warnings */ 2569u_char inb_(u_short); 2570void outb_(u_short, u_char); 2571 2572u_char 2573inb_(u_short port) 2574{ 2575 return inb(port); 2576} 2577 2578void 2579outb_(u_short port, u_char data) 2580{ 2581 outb(port, data); 2582} 2583 2584#endif /* KDB */ 2585