machdep.c revision 258559
12965Swollman/*- 227624Scharnier * Copyright (c) 2003 Peter Wemm. 32965Swollman * Copyright (c) 1992 Terrence R. Lambert. 42965Swollman * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 57094Swollman * All rights reserved. 62965Swollman * 72965Swollman * This code is derived from software contributed to Berkeley by 899112Sobrien * William Jolitz. 999112Sobrien * 1099112Sobrien * Redistribution and use in source and binary forms, with or without 1132593Sbde * modification, are permitted provided that the following conditions 1232593Sbde * are met: 132965Swollman * 1. Redistributions of source code must retain the above copyright 142965Swollman * notice, this list of conditions and the following disclaimer. 1523350Sbde * 2. Redistributions in binary form must reproduce the above copyright 1623350Sbde * notice, this list of conditions and the following disclaimer in the 172965Swollman * documentation and/or other materials provided with the distribution. 1823350Sbde * 3. All advertising materials mentioning features or use of this software 192965Swollman * must display the following acknowledgement: 2038619Sbde * This product includes software developed by the University of 2138619Sbde * California, Berkeley and its contributors. 2238619Sbde * 4. Neither the name of the University nor the names of its contributors 232965Swollman * may be used to endorse or promote products derived from this software 247094Swollman * without specific prior written permission. 257094Swollman * 262965Swollman * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 272965Swollman * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 282965Swollman * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 292965Swollman * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 3032593Sbde * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3132593Sbde * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 322965Swollman * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 332965Swollman * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 342965Swollman * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 352965Swollman * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3638619Sbde * SUCH DAMAGE. 372965Swollman * 382965Swollman * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 392965Swollman */ 402965Swollman 4147701Sru#include <sys/cdefs.h> 4238619Sbde__FBSDID("$FreeBSD: stable/10/sys/amd64/amd64/machdep.c 258559 2013-11-25 15:58:48Z emaste $"); 432965Swollman 442984Swollman#include "opt_atalk.h" 452965Swollman#include "opt_atpic.h" 462965Swollman#include "opt_compat.h" 472965Swollman#include "opt_cpu.h" 482965Swollman#include "opt_ddb.h" 4978716Sdd#include "opt_inet.h" 5038619Sbde#include "opt_ipx.h" 5132593Sbde#include "opt_isa.h" 522965Swollman#include "opt_kstack_pages.h" 532965Swollman#include "opt_maxmem.h" 542965Swollman#include "opt_mp_watchdog.h" 552965Swollman#include "opt_perfmon.h" 562965Swollman#include "opt_platform.h" 572965Swollman#include "opt_sched.h" 582965Swollman#include "opt_kdtrace.h" 597094Swollman 607094Swollman#include <sys/param.h> 617094Swollman#include <sys/proc.h> 627096Swollman#include <sys/systm.h> 637096Swollman#include <sys/bio.h> 647096Swollman#include <sys/buf.h> 6523350Sbde#include <sys/bus.h> 6623350Sbde#include <sys/callout.h> 677096Swollman#include <sys/cons.h> 687096Swollman#include <sys/cpu.h> 697096Swollman#include <sys/eventhandler.h> 707096Swollman#include <sys/exec.h> 717096Swollman#include <sys/imgact.h> 727096Swollman#include <sys/kdb.h> 737096Swollman#include <sys/kernel.h> 747096Swollman#include <sys/ktr.h> 757096Swollman#include <sys/linker.h> 767096Swollman#include <sys/lock.h> 777096Swollman#include <sys/malloc.h> 787096Swollman#include <sys/memrange.h> 797096Swollman#include <sys/msgbuf.h> 807096Swollman#include <sys/mutex.h> 817096Swollman#include <sys/pcpu.h> 827096Swollman#include <sys/ptrace.h> 837096Swollman#include <sys/reboot.h> 847096Swollman#include <sys/rwlock.h> 857096Swollman#include <sys/sched.h> 867096Swollman#include <sys/signalvar.h> 877096Swollman#ifdef SMP 887096Swollman#include <sys/smp.h> 897096Swollman#endif 907096Swollman#include <sys/syscallsubr.h> 917096Swollman#include <sys/sysctl.h> 927096Swollman#include <sys/sysent.h> 937096Swollman#include <sys/sysproto.h> 947096Swollman#include <sys/ucontext.h> 957096Swollman#include <sys/vmmeter.h> 9623350Sbde 9723350Sbde#include <vm/vm.h> 9823350Sbde#include <vm/vm_extern.h> 9923350Sbde#include <vm/vm_kern.h> 10023350Sbde#include <vm/vm_page.h> 1017096Swollman#include <vm/vm_map.h> 1027094Swollman#include <vm/vm_object.h> 103#include <vm/vm_pager.h> 104#include <vm/vm_param.h> 105 106#ifdef DDB 107#ifndef KDB 108#error KDB must be enabled in order for DDB to work! 109#endif 110#include <ddb/ddb.h> 111#include <ddb/db_sym.h> 112#endif 113 114#include <net/netisr.h> 115 116#include <machine/clock.h> 117#include <machine/cpu.h> 118#include <machine/cputypes.h> 119#include <machine/intr_machdep.h> 120#include <x86/mca.h> 121#include <machine/md_var.h> 122#include <machine/metadata.h> 123#include <machine/mp_watchdog.h> 124#include <machine/pc/bios.h> 125#include <machine/pcb.h> 126#include <machine/proc.h> 127#include <machine/reg.h> 128#include <machine/sigframe.h> 129#include <machine/specialreg.h> 130#ifdef PERFMON 131#include <machine/perfmon.h> 132#endif 133#include <machine/tss.h> 134#ifdef SMP 135#include <machine/smp.h> 136#endif 137#ifdef FDT 138#include <x86/fdt.h> 139#endif 140 141#ifdef DEV_ATPIC 142#include <x86/isa/icu.h> 143#else 144#include <machine/apicvar.h> 145#endif 146 147#include <isa/isareg.h> 148#include <isa/rtc.h> 149 150/* Sanity check for __curthread() */ 151CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 152 153extern u_int64_t hammer_time(u_int64_t, u_int64_t); 154 155extern void printcpuinfo(void); /* XXX header file */ 156extern void identify_cpu(void); 157extern void panicifcpuunsupported(void); 158 159#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 160#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 161 162static void cpu_startup(void *); 163static void get_fpcontext(struct thread *td, mcontext_t *mcp, 164 char *xfpusave, size_t xfpusave_len); 165static int set_fpcontext(struct thread *td, const mcontext_t *mcp, 166 char *xfpustate, size_t xfpustate_len); 167SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 168 169/* 170 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 171 * the physical address at which the kernel is loaded. 172 */ 173extern char kernphys[]; 174#ifdef DDB 175extern vm_offset_t ksym_start, ksym_end; 176#endif 177 178struct msgbuf *msgbufp; 179 180/* Intel ICH registers */ 181#define ICH_PMBASE 0x400 182#define ICH_SMI_EN ICH_PMBASE + 0x30 183 184int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 185 186int cold = 1; 187 188long Maxmem = 0; 189long realmem = 0; 190 191/* 192 * The number of PHYSMAP entries must be one less than the number of 193 * PHYSSEG entries because the PHYSMAP entry that spans the largest 194 * physical address that is accessible by ISA DMA is split into two 195 * PHYSSEG entries. 196 */ 197#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 198 199vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 200vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 201 202/* must be 2 less so 0 0 can signal end of chunks */ 203#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 204#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 205 206struct kva_md_info kmi; 207 208static struct trapframe proc0_tf; 209struct region_descriptor r_gdt, r_idt; 210 211struct pcpu __pcpu[MAXCPU]; 212 213struct mtx icu_lock; 214 215struct mem_range_softc mem_range_softc; 216 217struct mtx dt_lock; /* lock for GDT and LDT */ 218 219static void 220cpu_startup(dummy) 221 void *dummy; 222{ 223 uintmax_t memsize; 224 char *sysenv; 225 226 /* 227 * On MacBooks, we need to disallow the legacy USB circuit to 228 * generate an SMI# because this can cause several problems, 229 * namely: incorrect CPU frequency detection and failure to 230 * start the APs. 231 * We do this by disabling a bit in the SMI_EN (SMI Control and 232 * Enable register) of the Intel ICH LPC Interface Bridge. 233 */ 234 sysenv = getenv("smbios.system.product"); 235 if (sysenv != NULL) { 236 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 237 strncmp(sysenv, "MacBook3,1", 10) == 0 || 238 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 239 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 240 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 241 strncmp(sysenv, "Macmini1,1", 10) == 0) { 242 if (bootverbose) 243 printf("Disabling LEGACY_USB_EN bit on " 244 "Intel ICH.\n"); 245 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 246 } 247 freeenv(sysenv); 248 } 249 250 /* 251 * Good {morning,afternoon,evening,night}. 252 */ 253 startrtclock(); 254 printcpuinfo(); 255 panicifcpuunsupported(); 256#ifdef PERFMON 257 perfmon_init(); 258#endif 259 realmem = Maxmem; 260 261 /* 262 * Display physical memory if SMBIOS reports reasonable amount. 263 */ 264 memsize = 0; 265 sysenv = getenv("smbios.memory.enabled"); 266 if (sysenv != NULL) { 267 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 268 freeenv(sysenv); 269 } 270 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 271 memsize = ptoa((uintmax_t)Maxmem); 272 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 273 274 /* 275 * Display any holes after the first chunk of extended memory. 276 */ 277 if (bootverbose) { 278 int indx; 279 280 printf("Physical memory chunk(s):\n"); 281 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 282 vm_paddr_t size; 283 284 size = phys_avail[indx + 1] - phys_avail[indx]; 285 printf( 286 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 287 (uintmax_t)phys_avail[indx], 288 (uintmax_t)phys_avail[indx + 1] - 1, 289 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 290 } 291 } 292 293 vm_ksubmap_init(&kmi); 294 295 printf("avail memory = %ju (%ju MB)\n", 296 ptoa((uintmax_t)cnt.v_free_count), 297 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 298 299 /* 300 * Set up buffers, so they can be used to read disk labels. 301 */ 302 bufinit(); 303 vm_pager_bufferinit(); 304 305 cpu_setregs(); 306} 307 308/* 309 * Send an interrupt to process. 310 * 311 * Stack is set up to allow sigcode stored 312 * at top to call routine, followed by call 313 * to sigreturn routine below. After sigreturn 314 * resets the signal mask, the stack, and the 315 * frame pointer, it returns to the user 316 * specified pc, psl. 317 */ 318void 319sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 320{ 321 struct sigframe sf, *sfp; 322 struct pcb *pcb; 323 struct proc *p; 324 struct thread *td; 325 struct sigacts *psp; 326 char *sp; 327 struct trapframe *regs; 328 char *xfpusave; 329 size_t xfpusave_len; 330 int sig; 331 int oonstack; 332 333 td = curthread; 334 pcb = td->td_pcb; 335 p = td->td_proc; 336 PROC_LOCK_ASSERT(p, MA_OWNED); 337 sig = ksi->ksi_signo; 338 psp = p->p_sigacts; 339 mtx_assert(&psp->ps_mtx, MA_OWNED); 340 regs = td->td_frame; 341 oonstack = sigonstack(regs->tf_rsp); 342 343 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) { 344 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu); 345 xfpusave = __builtin_alloca(xfpusave_len); 346 } else { 347 xfpusave_len = 0; 348 xfpusave = NULL; 349 } 350 351 /* Save user context. */ 352 bzero(&sf, sizeof(sf)); 353 sf.sf_uc.uc_sigmask = *mask; 354 sf.sf_uc.uc_stack = td->td_sigstk; 355 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 356 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 357 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 358 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 359 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 360 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len); 361 fpstate_drop(td); 362 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 363 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 364 bzero(sf.sf_uc.uc_mcontext.mc_spare, 365 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 366 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 367 368 /* Allocate space for the signal handler context. */ 369 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 370 SIGISMEMBER(psp->ps_sigonstack, sig)) { 371 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size; 372#if defined(COMPAT_43) 373 td->td_sigstk.ss_flags |= SS_ONSTACK; 374#endif 375 } else 376 sp = (char *)regs->tf_rsp - 128; 377 if (xfpusave != NULL) { 378 sp -= xfpusave_len; 379 sp = (char *)((unsigned long)sp & ~0x3Ful); 380 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp; 381 } 382 sp -= sizeof(struct sigframe); 383 /* Align to 16 bytes. */ 384 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 385 386 /* Translate the signal if appropriate. */ 387 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 388 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 389 390 /* Build the argument list for the signal handler. */ 391 regs->tf_rdi = sig; /* arg 1 in %rdi */ 392 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 393 bzero(&sf.sf_si, sizeof(sf.sf_si)); 394 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 395 /* Signal handler installed with SA_SIGINFO. */ 396 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 397 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 398 399 /* Fill in POSIX parts */ 400 sf.sf_si = ksi->ksi_info; 401 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 402 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 403 } else { 404 /* Old FreeBSD-style arguments. */ 405 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 406 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 407 sf.sf_ahu.sf_handler = catcher; 408 } 409 mtx_unlock(&psp->ps_mtx); 410 PROC_UNLOCK(p); 411 412 /* 413 * Copy the sigframe out to the user's stack. 414 */ 415 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 || 416 (xfpusave != NULL && copyout(xfpusave, 417 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len) 418 != 0)) { 419#ifdef DEBUG 420 printf("process %ld has trashed its stack\n", (long)p->p_pid); 421#endif 422 PROC_LOCK(p); 423 sigexit(td, SIGILL); 424 } 425 426 regs->tf_rsp = (long)sfp; 427 regs->tf_rip = p->p_sysent->sv_sigcode_base; 428 regs->tf_rflags &= ~(PSL_T | PSL_D); 429 regs->tf_cs = _ucodesel; 430 regs->tf_ds = _udatasel; 431 regs->tf_es = _udatasel; 432 regs->tf_fs = _ufssel; 433 regs->tf_gs = _ugssel; 434 regs->tf_flags = TF_HASSEGS; 435 set_pcb_flags(pcb, PCB_FULL_IRET); 436 PROC_LOCK(p); 437 mtx_lock(&psp->ps_mtx); 438} 439 440/* 441 * System call to cleanup state after a signal 442 * has been taken. Reset signal mask and 443 * stack state from context left by sendsig (above). 444 * Return to previous pc and psl as specified by 445 * context left by sendsig. Check carefully to 446 * make sure that the user has not modified the 447 * state to gain improper privileges. 448 * 449 * MPSAFE 450 */ 451int 452sys_sigreturn(td, uap) 453 struct thread *td; 454 struct sigreturn_args /* { 455 const struct __ucontext *sigcntxp; 456 } */ *uap; 457{ 458 ucontext_t uc; 459 struct pcb *pcb; 460 struct proc *p; 461 struct trapframe *regs; 462 ucontext_t *ucp; 463 char *xfpustate; 464 size_t xfpustate_len; 465 long rflags; 466 int cs, error, ret; 467 ksiginfo_t ksi; 468 469 pcb = td->td_pcb; 470 p = td->td_proc; 471 472 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 473 if (error != 0) { 474 uprintf("pid %d (%s): sigreturn copyin failed\n", 475 p->p_pid, td->td_name); 476 return (error); 477 } 478 ucp = &uc; 479 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 480 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 481 td->td_name, ucp->uc_mcontext.mc_flags); 482 return (EINVAL); 483 } 484 regs = td->td_frame; 485 rflags = ucp->uc_mcontext.mc_rflags; 486 /* 487 * Don't allow users to change privileged or reserved flags. 488 */ 489 if (!EFL_SECURE(rflags, regs->tf_rflags)) { 490 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 491 td->td_name, rflags); 492 return (EINVAL); 493 } 494 495 /* 496 * Don't allow users to load a valid privileged %cs. Let the 497 * hardware check for invalid selectors, excess privilege in 498 * other selectors, invalid %eip's and invalid %esp's. 499 */ 500 cs = ucp->uc_mcontext.mc_cs; 501 if (!CS_SECURE(cs)) { 502 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 503 td->td_name, cs); 504 ksiginfo_init_trap(&ksi); 505 ksi.ksi_signo = SIGBUS; 506 ksi.ksi_code = BUS_OBJERR; 507 ksi.ksi_trapno = T_PROTFLT; 508 ksi.ksi_addr = (void *)regs->tf_rip; 509 trapsignal(td, &ksi); 510 return (EINVAL); 511 } 512 513 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) { 514 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len; 515 if (xfpustate_len > cpu_max_ext_state_size - 516 sizeof(struct savefpu)) { 517 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n", 518 p->p_pid, td->td_name, xfpustate_len); 519 return (EINVAL); 520 } 521 xfpustate = __builtin_alloca(xfpustate_len); 522 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate, 523 xfpustate, xfpustate_len); 524 if (error != 0) { 525 uprintf( 526 "pid %d (%s): sigreturn copying xfpustate failed\n", 527 p->p_pid, td->td_name); 528 return (error); 529 } 530 } else { 531 xfpustate = NULL; 532 xfpustate_len = 0; 533 } 534 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len); 535 if (ret != 0) { 536 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 537 p->p_pid, td->td_name, ret); 538 return (ret); 539 } 540 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 541 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 542 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 543 544#if defined(COMPAT_43) 545 if (ucp->uc_mcontext.mc_onstack & 1) 546 td->td_sigstk.ss_flags |= SS_ONSTACK; 547 else 548 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 549#endif 550 551 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 552 set_pcb_flags(pcb, PCB_FULL_IRET); 553 return (EJUSTRETURN); 554} 555 556#ifdef COMPAT_FREEBSD4 557int 558freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 559{ 560 561 return sys_sigreturn(td, (struct sigreturn_args *)uap); 562} 563#endif 564 565 566/* 567 * Machine dependent boot() routine 568 * 569 * I haven't seen anything to put here yet 570 * Possibly some stuff might be grafted back here from boot() 571 */ 572void 573cpu_boot(int howto) 574{ 575} 576 577/* 578 * Flush the D-cache for non-DMA I/O so that the I-cache can 579 * be made coherent later. 580 */ 581void 582cpu_flush_dcache(void *ptr, size_t len) 583{ 584 /* Not applicable */ 585} 586 587/* Get current clock frequency for the given cpu id. */ 588int 589cpu_est_clockrate(int cpu_id, uint64_t *rate) 590{ 591 uint64_t tsc1, tsc2; 592 uint64_t acnt, mcnt, perf; 593 register_t reg; 594 595 if (pcpu_find(cpu_id) == NULL || rate == NULL) 596 return (EINVAL); 597 598 /* 599 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 600 * DELAY(9) based logic fails. 601 */ 602 if (tsc_is_invariant && !tsc_perf_stat) 603 return (EOPNOTSUPP); 604 605#ifdef SMP 606 if (smp_cpus > 1) { 607 /* Schedule ourselves on the indicated cpu. */ 608 thread_lock(curthread); 609 sched_bind(curthread, cpu_id); 610 thread_unlock(curthread); 611 } 612#endif 613 614 /* Calibrate by measuring a short delay. */ 615 reg = intr_disable(); 616 if (tsc_is_invariant) { 617 wrmsr(MSR_MPERF, 0); 618 wrmsr(MSR_APERF, 0); 619 tsc1 = rdtsc(); 620 DELAY(1000); 621 mcnt = rdmsr(MSR_MPERF); 622 acnt = rdmsr(MSR_APERF); 623 tsc2 = rdtsc(); 624 intr_restore(reg); 625 perf = 1000 * acnt / mcnt; 626 *rate = (tsc2 - tsc1) * perf; 627 } else { 628 tsc1 = rdtsc(); 629 DELAY(1000); 630 tsc2 = rdtsc(); 631 intr_restore(reg); 632 *rate = (tsc2 - tsc1) * 1000; 633 } 634 635#ifdef SMP 636 if (smp_cpus > 1) { 637 thread_lock(curthread); 638 sched_unbind(curthread); 639 thread_unlock(curthread); 640 } 641#endif 642 643 return (0); 644} 645 646/* 647 * Shutdown the CPU as much as possible 648 */ 649void 650cpu_halt(void) 651{ 652 for (;;) 653 halt(); 654} 655 656void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 657static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 658static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 659TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 660SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 661 0, "Use MONITOR/MWAIT for short idle"); 662 663#define STATE_RUNNING 0x0 664#define STATE_MWAIT 0x1 665#define STATE_SLEEPING 0x2 666 667static void 668cpu_idle_acpi(sbintime_t sbt) 669{ 670 int *state; 671 672 state = (int *)PCPU_PTR(monitorbuf); 673 *state = STATE_SLEEPING; 674 675 /* See comments in cpu_idle_hlt(). */ 676 disable_intr(); 677 if (sched_runnable()) 678 enable_intr(); 679 else if (cpu_idle_hook) 680 cpu_idle_hook(sbt); 681 else 682 __asm __volatile("sti; hlt"); 683 *state = STATE_RUNNING; 684} 685 686static void 687cpu_idle_hlt(sbintime_t sbt) 688{ 689 int *state; 690 691 state = (int *)PCPU_PTR(monitorbuf); 692 *state = STATE_SLEEPING; 693 694 /* 695 * Since we may be in a critical section from cpu_idle(), if 696 * an interrupt fires during that critical section we may have 697 * a pending preemption. If the CPU halts, then that thread 698 * may not execute until a later interrupt awakens the CPU. 699 * To handle this race, check for a runnable thread after 700 * disabling interrupts and immediately return if one is 701 * found. Also, we must absolutely guarentee that hlt is 702 * the next instruction after sti. This ensures that any 703 * interrupt that fires after the call to disable_intr() will 704 * immediately awaken the CPU from hlt. Finally, please note 705 * that on x86 this works fine because of interrupts enabled only 706 * after the instruction following sti takes place, while IF is set 707 * to 1 immediately, allowing hlt instruction to acknowledge the 708 * interrupt. 709 */ 710 disable_intr(); 711 if (sched_runnable()) 712 enable_intr(); 713 else 714 __asm __volatile("sti; hlt"); 715 *state = STATE_RUNNING; 716} 717 718/* 719 * MWAIT cpu power states. Lower 4 bits are sub-states. 720 */ 721#define MWAIT_C0 0xf0 722#define MWAIT_C1 0x00 723#define MWAIT_C2 0x10 724#define MWAIT_C3 0x20 725#define MWAIT_C4 0x30 726 727static void 728cpu_idle_mwait(sbintime_t sbt) 729{ 730 int *state; 731 732 state = (int *)PCPU_PTR(monitorbuf); 733 *state = STATE_MWAIT; 734 735 /* See comments in cpu_idle_hlt(). */ 736 disable_intr(); 737 if (sched_runnable()) { 738 enable_intr(); 739 *state = STATE_RUNNING; 740 return; 741 } 742 cpu_monitor(state, 0, 0); 743 if (*state == STATE_MWAIT) 744 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 745 else 746 enable_intr(); 747 *state = STATE_RUNNING; 748} 749 750static void 751cpu_idle_spin(sbintime_t sbt) 752{ 753 int *state; 754 int i; 755 756 state = (int *)PCPU_PTR(monitorbuf); 757 *state = STATE_RUNNING; 758 759 /* 760 * The sched_runnable() call is racy but as long as there is 761 * a loop missing it one time will have just a little impact if any 762 * (and it is much better than missing the check at all). 763 */ 764 for (i = 0; i < 1000; i++) { 765 if (sched_runnable()) 766 return; 767 cpu_spinwait(); 768 } 769} 770 771/* 772 * C1E renders the local APIC timer dead, so we disable it by 773 * reading the Interrupt Pending Message register and clearing 774 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 775 * 776 * Reference: 777 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 778 * #32559 revision 3.00+ 779 */ 780#define MSR_AMDK8_IPM 0xc0010055 781#define AMDK8_SMIONCMPHALT (1ULL << 27) 782#define AMDK8_C1EONCMPHALT (1ULL << 28) 783#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 784 785static void 786cpu_probe_amdc1e(void) 787{ 788 789 /* 790 * Detect the presence of C1E capability mostly on latest 791 * dual-cores (or future) k8 family. 792 */ 793 if (cpu_vendor_id == CPU_VENDOR_AMD && 794 (cpu_id & 0x00000f00) == 0x00000f00 && 795 (cpu_id & 0x0fff0000) >= 0x00040000) { 796 cpu_ident_amdc1e = 1; 797 } 798} 799 800void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 801 802void 803cpu_idle(int busy) 804{ 805 uint64_t msr; 806 sbintime_t sbt = -1; 807 808 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 809 busy, curcpu); 810#ifdef MP_WATCHDOG 811 ap_watchdog(PCPU_GET(cpuid)); 812#endif 813 /* If we are busy - try to use fast methods. */ 814 if (busy) { 815 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 816 cpu_idle_mwait(busy); 817 goto out; 818 } 819 } 820 821 /* If we have time - switch timers into idle mode. */ 822 if (!busy) { 823 critical_enter(); 824 sbt = cpu_idleclock(); 825 } 826 827 /* Apply AMD APIC timer C1E workaround. */ 828 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { 829 msr = rdmsr(MSR_AMDK8_IPM); 830 if (msr & AMDK8_CMPHALT) 831 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 832 } 833 834 /* Call main idle method. */ 835 cpu_idle_fn(sbt); 836 837 /* Switch timers mack into active mode. */ 838 if (!busy) { 839 cpu_activeclock(); 840 critical_exit(); 841 } 842out: 843 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 844 busy, curcpu); 845} 846 847int 848cpu_idle_wakeup(int cpu) 849{ 850 struct pcpu *pcpu; 851 int *state; 852 853 pcpu = pcpu_find(cpu); 854 state = (int *)pcpu->pc_monitorbuf; 855 /* 856 * This doesn't need to be atomic since missing the race will 857 * simply result in unnecessary IPIs. 858 */ 859 if (*state == STATE_SLEEPING) 860 return (0); 861 if (*state == STATE_MWAIT) 862 *state = STATE_RUNNING; 863 return (1); 864} 865 866/* 867 * Ordered by speed/power consumption. 868 */ 869struct { 870 void *id_fn; 871 char *id_name; 872} idle_tbl[] = { 873 { cpu_idle_spin, "spin" }, 874 { cpu_idle_mwait, "mwait" }, 875 { cpu_idle_hlt, "hlt" }, 876 { cpu_idle_acpi, "acpi" }, 877 { NULL, NULL } 878}; 879 880static int 881idle_sysctl_available(SYSCTL_HANDLER_ARGS) 882{ 883 char *avail, *p; 884 int error; 885 int i; 886 887 avail = malloc(256, M_TEMP, M_WAITOK); 888 p = avail; 889 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 890 if (strstr(idle_tbl[i].id_name, "mwait") && 891 (cpu_feature2 & CPUID2_MON) == 0) 892 continue; 893 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 894 cpu_idle_hook == NULL) 895 continue; 896 p += sprintf(p, "%s%s", p != avail ? ", " : "", 897 idle_tbl[i].id_name); 898 } 899 error = sysctl_handle_string(oidp, avail, 0, req); 900 free(avail, M_TEMP); 901 return (error); 902} 903 904SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 905 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 906 907static int 908idle_sysctl(SYSCTL_HANDLER_ARGS) 909{ 910 char buf[16]; 911 int error; 912 char *p; 913 int i; 914 915 p = "unknown"; 916 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 917 if (idle_tbl[i].id_fn == cpu_idle_fn) { 918 p = idle_tbl[i].id_name; 919 break; 920 } 921 } 922 strncpy(buf, p, sizeof(buf)); 923 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 924 if (error != 0 || req->newptr == NULL) 925 return (error); 926 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 927 if (strstr(idle_tbl[i].id_name, "mwait") && 928 (cpu_feature2 & CPUID2_MON) == 0) 929 continue; 930 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 931 cpu_idle_hook == NULL) 932 continue; 933 if (strcmp(idle_tbl[i].id_name, buf)) 934 continue; 935 cpu_idle_fn = idle_tbl[i].id_fn; 936 return (0); 937 } 938 return (EINVAL); 939} 940 941SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 942 idle_sysctl, "A", "currently selected idle function"); 943 944/* 945 * Reset registers to default values on exec. 946 */ 947void 948exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 949{ 950 struct trapframe *regs = td->td_frame; 951 struct pcb *pcb = td->td_pcb; 952 953 mtx_lock(&dt_lock); 954 if (td->td_proc->p_md.md_ldt != NULL) 955 user_ldt_free(td); 956 else 957 mtx_unlock(&dt_lock); 958 959 pcb->pcb_fsbase = 0; 960 pcb->pcb_gsbase = 0; 961 clear_pcb_flags(pcb, PCB_32BIT); 962 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 963 set_pcb_flags(pcb, PCB_FULL_IRET); 964 965 bzero((char *)regs, sizeof(struct trapframe)); 966 regs->tf_rip = imgp->entry_addr; 967 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 968 regs->tf_rdi = stack; /* argv */ 969 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 970 regs->tf_ss = _udatasel; 971 regs->tf_cs = _ucodesel; 972 regs->tf_ds = _udatasel; 973 regs->tf_es = _udatasel; 974 regs->tf_fs = _ufssel; 975 regs->tf_gs = _ugssel; 976 regs->tf_flags = TF_HASSEGS; 977 td->td_retval[1] = 0; 978 979 /* 980 * Reset the hardware debug registers if they were in use. 981 * They won't have any meaning for the newly exec'd process. 982 */ 983 if (pcb->pcb_flags & PCB_DBREGS) { 984 pcb->pcb_dr0 = 0; 985 pcb->pcb_dr1 = 0; 986 pcb->pcb_dr2 = 0; 987 pcb->pcb_dr3 = 0; 988 pcb->pcb_dr6 = 0; 989 pcb->pcb_dr7 = 0; 990 if (pcb == curpcb) { 991 /* 992 * Clear the debug registers on the running 993 * CPU, otherwise they will end up affecting 994 * the next process we switch to. 995 */ 996 reset_dbregs(); 997 } 998 clear_pcb_flags(pcb, PCB_DBREGS); 999 } 1000 1001 /* 1002 * Drop the FP state if we hold it, so that the process gets a 1003 * clean FP state if it uses the FPU again. 1004 */ 1005 fpstate_drop(td); 1006} 1007 1008void 1009cpu_setregs(void) 1010{ 1011 register_t cr0; 1012 1013 cr0 = rcr0(); 1014 /* 1015 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 1016 * BSP. See the comments there about why we set them. 1017 */ 1018 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 1019 load_cr0(cr0); 1020} 1021 1022/* 1023 * Initialize amd64 and configure to run kernel 1024 */ 1025 1026/* 1027 * Initialize segments & interrupt table 1028 */ 1029 1030struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 1031static struct gate_descriptor idt0[NIDT]; 1032struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 1033 1034static char dblfault_stack[PAGE_SIZE] __aligned(16); 1035 1036static char nmi0_stack[PAGE_SIZE] __aligned(16); 1037CTASSERT(sizeof(struct nmi_pcpu) == 16); 1038 1039struct amd64tss common_tss[MAXCPU]; 1040 1041/* 1042 * Software prototypes -- in more palatable form. 1043 * 1044 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 1045 * slots as corresponding segments for i386 kernel. 1046 */ 1047struct soft_segment_descriptor gdt_segs[] = { 1048/* GNULL_SEL 0 Null Descriptor */ 1049{ .ssd_base = 0x0, 1050 .ssd_limit = 0x0, 1051 .ssd_type = 0, 1052 .ssd_dpl = 0, 1053 .ssd_p = 0, 1054 .ssd_long = 0, 1055 .ssd_def32 = 0, 1056 .ssd_gran = 0 }, 1057/* GNULL2_SEL 1 Null Descriptor */ 1058{ .ssd_base = 0x0, 1059 .ssd_limit = 0x0, 1060 .ssd_type = 0, 1061 .ssd_dpl = 0, 1062 .ssd_p = 0, 1063 .ssd_long = 0, 1064 .ssd_def32 = 0, 1065 .ssd_gran = 0 }, 1066/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 1067{ .ssd_base = 0x0, 1068 .ssd_limit = 0xfffff, 1069 .ssd_type = SDT_MEMRWA, 1070 .ssd_dpl = SEL_UPL, 1071 .ssd_p = 1, 1072 .ssd_long = 0, 1073 .ssd_def32 = 1, 1074 .ssd_gran = 1 }, 1075/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1076{ .ssd_base = 0x0, 1077 .ssd_limit = 0xfffff, 1078 .ssd_type = SDT_MEMRWA, 1079 .ssd_dpl = SEL_UPL, 1080 .ssd_p = 1, 1081 .ssd_long = 0, 1082 .ssd_def32 = 1, 1083 .ssd_gran = 1 }, 1084/* GCODE_SEL 4 Code Descriptor for kernel */ 1085{ .ssd_base = 0x0, 1086 .ssd_limit = 0xfffff, 1087 .ssd_type = SDT_MEMERA, 1088 .ssd_dpl = SEL_KPL, 1089 .ssd_p = 1, 1090 .ssd_long = 1, 1091 .ssd_def32 = 0, 1092 .ssd_gran = 1 }, 1093/* GDATA_SEL 5 Data Descriptor for kernel */ 1094{ .ssd_base = 0x0, 1095 .ssd_limit = 0xfffff, 1096 .ssd_type = SDT_MEMRWA, 1097 .ssd_dpl = SEL_KPL, 1098 .ssd_p = 1, 1099 .ssd_long = 1, 1100 .ssd_def32 = 0, 1101 .ssd_gran = 1 }, 1102/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1103{ .ssd_base = 0x0, 1104 .ssd_limit = 0xfffff, 1105 .ssd_type = SDT_MEMERA, 1106 .ssd_dpl = SEL_UPL, 1107 .ssd_p = 1, 1108 .ssd_long = 0, 1109 .ssd_def32 = 1, 1110 .ssd_gran = 1 }, 1111/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1112{ .ssd_base = 0x0, 1113 .ssd_limit = 0xfffff, 1114 .ssd_type = SDT_MEMRWA, 1115 .ssd_dpl = SEL_UPL, 1116 .ssd_p = 1, 1117 .ssd_long = 0, 1118 .ssd_def32 = 1, 1119 .ssd_gran = 1 }, 1120/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1121{ .ssd_base = 0x0, 1122 .ssd_limit = 0xfffff, 1123 .ssd_type = SDT_MEMERA, 1124 .ssd_dpl = SEL_UPL, 1125 .ssd_p = 1, 1126 .ssd_long = 1, 1127 .ssd_def32 = 0, 1128 .ssd_gran = 1 }, 1129/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1130{ .ssd_base = 0x0, 1131 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1132 .ssd_type = SDT_SYSTSS, 1133 .ssd_dpl = SEL_KPL, 1134 .ssd_p = 1, 1135 .ssd_long = 0, 1136 .ssd_def32 = 0, 1137 .ssd_gran = 0 }, 1138/* Actually, the TSS is a system descriptor which is double size */ 1139{ .ssd_base = 0x0, 1140 .ssd_limit = 0x0, 1141 .ssd_type = 0, 1142 .ssd_dpl = 0, 1143 .ssd_p = 0, 1144 .ssd_long = 0, 1145 .ssd_def32 = 0, 1146 .ssd_gran = 0 }, 1147/* GUSERLDT_SEL 11 LDT Descriptor */ 1148{ .ssd_base = 0x0, 1149 .ssd_limit = 0x0, 1150 .ssd_type = 0, 1151 .ssd_dpl = 0, 1152 .ssd_p = 0, 1153 .ssd_long = 0, 1154 .ssd_def32 = 0, 1155 .ssd_gran = 0 }, 1156/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1157{ .ssd_base = 0x0, 1158 .ssd_limit = 0x0, 1159 .ssd_type = 0, 1160 .ssd_dpl = 0, 1161 .ssd_p = 0, 1162 .ssd_long = 0, 1163 .ssd_def32 = 0, 1164 .ssd_gran = 0 }, 1165}; 1166 1167void 1168setidt(idx, func, typ, dpl, ist) 1169 int idx; 1170 inthand_t *func; 1171 int typ; 1172 int dpl; 1173 int ist; 1174{ 1175 struct gate_descriptor *ip; 1176 1177 ip = idt + idx; 1178 ip->gd_looffset = (uintptr_t)func; 1179 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1180 ip->gd_ist = ist; 1181 ip->gd_xx = 0; 1182 ip->gd_type = typ; 1183 ip->gd_dpl = dpl; 1184 ip->gd_p = 1; 1185 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1186} 1187 1188extern inthand_t 1189 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1190 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1191 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1192 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1193 IDTVEC(xmm), IDTVEC(dblfault), 1194#ifdef KDTRACE_HOOKS 1195 IDTVEC(dtrace_ret), 1196#endif 1197#ifdef XENHVM 1198 IDTVEC(xen_intr_upcall), 1199#endif 1200 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1201 1202#ifdef DDB 1203/* 1204 * Display the index and function name of any IDT entries that don't use 1205 * the default 'rsvd' entry point. 1206 */ 1207DB_SHOW_COMMAND(idt, db_show_idt) 1208{ 1209 struct gate_descriptor *ip; 1210 int idx; 1211 uintptr_t func; 1212 1213 ip = idt; 1214 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1215 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1216 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1217 db_printf("%3d\t", idx); 1218 db_printsym(func, DB_STGY_PROC); 1219 db_printf("\n"); 1220 } 1221 ip++; 1222 } 1223} 1224 1225/* Show privileged registers. */ 1226DB_SHOW_COMMAND(sysregs, db_show_sysregs) 1227{ 1228 struct { 1229 uint16_t limit; 1230 uint64_t base; 1231 } __packed idtr, gdtr; 1232 uint16_t ldt, tr; 1233 1234 __asm __volatile("sidt %0" : "=m" (idtr)); 1235 db_printf("idtr\t0x%016lx/%04x\n", 1236 (u_long)idtr.base, (u_int)idtr.limit); 1237 __asm __volatile("sgdt %0" : "=m" (gdtr)); 1238 db_printf("gdtr\t0x%016lx/%04x\n", 1239 (u_long)gdtr.base, (u_int)gdtr.limit); 1240 __asm __volatile("sldt %0" : "=r" (ldt)); 1241 db_printf("ldtr\t0x%04x\n", ldt); 1242 __asm __volatile("str %0" : "=r" (tr)); 1243 db_printf("tr\t0x%04x\n", tr); 1244 db_printf("cr0\t0x%016lx\n", rcr0()); 1245 db_printf("cr2\t0x%016lx\n", rcr2()); 1246 db_printf("cr3\t0x%016lx\n", rcr3()); 1247 db_printf("cr4\t0x%016lx\n", rcr4()); 1248 db_printf("EFER\t%016lx\n", rdmsr(MSR_EFER)); 1249 db_printf("FEATURES_CTL\t%016lx\n", rdmsr(MSR_IA32_FEATURE_CONTROL)); 1250 db_printf("DEBUG_CTL\t%016lx\n", rdmsr(MSR_DEBUGCTLMSR)); 1251 db_printf("PAT\t%016lx\n", rdmsr(MSR_PAT)); 1252 db_printf("GSBASE\t%016lx\n", rdmsr(MSR_GSBASE)); 1253} 1254#endif 1255 1256void 1257sdtossd(sd, ssd) 1258 struct user_segment_descriptor *sd; 1259 struct soft_segment_descriptor *ssd; 1260{ 1261 1262 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1263 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1264 ssd->ssd_type = sd->sd_type; 1265 ssd->ssd_dpl = sd->sd_dpl; 1266 ssd->ssd_p = sd->sd_p; 1267 ssd->ssd_long = sd->sd_long; 1268 ssd->ssd_def32 = sd->sd_def32; 1269 ssd->ssd_gran = sd->sd_gran; 1270} 1271 1272void 1273ssdtosd(ssd, sd) 1274 struct soft_segment_descriptor *ssd; 1275 struct user_segment_descriptor *sd; 1276{ 1277 1278 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1279 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1280 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1281 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1282 sd->sd_type = ssd->ssd_type; 1283 sd->sd_dpl = ssd->ssd_dpl; 1284 sd->sd_p = ssd->ssd_p; 1285 sd->sd_long = ssd->ssd_long; 1286 sd->sd_def32 = ssd->ssd_def32; 1287 sd->sd_gran = ssd->ssd_gran; 1288} 1289 1290void 1291ssdtosyssd(ssd, sd) 1292 struct soft_segment_descriptor *ssd; 1293 struct system_segment_descriptor *sd; 1294{ 1295 1296 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1297 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1298 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1299 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1300 sd->sd_type = ssd->ssd_type; 1301 sd->sd_dpl = ssd->ssd_dpl; 1302 sd->sd_p = ssd->ssd_p; 1303 sd->sd_gran = ssd->ssd_gran; 1304} 1305 1306#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1307#include <isa/isavar.h> 1308#include <isa/isareg.h> 1309/* 1310 * Return a bitmap of the current interrupt requests. This is 8259-specific 1311 * and is only suitable for use at probe time. 1312 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1313 * It shouldn't be here. There should probably be an APIC centric 1314 * implementation in the apic driver code, if at all. 1315 */ 1316intrmask_t 1317isa_irq_pending(void) 1318{ 1319 u_char irr1; 1320 u_char irr2; 1321 1322 irr1 = inb(IO_ICU1); 1323 irr2 = inb(IO_ICU2); 1324 return ((irr2 << 8) | irr1); 1325} 1326#endif 1327 1328u_int basemem; 1329 1330static int 1331add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp) 1332{ 1333 int i, insert_idx, physmap_idx; 1334 1335 physmap_idx = *physmap_idxp; 1336 1337 if (boothowto & RB_VERBOSE) 1338 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1339 smap->type, smap->base, smap->length); 1340 1341 if (smap->type != SMAP_TYPE_MEMORY) 1342 return (1); 1343 1344 if (smap->length == 0) 1345 return (0); 1346 1347 /* 1348 * Find insertion point while checking for overlap. Start off by 1349 * assuming the new entry will be added to the end. 1350 */ 1351 insert_idx = physmap_idx + 2; 1352 for (i = 0; i <= physmap_idx; i += 2) { 1353 if (smap->base < physmap[i + 1]) { 1354 if (smap->base + smap->length <= physmap[i]) { 1355 insert_idx = i; 1356 break; 1357 } 1358 if (boothowto & RB_VERBOSE) 1359 printf( 1360 "Overlapping memory regions, ignoring second region\n"); 1361 return (1); 1362 } 1363 } 1364 1365 /* See if we can prepend to the next entry. */ 1366 if (insert_idx <= physmap_idx && 1367 smap->base + smap->length == physmap[insert_idx]) { 1368 physmap[insert_idx] = smap->base; 1369 return (1); 1370 } 1371 1372 /* See if we can append to the previous entry. */ 1373 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) { 1374 physmap[insert_idx - 1] += smap->length; 1375 return (1); 1376 } 1377 1378 physmap_idx += 2; 1379 *physmap_idxp = physmap_idx; 1380 if (physmap_idx == PHYSMAP_SIZE) { 1381 printf( 1382 "Too many segments in the physical address map, giving up\n"); 1383 return (0); 1384 } 1385 1386 /* 1387 * Move the last 'N' entries down to make room for the new 1388 * entry if needed. 1389 */ 1390 for (i = physmap_idx; i > insert_idx; i -= 2) { 1391 physmap[i] = physmap[i - 2]; 1392 physmap[i + 1] = physmap[i - 1]; 1393 } 1394 1395 /* Insert the new entry. */ 1396 physmap[insert_idx] = smap->base; 1397 physmap[insert_idx + 1] = smap->base + smap->length; 1398 return (1); 1399} 1400 1401/* 1402 * Populate the (physmap) array with base/bound pairs describing the 1403 * available physical memory in the system, then test this memory and 1404 * build the phys_avail array describing the actually-available memory. 1405 * 1406 * Total memory size may be set by the kernel environment variable 1407 * hw.physmem or the compile-time define MAXMEM. 1408 * 1409 * XXX first should be vm_paddr_t. 1410 */ 1411static void 1412getmemsize(caddr_t kmdp, u_int64_t first) 1413{ 1414 int i, physmap_idx, pa_indx, da_indx; 1415 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1416 u_long physmem_start, physmem_tunable, memtest; 1417 pt_entry_t *pte; 1418 struct bios_smap *smapbase, *smap, *smapend; 1419 u_int32_t smapsize; 1420 quad_t dcons_addr, dcons_size; 1421 1422 bzero(physmap, sizeof(physmap)); 1423 basemem = 0; 1424 physmap_idx = 0; 1425 1426 /* 1427 * get memory map from INT 15:E820, kindly supplied by the loader. 1428 * 1429 * subr_module.c says: 1430 * "Consumer may safely assume that size value precedes data." 1431 * ie: an int32_t immediately precedes smap. 1432 */ 1433 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1434 MODINFO_METADATA | MODINFOMD_SMAP); 1435 if (smapbase == NULL) 1436 panic("No BIOS smap info from loader!"); 1437 1438 smapsize = *((u_int32_t *)smapbase - 1); 1439 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1440 1441 for (smap = smapbase; smap < smapend; smap++) 1442 if (!add_smap_entry(smap, physmap, &physmap_idx)) 1443 break; 1444 1445 /* 1446 * Find the 'base memory' segment for SMP 1447 */ 1448 basemem = 0; 1449 for (i = 0; i <= physmap_idx; i += 2) { 1450 if (physmap[i] == 0x00000000) { 1451 basemem = physmap[i + 1] / 1024; 1452 break; 1453 } 1454 } 1455 if (basemem == 0) 1456 panic("BIOS smap did not include a basemem segment!"); 1457 1458#ifdef SMP 1459 /* make hole for AP bootstrap code */ 1460 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1461#endif 1462 1463 /* 1464 * Maxmem isn't the "maximum memory", it's one larger than the 1465 * highest page of the physical address space. It should be 1466 * called something like "Maxphyspage". We may adjust this 1467 * based on ``hw.physmem'' and the results of the memory test. 1468 */ 1469 Maxmem = atop(physmap[physmap_idx + 1]); 1470 1471#ifdef MAXMEM 1472 Maxmem = MAXMEM / 4; 1473#endif 1474 1475 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1476 Maxmem = atop(physmem_tunable); 1477 1478 /* 1479 * By default enable the memory test on real hardware, and disable 1480 * it if we appear to be running in a VM. This avoids touching all 1481 * pages unnecessarily, which doesn't matter on real hardware but is 1482 * bad for shared VM hosts. Use a general name so that 1483 * one could eventually do more with the code than just disable it. 1484 */ 1485 memtest = (vm_guest > VM_GUEST_NO) ? 0 : 1; 1486 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1487 1488 /* 1489 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1490 * in the system. 1491 */ 1492 if (Maxmem > atop(physmap[physmap_idx + 1])) 1493 Maxmem = atop(physmap[physmap_idx + 1]); 1494 1495 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1496 (boothowto & RB_VERBOSE)) 1497 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1498 1499 /* call pmap initialization to make new kernel address space */ 1500 pmap_bootstrap(&first); 1501 1502 /* 1503 * Size up each available chunk of physical memory. 1504 * 1505 * XXX Some BIOSes corrupt low 64KB between suspend and resume. 1506 * By default, mask off the first 16 pages unless we appear to be 1507 * running in a VM. 1508 */ 1509 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT; 1510 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start); 1511 if (physmem_start < PAGE_SIZE) 1512 physmap[0] = PAGE_SIZE; 1513 else if (physmem_start >= physmap[1]) 1514 physmap[0] = round_page(physmap[1] - PAGE_SIZE); 1515 else 1516 physmap[0] = round_page(physmem_start); 1517 pa_indx = 0; 1518 da_indx = 1; 1519 phys_avail[pa_indx++] = physmap[0]; 1520 phys_avail[pa_indx] = physmap[0]; 1521 dump_avail[da_indx] = physmap[0]; 1522 pte = CMAP1; 1523 1524 /* 1525 * Get dcons buffer address 1526 */ 1527 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1528 getenv_quad("dcons.size", &dcons_size) == 0) 1529 dcons_addr = 0; 1530 1531 /* 1532 * physmap is in bytes, so when converting to page boundaries, 1533 * round up the start address and round down the end address. 1534 */ 1535 for (i = 0; i <= physmap_idx; i += 2) { 1536 vm_paddr_t end; 1537 1538 end = ptoa((vm_paddr_t)Maxmem); 1539 if (physmap[i + 1] < end) 1540 end = trunc_page(physmap[i + 1]); 1541 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1542 int tmp, page_bad, full; 1543 int *ptr = (int *)CADDR1; 1544 1545 full = FALSE; 1546 /* 1547 * block out kernel memory as not available. 1548 */ 1549 if (pa >= (vm_paddr_t)kernphys && pa < first) 1550 goto do_dump_avail; 1551 1552 /* 1553 * block out dcons buffer 1554 */ 1555 if (dcons_addr > 0 1556 && pa >= trunc_page(dcons_addr) 1557 && pa < dcons_addr + dcons_size) 1558 goto do_dump_avail; 1559 1560 page_bad = FALSE; 1561 if (memtest == 0) 1562 goto skip_memtest; 1563 1564 /* 1565 * map page into kernel: valid, read/write,non-cacheable 1566 */ 1567 *pte = pa | PG_V | PG_RW | PG_NC_PWT | PG_NC_PCD; 1568 invltlb(); 1569 1570 tmp = *(int *)ptr; 1571 /* 1572 * Test for alternating 1's and 0's 1573 */ 1574 *(volatile int *)ptr = 0xaaaaaaaa; 1575 if (*(volatile int *)ptr != 0xaaaaaaaa) 1576 page_bad = TRUE; 1577 /* 1578 * Test for alternating 0's and 1's 1579 */ 1580 *(volatile int *)ptr = 0x55555555; 1581 if (*(volatile int *)ptr != 0x55555555) 1582 page_bad = TRUE; 1583 /* 1584 * Test for all 1's 1585 */ 1586 *(volatile int *)ptr = 0xffffffff; 1587 if (*(volatile int *)ptr != 0xffffffff) 1588 page_bad = TRUE; 1589 /* 1590 * Test for all 0's 1591 */ 1592 *(volatile int *)ptr = 0x0; 1593 if (*(volatile int *)ptr != 0x0) 1594 page_bad = TRUE; 1595 /* 1596 * Restore original value. 1597 */ 1598 *(int *)ptr = tmp; 1599 1600skip_memtest: 1601 /* 1602 * Adjust array of valid/good pages. 1603 */ 1604 if (page_bad == TRUE) 1605 continue; 1606 /* 1607 * If this good page is a continuation of the 1608 * previous set of good pages, then just increase 1609 * the end pointer. Otherwise start a new chunk. 1610 * Note that "end" points one higher than end, 1611 * making the range >= start and < end. 1612 * If we're also doing a speculative memory 1613 * test and we at or past the end, bump up Maxmem 1614 * so that we keep going. The first bad page 1615 * will terminate the loop. 1616 */ 1617 if (phys_avail[pa_indx] == pa) { 1618 phys_avail[pa_indx] += PAGE_SIZE; 1619 } else { 1620 pa_indx++; 1621 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1622 printf( 1623 "Too many holes in the physical address space, giving up\n"); 1624 pa_indx--; 1625 full = TRUE; 1626 goto do_dump_avail; 1627 } 1628 phys_avail[pa_indx++] = pa; /* start */ 1629 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1630 } 1631 physmem++; 1632do_dump_avail: 1633 if (dump_avail[da_indx] == pa) { 1634 dump_avail[da_indx] += PAGE_SIZE; 1635 } else { 1636 da_indx++; 1637 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1638 da_indx--; 1639 goto do_next; 1640 } 1641 dump_avail[da_indx++] = pa; /* start */ 1642 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1643 } 1644do_next: 1645 if (full) 1646 break; 1647 } 1648 } 1649 *pte = 0; 1650 invltlb(); 1651 1652 /* 1653 * XXX 1654 * The last chunk must contain at least one page plus the message 1655 * buffer to avoid complicating other code (message buffer address 1656 * calculation, etc.). 1657 */ 1658 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1659 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1660 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1661 phys_avail[pa_indx--] = 0; 1662 phys_avail[pa_indx--] = 0; 1663 } 1664 1665 Maxmem = atop(phys_avail[pa_indx]); 1666 1667 /* Trim off space for the message buffer. */ 1668 phys_avail[pa_indx] -= round_page(msgbufsize); 1669 1670 /* Map the message buffer. */ 1671 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1672} 1673 1674u_int64_t 1675hammer_time(u_int64_t modulep, u_int64_t physfree) 1676{ 1677 caddr_t kmdp; 1678 int gsel_tss, x; 1679 struct pcpu *pc; 1680 struct nmi_pcpu *np; 1681 struct xstate_hdr *xhdr; 1682 u_int64_t msr; 1683 char *env; 1684 size_t kstack0_sz; 1685 1686 thread0.td_kstack = physfree + KERNBASE; 1687 thread0.td_kstack_pages = KSTACK_PAGES; 1688 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1689 bzero((void *)thread0.td_kstack, kstack0_sz); 1690 physfree += kstack0_sz; 1691 1692 /* 1693 * This may be done better later if it gets more high level 1694 * components in it. If so just link td->td_proc here. 1695 */ 1696 proc_linkup0(&proc0, &thread0); 1697 1698 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1699 preload_bootstrap_relocate(KERNBASE); 1700 kmdp = preload_search_by_type("elf kernel"); 1701 if (kmdp == NULL) 1702 kmdp = preload_search_by_type("elf64 kernel"); 1703 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1704 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1705#ifdef DDB 1706 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1707 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1708#endif 1709 1710 /* Init basic tunables, hz etc */ 1711 init_param1(); 1712 1713 /* 1714 * make gdt memory segments 1715 */ 1716 for (x = 0; x < NGDT; x++) { 1717 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1718 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1719 ssdtosd(&gdt_segs[x], &gdt[x]); 1720 } 1721 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1722 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1723 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1724 1725 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1726 r_gdt.rd_base = (long) gdt; 1727 lgdt(&r_gdt); 1728 pc = &__pcpu[0]; 1729 1730 wrmsr(MSR_FSBASE, 0); /* User value */ 1731 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1732 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1733 1734 pcpu_init(pc, 0, sizeof(struct pcpu)); 1735 dpcpu_init((void *)(physfree + KERNBASE), 0); 1736 physfree += DPCPU_SIZE; 1737 PCPU_SET(prvspace, pc); 1738 PCPU_SET(curthread, &thread0); 1739 PCPU_SET(tssp, &common_tss[0]); 1740 PCPU_SET(commontssp, &common_tss[0]); 1741 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1742 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1743 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1744 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1745 1746 /* 1747 * Initialize mutexes. 1748 * 1749 * icu_lock: in order to allow an interrupt to occur in a critical 1750 * section, to set pcpu->ipending (etc...) properly, we 1751 * must be able to get the icu lock, so it can't be 1752 * under witness. 1753 */ 1754 mutex_init(); 1755 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1756 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1757 1758 /* exceptions */ 1759 for (x = 0; x < NIDT; x++) 1760 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1761 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1762 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1763 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1764 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1765 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1766 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1767 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1768 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1769 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1770 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1771 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1772 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1773 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1774 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1775 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1776 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1777 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1778 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1779 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1780#ifdef KDTRACE_HOOKS 1781 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1782#endif 1783#ifdef XENHVM 1784 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall), SDT_SYSIGT, SEL_UPL, 0); 1785#endif 1786 1787 r_idt.rd_limit = sizeof(idt0) - 1; 1788 r_idt.rd_base = (long) idt; 1789 lidt(&r_idt); 1790 1791 /* 1792 * Initialize the i8254 before the console so that console 1793 * initialization can use DELAY(). 1794 */ 1795 i8254_init(); 1796 1797 /* 1798 * Initialize the console before we print anything out. 1799 */ 1800 cninit(); 1801 1802#ifdef DEV_ISA 1803#ifdef DEV_ATPIC 1804 elcr_probe(); 1805 atpic_startup(); 1806#else 1807 /* Reset and mask the atpics and leave them shut down. */ 1808 atpic_reset(); 1809 1810 /* 1811 * Point the ICU spurious interrupt vectors at the APIC spurious 1812 * interrupt handler. 1813 */ 1814 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1815 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1816#endif 1817#else 1818#error "have you forgotten the isa device?"; 1819#endif 1820 1821 kdb_init(); 1822 1823#ifdef KDB 1824 if (boothowto & RB_KDB) 1825 kdb_enter(KDB_WHY_BOOTFLAGS, 1826 "Boot flags requested debugger"); 1827#endif 1828 1829 identify_cpu(); /* Final stage of CPU initialization */ 1830 initializecpu(); /* Initialize CPU registers */ 1831 initializecpucache(); 1832 1833 /* doublefault stack space, runs on ist1 */ 1834 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1835 1836 /* 1837 * NMI stack, runs on ist2. The pcpu pointer is stored just 1838 * above the start of the ist2 stack. 1839 */ 1840 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1841 np->np_pcpu = (register_t) pc; 1842 common_tss[0].tss_ist2 = (long) np; 1843 1844 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1845 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1846 IOPAGES * PAGE_SIZE; 1847 1848 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1849 ltr(gsel_tss); 1850 1851 /* Set up the fast syscall stuff */ 1852 msr = rdmsr(MSR_EFER) | EFER_SCE; 1853 wrmsr(MSR_EFER, msr); 1854 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1855 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1856 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1857 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1858 wrmsr(MSR_STAR, msr); 1859 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1860 1861 getmemsize(kmdp, physfree); 1862 init_param2(physmem); 1863 1864 /* now running on new page tables, configured,and u/iom is accessible */ 1865 1866 msgbufinit(msgbufp, msgbufsize); 1867 fpuinit(); 1868 1869 /* 1870 * Set up thread0 pcb after fpuinit calculated pcb + fpu save 1871 * area size. Zero out the extended state header in fpu save 1872 * area. 1873 */ 1874 thread0.td_pcb = get_pcb_td(&thread0); 1875 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size); 1876 if (use_xsave) { 1877 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) + 1878 1); 1879 xhdr->xstate_bv = xsave_mask; 1880 } 1881 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1882 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb; 1883 /* Ensure the stack is aligned to 16 bytes */ 1884 common_tss[0].tss_rsp0 &= ~0xFul; 1885 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1886 PCPU_SET(curpcb, thread0.td_pcb); 1887 1888 /* transfer to user mode */ 1889 1890 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1891 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1892 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1893 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1894 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1895 1896 load_ds(_udatasel); 1897 load_es(_udatasel); 1898 load_fs(_ufssel); 1899 1900 /* setup proc 0's pcb */ 1901 thread0.td_pcb->pcb_flags = 0; 1902 thread0.td_pcb->pcb_cr3 = KPML4phys; /* PCID 0 is reserved for kernel */ 1903 thread0.td_frame = &proc0_tf; 1904 1905 env = getenv("kernelname"); 1906 if (env != NULL) 1907 strlcpy(kernelname, env, sizeof(kernelname)); 1908 1909 cpu_probe_amdc1e(); 1910 1911#ifdef FDT 1912 x86_init_fdt(); 1913#endif 1914 1915 /* Location of kernel stack for locore */ 1916 return ((u_int64_t)thread0.td_pcb); 1917} 1918 1919void 1920cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1921{ 1922 1923 pcpu->pc_acpi_id = 0xffffffff; 1924} 1925 1926void 1927spinlock_enter(void) 1928{ 1929 struct thread *td; 1930 register_t flags; 1931 1932 td = curthread; 1933 if (td->td_md.md_spinlock_count == 0) { 1934 flags = intr_disable(); 1935 td->td_md.md_spinlock_count = 1; 1936 td->td_md.md_saved_flags = flags; 1937 } else 1938 td->td_md.md_spinlock_count++; 1939 critical_enter(); 1940} 1941 1942void 1943spinlock_exit(void) 1944{ 1945 struct thread *td; 1946 register_t flags; 1947 1948 td = curthread; 1949 critical_exit(); 1950 flags = td->td_md.md_saved_flags; 1951 td->td_md.md_spinlock_count--; 1952 if (td->td_md.md_spinlock_count == 0) 1953 intr_restore(flags); 1954} 1955 1956/* 1957 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1958 * we want to start a backtrace from the function that caused us to enter 1959 * the debugger. We have the context in the trapframe, but base the trace 1960 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1961 * enough for a backtrace. 1962 */ 1963void 1964makectx(struct trapframe *tf, struct pcb *pcb) 1965{ 1966 1967 pcb->pcb_r12 = tf->tf_r12; 1968 pcb->pcb_r13 = tf->tf_r13; 1969 pcb->pcb_r14 = tf->tf_r14; 1970 pcb->pcb_r15 = tf->tf_r15; 1971 pcb->pcb_rbp = tf->tf_rbp; 1972 pcb->pcb_rbx = tf->tf_rbx; 1973 pcb->pcb_rip = tf->tf_rip; 1974 pcb->pcb_rsp = tf->tf_rsp; 1975} 1976 1977int 1978ptrace_set_pc(struct thread *td, unsigned long addr) 1979{ 1980 td->td_frame->tf_rip = addr; 1981 return (0); 1982} 1983 1984int 1985ptrace_single_step(struct thread *td) 1986{ 1987 td->td_frame->tf_rflags |= PSL_T; 1988 return (0); 1989} 1990 1991int 1992ptrace_clear_single_step(struct thread *td) 1993{ 1994 td->td_frame->tf_rflags &= ~PSL_T; 1995 return (0); 1996} 1997 1998int 1999fill_regs(struct thread *td, struct reg *regs) 2000{ 2001 struct trapframe *tp; 2002 2003 tp = td->td_frame; 2004 return (fill_frame_regs(tp, regs)); 2005} 2006 2007int 2008fill_frame_regs(struct trapframe *tp, struct reg *regs) 2009{ 2010 regs->r_r15 = tp->tf_r15; 2011 regs->r_r14 = tp->tf_r14; 2012 regs->r_r13 = tp->tf_r13; 2013 regs->r_r12 = tp->tf_r12; 2014 regs->r_r11 = tp->tf_r11; 2015 regs->r_r10 = tp->tf_r10; 2016 regs->r_r9 = tp->tf_r9; 2017 regs->r_r8 = tp->tf_r8; 2018 regs->r_rdi = tp->tf_rdi; 2019 regs->r_rsi = tp->tf_rsi; 2020 regs->r_rbp = tp->tf_rbp; 2021 regs->r_rbx = tp->tf_rbx; 2022 regs->r_rdx = tp->tf_rdx; 2023 regs->r_rcx = tp->tf_rcx; 2024 regs->r_rax = tp->tf_rax; 2025 regs->r_rip = tp->tf_rip; 2026 regs->r_cs = tp->tf_cs; 2027 regs->r_rflags = tp->tf_rflags; 2028 regs->r_rsp = tp->tf_rsp; 2029 regs->r_ss = tp->tf_ss; 2030 if (tp->tf_flags & TF_HASSEGS) { 2031 regs->r_ds = tp->tf_ds; 2032 regs->r_es = tp->tf_es; 2033 regs->r_fs = tp->tf_fs; 2034 regs->r_gs = tp->tf_gs; 2035 } else { 2036 regs->r_ds = 0; 2037 regs->r_es = 0; 2038 regs->r_fs = 0; 2039 regs->r_gs = 0; 2040 } 2041 return (0); 2042} 2043 2044int 2045set_regs(struct thread *td, struct reg *regs) 2046{ 2047 struct trapframe *tp; 2048 register_t rflags; 2049 2050 tp = td->td_frame; 2051 rflags = regs->r_rflags & 0xffffffff; 2052 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 2053 return (EINVAL); 2054 tp->tf_r15 = regs->r_r15; 2055 tp->tf_r14 = regs->r_r14; 2056 tp->tf_r13 = regs->r_r13; 2057 tp->tf_r12 = regs->r_r12; 2058 tp->tf_r11 = regs->r_r11; 2059 tp->tf_r10 = regs->r_r10; 2060 tp->tf_r9 = regs->r_r9; 2061 tp->tf_r8 = regs->r_r8; 2062 tp->tf_rdi = regs->r_rdi; 2063 tp->tf_rsi = regs->r_rsi; 2064 tp->tf_rbp = regs->r_rbp; 2065 tp->tf_rbx = regs->r_rbx; 2066 tp->tf_rdx = regs->r_rdx; 2067 tp->tf_rcx = regs->r_rcx; 2068 tp->tf_rax = regs->r_rax; 2069 tp->tf_rip = regs->r_rip; 2070 tp->tf_cs = regs->r_cs; 2071 tp->tf_rflags = rflags; 2072 tp->tf_rsp = regs->r_rsp; 2073 tp->tf_ss = regs->r_ss; 2074 if (0) { /* XXXKIB */ 2075 tp->tf_ds = regs->r_ds; 2076 tp->tf_es = regs->r_es; 2077 tp->tf_fs = regs->r_fs; 2078 tp->tf_gs = regs->r_gs; 2079 tp->tf_flags = TF_HASSEGS; 2080 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2081 } 2082 return (0); 2083} 2084 2085/* XXX check all this stuff! */ 2086/* externalize from sv_xmm */ 2087static void 2088fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 2089{ 2090 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2091 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2092 int i; 2093 2094 /* pcb -> fpregs */ 2095 bzero(fpregs, sizeof(*fpregs)); 2096 2097 /* FPU control/status */ 2098 penv_fpreg->en_cw = penv_xmm->en_cw; 2099 penv_fpreg->en_sw = penv_xmm->en_sw; 2100 penv_fpreg->en_tw = penv_xmm->en_tw; 2101 penv_fpreg->en_opcode = penv_xmm->en_opcode; 2102 penv_fpreg->en_rip = penv_xmm->en_rip; 2103 penv_fpreg->en_rdp = penv_xmm->en_rdp; 2104 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 2105 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 2106 2107 /* FPU registers */ 2108 for (i = 0; i < 8; ++i) 2109 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 2110 2111 /* SSE registers */ 2112 for (i = 0; i < 16; ++i) 2113 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 2114} 2115 2116/* internalize from fpregs into sv_xmm */ 2117static void 2118set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 2119{ 2120 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2121 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2122 int i; 2123 2124 /* fpregs -> pcb */ 2125 /* FPU control/status */ 2126 penv_xmm->en_cw = penv_fpreg->en_cw; 2127 penv_xmm->en_sw = penv_fpreg->en_sw; 2128 penv_xmm->en_tw = penv_fpreg->en_tw; 2129 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2130 penv_xmm->en_rip = penv_fpreg->en_rip; 2131 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2132 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2133 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2134 2135 /* FPU registers */ 2136 for (i = 0; i < 8; ++i) 2137 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2138 2139 /* SSE registers */ 2140 for (i = 0; i < 16; ++i) 2141 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2142} 2143 2144/* externalize from td->pcb */ 2145int 2146fill_fpregs(struct thread *td, struct fpreg *fpregs) 2147{ 2148 2149 KASSERT(td == curthread || TD_IS_SUSPENDED(td) || 2150 P_SHOULDSTOP(td->td_proc), 2151 ("not suspended thread %p", td)); 2152 fpugetregs(td); 2153 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs); 2154 return (0); 2155} 2156 2157/* internalize to td->pcb */ 2158int 2159set_fpregs(struct thread *td, struct fpreg *fpregs) 2160{ 2161 2162 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td)); 2163 fpuuserinited(td); 2164 return (0); 2165} 2166 2167/* 2168 * Get machine context. 2169 */ 2170int 2171get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2172{ 2173 struct pcb *pcb; 2174 struct trapframe *tp; 2175 2176 pcb = td->td_pcb; 2177 tp = td->td_frame; 2178 PROC_LOCK(curthread->td_proc); 2179 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2180 PROC_UNLOCK(curthread->td_proc); 2181 mcp->mc_r15 = tp->tf_r15; 2182 mcp->mc_r14 = tp->tf_r14; 2183 mcp->mc_r13 = tp->tf_r13; 2184 mcp->mc_r12 = tp->tf_r12; 2185 mcp->mc_r11 = tp->tf_r11; 2186 mcp->mc_r10 = tp->tf_r10; 2187 mcp->mc_r9 = tp->tf_r9; 2188 mcp->mc_r8 = tp->tf_r8; 2189 mcp->mc_rdi = tp->tf_rdi; 2190 mcp->mc_rsi = tp->tf_rsi; 2191 mcp->mc_rbp = tp->tf_rbp; 2192 mcp->mc_rbx = tp->tf_rbx; 2193 mcp->mc_rcx = tp->tf_rcx; 2194 mcp->mc_rflags = tp->tf_rflags; 2195 if (flags & GET_MC_CLEAR_RET) { 2196 mcp->mc_rax = 0; 2197 mcp->mc_rdx = 0; 2198 mcp->mc_rflags &= ~PSL_C; 2199 } else { 2200 mcp->mc_rax = tp->tf_rax; 2201 mcp->mc_rdx = tp->tf_rdx; 2202 } 2203 mcp->mc_rip = tp->tf_rip; 2204 mcp->mc_cs = tp->tf_cs; 2205 mcp->mc_rsp = tp->tf_rsp; 2206 mcp->mc_ss = tp->tf_ss; 2207 mcp->mc_ds = tp->tf_ds; 2208 mcp->mc_es = tp->tf_es; 2209 mcp->mc_fs = tp->tf_fs; 2210 mcp->mc_gs = tp->tf_gs; 2211 mcp->mc_flags = tp->tf_flags; 2212 mcp->mc_len = sizeof(*mcp); 2213 get_fpcontext(td, mcp, NULL, 0); 2214 mcp->mc_fsbase = pcb->pcb_fsbase; 2215 mcp->mc_gsbase = pcb->pcb_gsbase; 2216 mcp->mc_xfpustate = 0; 2217 mcp->mc_xfpustate_len = 0; 2218 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2219 return (0); 2220} 2221 2222/* 2223 * Set machine context. 2224 * 2225 * However, we don't set any but the user modifiable flags, and we won't 2226 * touch the cs selector. 2227 */ 2228int 2229set_mcontext(struct thread *td, const mcontext_t *mcp) 2230{ 2231 struct pcb *pcb; 2232 struct trapframe *tp; 2233 char *xfpustate; 2234 long rflags; 2235 int ret; 2236 2237 pcb = td->td_pcb; 2238 tp = td->td_frame; 2239 if (mcp->mc_len != sizeof(*mcp) || 2240 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2241 return (EINVAL); 2242 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2243 (tp->tf_rflags & ~PSL_USERCHANGE); 2244 if (mcp->mc_flags & _MC_HASFPXSTATE) { 2245 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size - 2246 sizeof(struct savefpu)) 2247 return (EINVAL); 2248 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len); 2249 ret = copyin((void *)mcp->mc_xfpustate, xfpustate, 2250 mcp->mc_xfpustate_len); 2251 if (ret != 0) 2252 return (ret); 2253 } else 2254 xfpustate = NULL; 2255 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len); 2256 if (ret != 0) 2257 return (ret); 2258 tp->tf_r15 = mcp->mc_r15; 2259 tp->tf_r14 = mcp->mc_r14; 2260 tp->tf_r13 = mcp->mc_r13; 2261 tp->tf_r12 = mcp->mc_r12; 2262 tp->tf_r11 = mcp->mc_r11; 2263 tp->tf_r10 = mcp->mc_r10; 2264 tp->tf_r9 = mcp->mc_r9; 2265 tp->tf_r8 = mcp->mc_r8; 2266 tp->tf_rdi = mcp->mc_rdi; 2267 tp->tf_rsi = mcp->mc_rsi; 2268 tp->tf_rbp = mcp->mc_rbp; 2269 tp->tf_rbx = mcp->mc_rbx; 2270 tp->tf_rdx = mcp->mc_rdx; 2271 tp->tf_rcx = mcp->mc_rcx; 2272 tp->tf_rax = mcp->mc_rax; 2273 tp->tf_rip = mcp->mc_rip; 2274 tp->tf_rflags = rflags; 2275 tp->tf_rsp = mcp->mc_rsp; 2276 tp->tf_ss = mcp->mc_ss; 2277 tp->tf_flags = mcp->mc_flags; 2278 if (tp->tf_flags & TF_HASSEGS) { 2279 tp->tf_ds = mcp->mc_ds; 2280 tp->tf_es = mcp->mc_es; 2281 tp->tf_fs = mcp->mc_fs; 2282 tp->tf_gs = mcp->mc_gs; 2283 } 2284 if (mcp->mc_flags & _MC_HASBASES) { 2285 pcb->pcb_fsbase = mcp->mc_fsbase; 2286 pcb->pcb_gsbase = mcp->mc_gsbase; 2287 } 2288 set_pcb_flags(pcb, PCB_FULL_IRET); 2289 return (0); 2290} 2291 2292static void 2293get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave, 2294 size_t xfpusave_len) 2295{ 2296 size_t max_len, len; 2297 2298 mcp->mc_ownedfp = fpugetregs(td); 2299 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0], 2300 sizeof(mcp->mc_fpstate)); 2301 mcp->mc_fpformat = fpuformat(); 2302 if (!use_xsave || xfpusave_len == 0) 2303 return; 2304 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 2305 len = xfpusave_len; 2306 if (len > max_len) { 2307 len = max_len; 2308 bzero(xfpusave + max_len, len - max_len); 2309 } 2310 mcp->mc_flags |= _MC_HASFPXSTATE; 2311 mcp->mc_xfpustate_len = len; 2312 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len); 2313} 2314 2315static int 2316set_fpcontext(struct thread *td, const mcontext_t *mcp, char *xfpustate, 2317 size_t xfpustate_len) 2318{ 2319 struct savefpu *fpstate; 2320 int error; 2321 2322 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2323 return (0); 2324 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2325 return (EINVAL); 2326 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) { 2327 /* We don't care what state is left in the FPU or PCB. */ 2328 fpstate_drop(td); 2329 error = 0; 2330 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2331 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2332 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2333 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2334 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len); 2335 } else 2336 return (EINVAL); 2337 return (error); 2338} 2339 2340void 2341fpstate_drop(struct thread *td) 2342{ 2343 2344 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2345 critical_enter(); 2346 if (PCPU_GET(fpcurthread) == td) 2347 fpudrop(); 2348 /* 2349 * XXX force a full drop of the fpu. The above only drops it if we 2350 * owned it. 2351 * 2352 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2353 * drop. Dropping only to the pcb matches fnsave's behaviour. 2354 * We only need to drop to !PCB_INITDONE in sendsig(). But 2355 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2356 * have too many layers. 2357 */ 2358 clear_pcb_flags(curthread->td_pcb, 2359 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2360 critical_exit(); 2361} 2362 2363int 2364fill_dbregs(struct thread *td, struct dbreg *dbregs) 2365{ 2366 struct pcb *pcb; 2367 2368 if (td == NULL) { 2369 dbregs->dr[0] = rdr0(); 2370 dbregs->dr[1] = rdr1(); 2371 dbregs->dr[2] = rdr2(); 2372 dbregs->dr[3] = rdr3(); 2373 dbregs->dr[6] = rdr6(); 2374 dbregs->dr[7] = rdr7(); 2375 } else { 2376 pcb = td->td_pcb; 2377 dbregs->dr[0] = pcb->pcb_dr0; 2378 dbregs->dr[1] = pcb->pcb_dr1; 2379 dbregs->dr[2] = pcb->pcb_dr2; 2380 dbregs->dr[3] = pcb->pcb_dr3; 2381 dbregs->dr[6] = pcb->pcb_dr6; 2382 dbregs->dr[7] = pcb->pcb_dr7; 2383 } 2384 dbregs->dr[4] = 0; 2385 dbregs->dr[5] = 0; 2386 dbregs->dr[8] = 0; 2387 dbregs->dr[9] = 0; 2388 dbregs->dr[10] = 0; 2389 dbregs->dr[11] = 0; 2390 dbregs->dr[12] = 0; 2391 dbregs->dr[13] = 0; 2392 dbregs->dr[14] = 0; 2393 dbregs->dr[15] = 0; 2394 return (0); 2395} 2396 2397int 2398set_dbregs(struct thread *td, struct dbreg *dbregs) 2399{ 2400 struct pcb *pcb; 2401 int i; 2402 2403 if (td == NULL) { 2404 load_dr0(dbregs->dr[0]); 2405 load_dr1(dbregs->dr[1]); 2406 load_dr2(dbregs->dr[2]); 2407 load_dr3(dbregs->dr[3]); 2408 load_dr6(dbregs->dr[6]); 2409 load_dr7(dbregs->dr[7]); 2410 } else { 2411 /* 2412 * Don't let an illegal value for dr7 get set. Specifically, 2413 * check for undefined settings. Setting these bit patterns 2414 * result in undefined behaviour and can lead to an unexpected 2415 * TRCTRAP or a general protection fault right here. 2416 * Upper bits of dr6 and dr7 must not be set 2417 */ 2418 for (i = 0; i < 4; i++) { 2419 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2420 return (EINVAL); 2421 if (td->td_frame->tf_cs == _ucode32sel && 2422 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2423 return (EINVAL); 2424 } 2425 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2426 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2427 return (EINVAL); 2428 2429 pcb = td->td_pcb; 2430 2431 /* 2432 * Don't let a process set a breakpoint that is not within the 2433 * process's address space. If a process could do this, it 2434 * could halt the system by setting a breakpoint in the kernel 2435 * (if ddb was enabled). Thus, we need to check to make sure 2436 * that no breakpoints are being enabled for addresses outside 2437 * process's address space. 2438 * 2439 * XXX - what about when the watched area of the user's 2440 * address space is written into from within the kernel 2441 * ... wouldn't that still cause a breakpoint to be generated 2442 * from within kernel mode? 2443 */ 2444 2445 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2446 /* dr0 is enabled */ 2447 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2448 return (EINVAL); 2449 } 2450 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2451 /* dr1 is enabled */ 2452 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2453 return (EINVAL); 2454 } 2455 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2456 /* dr2 is enabled */ 2457 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2458 return (EINVAL); 2459 } 2460 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2461 /* dr3 is enabled */ 2462 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2463 return (EINVAL); 2464 } 2465 2466 pcb->pcb_dr0 = dbregs->dr[0]; 2467 pcb->pcb_dr1 = dbregs->dr[1]; 2468 pcb->pcb_dr2 = dbregs->dr[2]; 2469 pcb->pcb_dr3 = dbregs->dr[3]; 2470 pcb->pcb_dr6 = dbregs->dr[6]; 2471 pcb->pcb_dr7 = dbregs->dr[7]; 2472 2473 set_pcb_flags(pcb, PCB_DBREGS); 2474 } 2475 2476 return (0); 2477} 2478 2479void 2480reset_dbregs(void) 2481{ 2482 2483 load_dr7(0); /* Turn off the control bits first */ 2484 load_dr0(0); 2485 load_dr1(0); 2486 load_dr2(0); 2487 load_dr3(0); 2488 load_dr6(0); 2489} 2490 2491/* 2492 * Return > 0 if a hardware breakpoint has been hit, and the 2493 * breakpoint was in user space. Return 0, otherwise. 2494 */ 2495int 2496user_dbreg_trap(void) 2497{ 2498 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2499 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2500 int nbp; /* number of breakpoints that triggered */ 2501 caddr_t addr[4]; /* breakpoint addresses */ 2502 int i; 2503 2504 dr7 = rdr7(); 2505 if ((dr7 & 0x000000ff) == 0) { 2506 /* 2507 * all GE and LE bits in the dr7 register are zero, 2508 * thus the trap couldn't have been caused by the 2509 * hardware debug registers 2510 */ 2511 return 0; 2512 } 2513 2514 nbp = 0; 2515 dr6 = rdr6(); 2516 bp = dr6 & 0x0000000f; 2517 2518 if (!bp) { 2519 /* 2520 * None of the breakpoint bits are set meaning this 2521 * trap was not caused by any of the debug registers 2522 */ 2523 return 0; 2524 } 2525 2526 /* 2527 * at least one of the breakpoints were hit, check to see 2528 * which ones and if any of them are user space addresses 2529 */ 2530 2531 if (bp & 0x01) { 2532 addr[nbp++] = (caddr_t)rdr0(); 2533 } 2534 if (bp & 0x02) { 2535 addr[nbp++] = (caddr_t)rdr1(); 2536 } 2537 if (bp & 0x04) { 2538 addr[nbp++] = (caddr_t)rdr2(); 2539 } 2540 if (bp & 0x08) { 2541 addr[nbp++] = (caddr_t)rdr3(); 2542 } 2543 2544 for (i = 0; i < nbp; i++) { 2545 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2546 /* 2547 * addr[i] is in user space 2548 */ 2549 return nbp; 2550 } 2551 } 2552 2553 /* 2554 * None of the breakpoints are in user space. 2555 */ 2556 return 0; 2557} 2558 2559#ifdef KDB 2560 2561/* 2562 * Provide inb() and outb() as functions. They are normally only available as 2563 * inline functions, thus cannot be called from the debugger. 2564 */ 2565 2566/* silence compiler warnings */ 2567u_char inb_(u_short); 2568void outb_(u_short, u_char); 2569 2570u_char 2571inb_(u_short port) 2572{ 2573 return inb(port); 2574} 2575 2576void 2577outb_(u_short port, u_char data) 2578{ 2579 outb(port, data); 2580} 2581 2582#endif /* KDB */ 2583