t4_chip_type.h revision 319255 
1/*
2 * This file is part of the Chelsio T4/T5/T6 Ethernet driver.
3 *
4 * Copyright (C) 2003-2016 Chelsio Communications.  All rights reserved.
5 *
6 * This program is distributed in the hope that it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
9 * release for licensing terms and conditions.
10 */
11#ifndef __T4_CHIP_TYPE_H__
12#define __T4_CHIP_TYPE_H__
13
14/*
15 * All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
16 *
17 *   V  = "4" for T4; "5" for T5, etc. or
18 *      = "a" for T4 FPGA; "b" for T4 FPGA, etc.
19 *   F  = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
20 *   PP = adapter product designation
21 *
22 * We use the "version" (V) of the adpater to code the Chip Version above
23 * but separate out the FPGA as a separate boolean as per above.
24 */
25#define CHELSIO_PCI_ID_VER(__DeviceID)	((__DeviceID) >> 12)
26#define CHELSIO_PCI_ID_FUNC(__DeviceID)	(((__DeviceID) >> 8) & 0xf)
27#define CHELSIO_PCI_ID_PROD(__DeviceID)	((__DeviceID) & 0xff)
28
29#define CHELSIO_T4		0x4
30#define CHELSIO_T4_FPGA		0xa
31#define CHELSIO_T5		0x5
32#define CHELSIO_T5_FPGA		0xb
33#define CHELSIO_T6		0x6
34#define CHELSIO_T6_FPGA		0xc
35
36/*
37 * Translate a PCI Device ID to a base Chelsio Chip Version -- CHELSIO_T4,
38 * CHELSIO_T5, etc.  If it weren't for the screwed up numbering of the FPGAs
39 * we could do this simply as DeviceID >> 12 (because we know the real
40 * encoding oc CHELSIO_Tx identifiers).  However, the FPGAs _do_ have weird
41 * Device IDs so we need to do this translation here.  Note that only constant
42 * arithmetic and comparisons can be done here since this is being used to
43 * initialize static tables, etc.
44 *
45 * Finally: This will of course need to be expanded as future chips are
46 * developed.
47 */
48static inline unsigned int
49CHELSIO_PCI_ID_CHIP_VERSION(unsigned int DeviceID)
50{
51	switch (CHELSIO_PCI_ID_VER(DeviceID)) {
52	case CHELSIO_T4:
53	case CHELSIO_T4_FPGA:
54	return CHELSIO_T4;
55
56	case CHELSIO_T5:
57	case CHELSIO_T5_FPGA:
58	return CHELSIO_T5;
59
60	case CHELSIO_T6:
61	case CHELSIO_T6_FPGA:
62	return CHELSIO_T6;
63	}
64
65	return 0;
66}
67
68/*
69 * Internally we code the Chelsio T4 Family "Chip Code" as a tuple:
70 *
71 *     (Is FPGA, Chip Version, Chip Revision)
72 *
73 * where:
74 *
75 *     Is FPGA: is 0/1 indicating whether we're working with an FPGA
76 *     Chip Version: is T4, T5, etc.
77 *     Chip Revision: is the FAB "spin" of the Chip Version.
78 */
79#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
80#define CHELSIO_CHIP_FPGA          0x100
81#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
82#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
83
84enum chip_type {
85	T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
86	T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
87	T4_FIRST_REV	= T4_A1,
88	T4_LAST_REV	= T4_A2,
89
90	T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
91	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
92	T5_FIRST_REV	= T5_A0,
93	T5_LAST_REV	= T5_A1,
94
95	T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
96	T6_FIRST_REV	= T6_A0,
97	T6_LAST_REV	= T6_A0,
98};
99
100static inline int is_t4(enum chip_type chip)
101{
102	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4);
103}
104
105static inline int is_t5(enum chip_type chip)
106{
107
108	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
109}
110
111static inline int is_t6(enum chip_type chip)
112{
113	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
114}
115
116static inline int is_fpga(enum chip_type chip)
117{
118	 return chip & CHELSIO_CHIP_FPGA;
119}
120
121#endif /* __T4_CHIP_TYPE_H__ */
122