t4.h revision 309378 
1/*
2 * Copyright (c) 2006-2014 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *      - Redistributions in binary form must reproduce the above
18 *        copyright notice, this list of conditions and the following
19 *        disclaimer in the documentation and/or other materials
20 *        provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31#ifndef __T4_H__
32#define __T4_H__
33
34#include <stdint.h>
35#include <assert.h>
36#include <syslog.h>
37
38#define ENODATA 95
39#undef  ELAST
40#define ELAST ENODATA
41
42/*
43 * Try and minimize the changes from the kernel code that is pull in
44 * here for kernel bypass ops.
45 */
46#define __u8 uint8_t
47#define u8 uint8_t
48#define __u16 uint16_t
49#define __be16 uint16_t
50#define u16 uint16_t
51#define __u32 uint32_t
52#define __be32 uint32_t
53#define u32 uint32_t
54#define __u64 uint64_t
55#define __be64 uint64_t
56#define u64 uint64_t
57#define DECLARE_PCI_UNMAP_ADDR(a)
58#define __iomem
59#define cpu_to_be16 htons
60#define cpu_to_be32 htonl
61#define cpu_to_be64 htonll
62#define be16_to_cpu ntohs
63#define be32_to_cpu ntohl
64#define be64_to_cpu ntohll
65#define BUG_ON(c) assert(!(c))
66#define unlikely
67#define ROUND_UP(x, n) (((x) + (n) - 1u) & ~((n) - 1u))
68#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
69#if __BYTE_ORDER == __LITTLE_ENDIAN
70#  define cpu_to_pci32(val) ((val))
71#elif __BYTE_ORDER == __BIG_ENDIAN
72#  define cpu_to_pci32(val) (__bswap_32((val)))
73#else
74#  error __BYTE_ORDER not defined
75#endif
76
77#define writel(v, a) do { *((volatile u32 *)(a)) = cpu_to_pci32(v); } while (0)
78
79#include <arpa/inet.h> 			/* For htonl() and friends */
80#include "t4_regs.h"
81#include "t4_chip_type.h"
82#include "t4fw_interface.h"
83
84#ifdef DEBUG
85#define DBGLOG(s)
86#define PDBG(fmt, args...) do {syslog(LOG_DEBUG, fmt, ##args); } while (0)
87#else
88#define DBGLOG(s)
89#define PDBG(fmt, args...) do {} while (0)
90#endif
91
92#define T4_MAX_READ_DEPTH 16
93#define T4_QID_BASE 1024
94#define T4_MAX_QIDS 256
95#define T4_MAX_NUM_PD 65536
96#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
97#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
98#define T4_MAX_IQ_SIZE (65520 - 1)
99#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
100#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
101#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
102#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
103#define T4_MAX_NUM_STAG (1<<15)
104#define T4_MAX_MR_SIZE (~0ULL - 1)
105#define T4_PAGESIZE_MASK 0xffff000  /* 4KB-128MB */
106#define T4_STAG_UNSET 0xffffffff
107#define T4_FW_MAJ 0
108
109struct t4_status_page {
110	__be32 rsvd1;	/* flit 0 - hw owns */
111	__be16 rsvd2;
112	__be16 qid;
113	__be16 cidx;
114	__be16 pidx;
115	u8 qp_err;	/* flit 1 - sw owns */
116	u8 db_off;
117	u8 pad;
118	u16 host_wq_pidx;
119	u16 host_cidx;
120	u16 host_pidx;
121};
122
123#define T4_EQ_ENTRY_SIZE 64
124
125#define T4_SQ_NUM_SLOTS 5
126#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
127#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - sizeof(struct fw_ri_isgl)) / sizeof (struct fw_ri_sge))
128#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - sizeof(struct fw_ri_immd)))
129#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_rdma_write_wr) - sizeof(struct fw_ri_immd)))
130#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_rdma_write_wr) - sizeof(struct fw_ri_isgl)) / sizeof (struct fw_ri_sge))
131#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - sizeof(struct fw_ri_immd)))
132#define T4_MAX_FR_DEPTH 255
133
134#define T4_RQ_NUM_SLOTS 2
135#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
136#define T4_MAX_RECV_SGE 4
137
138union t4_wr {
139	struct fw_ri_res_wr res;
140	struct fw_ri_wr init;
141	struct fw_ri_rdma_write_wr write;
142	struct fw_ri_send_wr send;
143	struct fw_ri_rdma_read_wr read;
144	struct fw_ri_bind_mw_wr bind;
145	struct fw_ri_fr_nsmr_wr fr;
146	struct fw_ri_inv_lstag_wr inv;
147	struct t4_status_page status;
148	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
149};
150
151union t4_recv_wr {
152	struct fw_ri_recv_wr recv;
153	struct t4_status_page status;
154	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
155};
156
157static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
158			       enum fw_wr_opcodes opcode, u8 flags, u8 len16)
159{
160	wqe->send.opcode = (u8)opcode;
161	wqe->send.flags = flags;
162	wqe->send.wrid = wrid;
163	wqe->send.r1[0] = 0;
164	wqe->send.r1[1] = 0;
165	wqe->send.r1[2] = 0;
166	wqe->send.len16 = len16;
167}
168
169/* CQE/AE status codes */
170#define T4_ERR_SUCCESS                     0x0
171#define T4_ERR_STAG                        0x1	/* STAG invalid: either the */
172						/* STAG is offlimt, being 0, */
173						/* or STAG_key mismatch */
174#define T4_ERR_PDID                        0x2	/* PDID mismatch */
175#define T4_ERR_QPID                        0x3	/* QPID mismatch */
176#define T4_ERR_ACCESS                      0x4	/* Invalid access right */
177#define T4_ERR_WRAP                        0x5	/* Wrap error */
178#define T4_ERR_BOUND                       0x6	/* base and bounds voilation */
179#define T4_ERR_INVALIDATE_SHARED_MR        0x7	/* attempt to invalidate a  */
180						/* shared memory region */
181#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8	/* attempt to invalidate a  */
182						/* shared memory region */
183#define T4_ERR_ECC                         0x9	/* ECC error detected */
184#define T4_ERR_ECC_PSTAG                   0xA	/* ECC error detected when  */
185						/* reading PSTAG for a MW  */
186						/* Invalidate */
187#define T4_ERR_PBL_ADDR_BOUND              0xB	/* pbl addr out of bounds:  */
188						/* software error */
189#define T4_ERR_SWFLUSH			   0xC	/* SW FLUSHED */
190#define T4_ERR_CRC                         0x10 /* CRC error */
191#define T4_ERR_MARKER                      0x11 /* Marker error */
192#define T4_ERR_PDU_LEN_ERR                 0x12 /* invalid PDU length */
193#define T4_ERR_OUT_OF_RQE                  0x13 /* out of RQE */
194#define T4_ERR_DDP_VERSION                 0x14 /* wrong DDP version */
195#define T4_ERR_RDMA_VERSION                0x15 /* wrong RDMA version */
196#define T4_ERR_OPCODE                      0x16 /* invalid rdma opcode */
197#define T4_ERR_DDP_QUEUE_NUM               0x17 /* invalid ddp queue number */
198#define T4_ERR_MSN                         0x18 /* MSN error */
199#define T4_ERR_TBIT                        0x19 /* tag bit not set correctly */
200#define T4_ERR_MO                          0x1A /* MO not 0 for TERMINATE  */
201						/* or READ_REQ */
202#define T4_ERR_MSN_GAP                     0x1B
203#define T4_ERR_MSN_RANGE                   0x1C
204#define T4_ERR_IRD_OVERFLOW                0x1D
205#define T4_ERR_RQE_ADDR_BOUND              0x1E /* RQE addr out of bounds:  */
206						/* software error */
207#define T4_ERR_INTERNAL_ERR                0x1F /* internal error (opcode  */
208						/* mismatch) */
209/*
210 * CQE defs
211 */
212struct t4_cqe {
213	__be32 header;
214	__be32 len;
215	union {
216		struct {
217			__be32 stag;
218			__be32 msn;
219		} rcqe;
220		struct {
221			u32 nada1;
222			u16 nada2;
223			u16 cidx;
224		} scqe;
225		struct {
226			__be32 wrid_hi;
227			__be32 wrid_low;
228		} gen;
229	} u;
230	__be64 reserved;
231	__be64 bits_type_ts;
232};
233
234/* macros for flit 0 of the cqe */
235
236#define S_CQE_QPID        12
237#define M_CQE_QPID        0xFFFFF
238#define G_CQE_QPID(x)     ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
239#define V_CQE_QPID(x)	  ((x)<<S_CQE_QPID)
240
241#define S_CQE_SWCQE       11
242#define M_CQE_SWCQE       0x1
243#define G_CQE_SWCQE(x)    ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
244#define V_CQE_SWCQE(x)	  ((x)<<S_CQE_SWCQE)
245
246#define S_CQE_STATUS      5
247#define M_CQE_STATUS      0x1F
248#define G_CQE_STATUS(x)   ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
249#define V_CQE_STATUS(x)   ((x)<<S_CQE_STATUS)
250
251#define S_CQE_TYPE        4
252#define M_CQE_TYPE        0x1
253#define G_CQE_TYPE(x)     ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
254#define V_CQE_TYPE(x)     ((x)<<S_CQE_TYPE)
255
256#define S_CQE_OPCODE      0
257#define M_CQE_OPCODE      0xF
258#define G_CQE_OPCODE(x)   ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
259#define V_CQE_OPCODE(x)   ((x)<<S_CQE_OPCODE)
260
261#define SW_CQE(x)         (G_CQE_SWCQE(be32_to_cpu((x)->header)))
262#define CQE_QPID(x)       (G_CQE_QPID(be32_to_cpu((x)->header)))
263#define CQE_TYPE(x)       (G_CQE_TYPE(be32_to_cpu((x)->header)))
264#define SQ_TYPE(x)	  (CQE_TYPE((x)))
265#define RQ_TYPE(x)	  (!CQE_TYPE((x)))
266#define CQE_STATUS(x)     (G_CQE_STATUS(be32_to_cpu((x)->header)))
267#define CQE_OPCODE(x)     (G_CQE_OPCODE(be32_to_cpu((x)->header)))
268
269#define CQE_SEND_OPCODE(x)( \
270	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
271	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
272	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
273	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
274
275#define CQE_LEN(x)        (be32_to_cpu((x)->len))
276
277/* used for RQ completion processing */
278#define CQE_WRID_STAG(x)  (be32_to_cpu((x)->u.rcqe.stag))
279#define CQE_WRID_MSN(x)   (be32_to_cpu((x)->u.rcqe.msn))
280
281/* used for SQ completion processing */
282#define CQE_WRID_SQ_IDX(x)	(x)->u.scqe.cidx
283
284/* generic accessor macros */
285#define CQE_WRID_HI(x)		((x)->u.gen.wrid_hi)
286#define CQE_WRID_LOW(x)		((x)->u.gen.wrid_low)
287
288/* macros for flit 3 of the cqe */
289#define S_CQE_GENBIT	63
290#define M_CQE_GENBIT	0x1
291#define G_CQE_GENBIT(x)	(((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
292#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
293
294#define S_CQE_OVFBIT	62
295#define M_CQE_OVFBIT	0x1
296#define G_CQE_OVFBIT(x)	((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
297
298#define S_CQE_IQTYPE	60
299#define M_CQE_IQTYPE	0x3
300#define G_CQE_IQTYPE(x)	((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
301
302#define M_CQE_TS	0x0fffffffffffffffULL
303#define G_CQE_TS(x)	((x) & M_CQE_TS)
304
305#define CQE_OVFBIT(x)	((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
306#define CQE_GENBIT(x)	((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
307#define CQE_TS(x)	(G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
308
309struct t4_swsqe {
310	u64			wr_id;
311	struct t4_cqe		cqe;
312	__be32			read_len;
313	int			opcode;
314	int			complete;
315	int			signaled;
316	u16			idx;
317	int			flushed;
318};
319
320enum {
321	T4_SQ_ONCHIP = (1<<0),
322};
323
324struct t4_sq {
325	union t4_wr *queue;
326	struct t4_swsqe *sw_sq;
327	struct t4_swsqe *oldest_read;
328	volatile u32 *udb;
329	size_t memsize;
330	u32 qid;
331	u32 bar2_qid;
332	void *ma_sync;
333	u16 in_use;
334	u16 size;
335	u16 cidx;
336	u16 pidx;
337	u16 wq_pidx;
338	u16 flags;
339	short flush_cidx;
340	int wc_reg_available;
341};
342
343struct t4_swrqe {
344	u64 wr_id;
345};
346
347struct t4_rq {
348	union  t4_recv_wr *queue;
349	struct t4_swrqe *sw_rq;
350	volatile u32 *udb;
351	size_t memsize;
352	u32 qid;
353	u32 bar2_qid;
354	u32 msn;
355	u32 rqt_hwaddr;
356	u16 rqt_size;
357	u16 in_use;
358	u16 size;
359	u16 cidx;
360	u16 pidx;
361	u16 wq_pidx;
362	int wc_reg_available;
363};
364
365struct t4_wq {
366	struct t4_sq sq;
367	struct t4_rq rq;
368	struct c4iw_rdev *rdev;
369	u32 qid_mask;
370	int error;
371	int flushed;
372	u8 *db_offp;
373};
374
375static inline void t4_ma_sync(struct t4_wq *wq, int page_size)
376{
377	wc_wmb();
378	*((volatile u32 *)wq->sq.ma_sync) = 1;
379}
380
381static inline int t4_rqes_posted(struct t4_wq *wq)
382{
383	return wq->rq.in_use;
384}
385
386static inline int t4_rq_empty(struct t4_wq *wq)
387{
388	return wq->rq.in_use == 0;
389}
390
391static inline int t4_rq_full(struct t4_wq *wq)
392{
393	return wq->rq.in_use == (wq->rq.size - 1);
394}
395
396static inline u32 t4_rq_avail(struct t4_wq *wq)
397{
398	return wq->rq.size - 1 - wq->rq.in_use;
399}
400
401static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
402{
403	wq->rq.in_use++;
404	if (++wq->rq.pidx == wq->rq.size)
405		wq->rq.pidx = 0;
406	wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
407	if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
408		wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
409	if (!wq->error)
410		wq->rq.queue[wq->rq.size].status.host_pidx = wq->rq.pidx;
411}
412
413static inline void t4_rq_consume(struct t4_wq *wq)
414{
415	wq->rq.in_use--;
416	wq->rq.msn++;
417	if (++wq->rq.cidx == wq->rq.size)
418		wq->rq.cidx = 0;
419	assert((wq->rq.cidx != wq->rq.pidx) || wq->rq.in_use == 0);
420	if (!wq->error)
421		wq->rq.queue[wq->rq.size].status.host_cidx = wq->rq.cidx;
422}
423
424static inline int t4_sq_empty(struct t4_wq *wq)
425{
426	return wq->sq.in_use == 0;
427}
428
429static inline int t4_sq_full(struct t4_wq *wq)
430{
431	return wq->sq.in_use == (wq->sq.size - 1);
432}
433
434static inline u32 t4_sq_avail(struct t4_wq *wq)
435{
436	return wq->sq.size - 1 - wq->sq.in_use;
437}
438
439static inline int t4_sq_onchip(struct t4_wq *wq)
440{
441	return wq->sq.flags & T4_SQ_ONCHIP;
442}
443
444static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
445{
446	wq->sq.in_use++;
447	if (++wq->sq.pidx == wq->sq.size)
448		wq->sq.pidx = 0;
449	wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
450	if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
451		wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
452	if (!wq->error)
453		wq->sq.queue[wq->sq.size].status.host_pidx = (wq->sq.pidx);
454}
455
456static inline void t4_sq_consume(struct t4_wq *wq)
457{
458	assert(wq->sq.in_use >= 1);
459	if (wq->sq.cidx == wq->sq.flush_cidx)
460                wq->sq.flush_cidx = -1;
461	wq->sq.in_use--;
462	if (++wq->sq.cidx == wq->sq.size)
463		wq->sq.cidx = 0;
464	assert((wq->sq.cidx != wq->sq.pidx) || wq->sq.in_use == 0);
465	if (!wq->error)
466		wq->sq.queue[wq->sq.size].status.host_cidx = wq->sq.cidx;
467}
468
469static void copy_wqe_to_udb(volatile u32 *udb_offset, void *wqe)
470{
471	u64 *src, *dst;
472	int len16 = 4;
473
474	src = (u64 *)wqe;
475	dst = (u64 *)udb_offset;
476
477	while (len16) {
478		*dst++ = *src++;
479		*dst++ = *src++;
480		len16--;
481	}
482}
483
484extern int ma_wr;
485extern int t5_en_wc;
486
487static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
488				 union t4_wr *wqe)
489{
490	wc_wmb();
491	if (t5) {
492		if (t5_en_wc && inc == 1 && wq->sq.wc_reg_available) {
493			PDBG("%s: WC wq->sq.pidx = %d; len16=%d\n",
494			     __func__, wq->sq.pidx, len16);
495			copy_wqe_to_udb(wq->sq.udb + 14, wqe);
496		} else {
497			PDBG("%s: DB wq->sq.pidx = %d; len16=%d\n",
498			     __func__, wq->sq.pidx, len16);
499			writel(V_QID(wq->sq.bar2_qid) | V_PIDX_T5(inc), wq->sq.udb);
500		}
501		wc_wmb();
502		return;
503	}
504	if (ma_wr) {
505		if (t4_sq_onchip(wq)) {
506			int i;
507			for (i = 0; i < 16; i++)
508				*(volatile u32 *)&wq->sq.queue[wq->sq.size].flits[2+i] = i;
509		}
510	} else {
511		if (t4_sq_onchip(wq)) {
512			int i;
513			for (i = 0; i < 16; i++)
514				*(u32 *)&wq->sq.queue[wq->sq.size].flits[2] = i;
515		}
516	}
517	writel(V_QID(wq->sq.qid & wq->qid_mask) | V_PIDX(inc), wq->sq.udb);
518}
519
520static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
521				 union t4_recv_wr *wqe)
522{
523	wc_wmb();
524	if (t5) {
525		if (t5_en_wc && inc == 1 && wq->sq.wc_reg_available) {
526			PDBG("%s: WC wq->rq.pidx = %d; len16=%d\n",
527			     __func__, wq->rq.pidx, len16);
528			copy_wqe_to_udb(wq->rq.udb + 14, wqe);
529		} else {
530			PDBG("%s: DB wq->rq.pidx = %d; len16=%d\n",
531			     __func__, wq->rq.pidx, len16);
532			writel(V_QID(wq->rq.bar2_qid) | V_PIDX_T5(inc), wq->rq.udb);
533		}
534		wc_wmb();
535		return;
536	}
537	writel(V_QID(wq->rq.qid & wq->qid_mask) | V_PIDX(inc), wq->rq.udb);
538}
539
540static inline int t4_wq_in_error(struct t4_wq *wq)
541{
542	return wq->error || wq->rq.queue[wq->rq.size].status.qp_err;
543}
544
545static inline void t4_set_wq_in_error(struct t4_wq *wq)
546{
547	wq->rq.queue[wq->rq.size].status.qp_err = 1;
548}
549
550extern int c4iw_abi_version;
551
552static inline int t4_wq_db_enabled(struct t4_wq *wq)
553{
554	/*
555	 * If iw_cxgb4 driver supports door bell drop recovery then its
556	 * c4iw_abi_version would be greater than or equal to 2. In such
557	 * case return the status of db_off flag to ring the kernel mode
558	 * DB from user mode library.
559	 */
560	if ( c4iw_abi_version >= 2 )
561		return ! *wq->db_offp;
562	else
563		return 1;
564}
565
566struct t4_cq {
567	struct t4_cqe *queue;
568	struct t4_cqe *sw_queue;
569	struct c4iw_rdev *rdev;
570	volatile u32 *ugts;
571	size_t memsize;
572	u64 bits_type_ts;
573	u32 cqid;
574	u32 qid_mask;
575	u16 size; /* including status page */
576	u16 cidx;
577	u16 sw_pidx;
578	u16 sw_cidx;
579	u16 sw_in_use;
580	u16 cidx_inc;
581	u8 gen;
582	u8 error;
583};
584
585static inline int t4_arm_cq(struct t4_cq *cq, int se)
586{
587	u32 val;
588
589	while (cq->cidx_inc > M_CIDXINC) {
590		val = V_SEINTARM(0) | V_CIDXINC(M_CIDXINC) | V_TIMERREG(7) |
591		      V_INGRESSQID(cq->cqid & cq->qid_mask);
592		writel(val, cq->ugts);
593		cq->cidx_inc -= M_CIDXINC;
594	}
595	val = V_SEINTARM(se) | V_CIDXINC(cq->cidx_inc) | V_TIMERREG(6) |
596	      V_INGRESSQID(cq->cqid & cq->qid_mask);
597	writel(val, cq->ugts);
598	cq->cidx_inc = 0;
599	return 0;
600}
601
602static inline void t4_swcq_produce(struct t4_cq *cq)
603{
604	cq->sw_in_use++;
605	if (cq->sw_in_use == cq->size) {
606		syslog(LOG_NOTICE, "cxgb4 sw cq overflow cqid %u\n", cq->cqid);
607		cq->error = 1;
608		assert(0);
609	}
610	if (++cq->sw_pidx == cq->size)
611		cq->sw_pidx = 0;
612}
613
614static inline void t4_swcq_consume(struct t4_cq *cq)
615{
616	assert(cq->sw_in_use >= 1);
617	cq->sw_in_use--;
618	if (++cq->sw_cidx == cq->size)
619		cq->sw_cidx = 0;
620}
621
622static inline void t4_hwcq_consume(struct t4_cq *cq)
623{
624	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
625	if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == M_CIDXINC) {
626		uint32_t val;
627
628		val = V_SEINTARM(0) | V_CIDXINC(cq->cidx_inc) | V_TIMERREG(7) |
629			V_INGRESSQID(cq->cqid & cq->qid_mask);
630		writel(val, cq->ugts);
631		cq->cidx_inc = 0;
632	}
633	if (++cq->cidx == cq->size) {
634		cq->cidx = 0;
635		cq->gen ^= 1;
636	}
637	((struct t4_status_page *)&cq->queue[cq->size])->host_cidx = cq->cidx;
638}
639
640static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
641{
642	return (CQE_GENBIT(cqe) == cq->gen);
643}
644
645static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
646{
647	int ret;
648	u16 prev_cidx;
649
650	if (cq->cidx == 0)
651		prev_cidx = cq->size - 1;
652	else
653		prev_cidx = cq->cidx - 1;
654
655	if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
656		ret = -EOVERFLOW;
657		syslog(LOG_NOTICE, "cxgb4 cq overflow cqid %u\n", cq->cqid);
658		cq->error = 1;
659		assert(0);
660	} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
661		rmb();
662		*cqe = &cq->queue[cq->cidx];
663		ret = 0;
664	} else
665		ret = -ENODATA;
666	return ret;
667}
668
669static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
670{
671	if (cq->sw_in_use == cq->size) {
672		syslog(LOG_NOTICE, "cxgb4 sw cq overflow cqid %u\n", cq->cqid);
673		cq->error = 1;
674		assert(0);
675		return NULL;
676	}
677	if (cq->sw_in_use)
678		return &cq->sw_queue[cq->sw_cidx];
679	return NULL;
680}
681
682static inline int t4_cq_notempty(struct t4_cq *cq)
683{
684	return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]);
685}
686
687static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
688{
689	int ret = 0;
690
691	if (cq->error)
692		ret = -ENODATA;
693	else if (cq->sw_in_use)
694		*cqe = &cq->sw_queue[cq->sw_cidx];
695	else ret = t4_next_hw_cqe(cq, cqe);
696	return ret;
697}
698
699static inline int t4_cq_in_error(struct t4_cq *cq)
700{
701	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
702}
703
704static inline void t4_set_cq_in_error(struct t4_cq *cq)
705{
706	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
707}
708
709static inline void t4_reset_cq_in_error(struct t4_cq *cq)
710{
711	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 0;
712}
713
714struct t4_dev_status_page
715{
716	u8 db_off;
717};
718
719#endif
720