ArchSpec.cpp revision 269024
1//===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "lldb/Core/ArchSpec.h" 11 12#include <stdio.h> 13#include <errno.h> 14 15#include <string> 16 17#include "llvm/Support/COFF.h" 18#include "llvm/Support/ELF.h" 19#include "llvm/Support/Host.h" 20#include "llvm/Support/MachO.h" 21#include "lldb/Core/RegularExpression.h" 22#include "lldb/Host/Endian.h" 23#include "lldb/Host/Host.h" 24#include "lldb/Target/Platform.h" 25 26using namespace lldb; 27using namespace lldb_private; 28 29#define ARCH_SPEC_SEPARATOR_CHAR '-' 30 31 32static bool cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match); 33 34namespace lldb_private { 35 36 struct CoreDefinition 37 { 38 ByteOrder default_byte_order; 39 uint32_t addr_byte_size; 40 uint32_t min_opcode_byte_size; 41 uint32_t max_opcode_byte_size; 42 llvm::Triple::ArchType machine; 43 ArchSpec::Core core; 44 const char *name; 45 }; 46 47} 48 49// This core information can be looked using the ArchSpec::Core as the index 50static const CoreDefinition g_core_definitions[ArchSpec::kNumCores] = 51{ 52 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_generic , "arm" }, 53 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4 , "armv4" }, 54 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4t , "armv4t" }, 55 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5 , "armv5" }, 56 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5e , "armv5e" }, 57 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5t , "armv5t" }, 58 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6 , "armv6" }, 59 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6m , "armv6m" }, 60 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7 , "armv7" }, 61 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7f , "armv7f" }, 62 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7s , "armv7s" }, 63 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7k , "armv7k" }, 64 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7m , "armv7m" }, 65 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7em , "armv7em" }, 66 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_xscale , "xscale" }, 67 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumb , "thumb" }, 68 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv4t , "thumbv4t" }, 69 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5 , "thumbv5" }, 70 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5e , "thumbv5e" }, 71 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6 , "thumbv6" }, 72 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6m , "thumbv6m" }, 73 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7 , "thumbv7" }, 74 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7f , "thumbv7f" }, 75 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7s , "thumbv7s" }, 76 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7k , "thumbv7k" }, 77 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7m , "thumbv7m" }, 78 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7em , "thumbv7em" }, 79 80 { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" }, 81 82 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "ppc" }, 83 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" }, 84 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc602 , "ppc602" }, 85 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603 , "ppc603" }, 86 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603e , "ppc603e" }, 87 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603ev , "ppc603ev" }, 88 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604 , "ppc604" }, 89 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604e , "ppc604e" }, 90 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc620 , "ppc620" }, 91 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc750 , "ppc750" }, 92 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7400 , "ppc7400" }, 93 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7450 , "ppc7450" }, 94 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc970 , "ppc970" }, 95 96 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_generic , "ppc64" }, 97 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_ppc970_64 , "ppc970-64" }, 98 99 { eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc , ArchSpec::eCore_sparc_generic , "sparc" }, 100 { eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, ArchSpec::eCore_sparc9_generic , "sparcv9" }, 101 102 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i386 , "i386" }, 103 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486 , "i486" }, 104 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486sx , "i486sx" }, 105 106 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64 , "x86_64" }, 107 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64h , "x86_64h" }, 108 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_generic, "hexagon" }, 109 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4" }, 110 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5" }, 111 112 { eByteOrderLittle, 4, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach32 , "unknown-mach-32" }, 113 { eByteOrderLittle, 8, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach64 , "unknown-mach-64" } 114}; 115 116struct ArchDefinitionEntry 117{ 118 ArchSpec::Core core; 119 uint32_t cpu; 120 uint32_t sub; 121 uint32_t cpu_mask; 122 uint32_t sub_mask; 123}; 124 125struct ArchDefinition 126{ 127 ArchitectureType type; 128 size_t num_entries; 129 const ArchDefinitionEntry *entries; 130 const char *name; 131}; 132 133 134size_t 135ArchSpec::AutoComplete (const char *name, StringList &matches) 136{ 137 uint32_t i; 138 if (name && name[0]) 139 { 140 for (i = 0; i < ArchSpec::kNumCores; ++i) 141 { 142 if (NameMatches(g_core_definitions[i].name, eNameMatchStartsWith, name)) 143 matches.AppendString (g_core_definitions[i].name); 144 } 145 } 146 else 147 { 148 for (i = 0; i < ArchSpec::kNumCores; ++i) 149 matches.AppendString (g_core_definitions[i].name); 150 } 151 return matches.GetSize(); 152} 153 154 155 156#define CPU_ANY (UINT32_MAX) 157 158//===----------------------------------------------------------------------===// 159// A table that gets searched linearly for matches. This table is used to 160// convert cpu type and subtypes to architecture names, and to convert 161// architecture names to cpu types and subtypes. The ordering is important and 162// allows the precedence to be set when the table is built. 163#define SUBTYPE_MASK 0x00FFFFFFu 164static const ArchDefinitionEntry g_macho_arch_entries[] = 165{ 166 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , CPU_ANY, UINT32_MAX , UINT32_MAX }, 167 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK }, 168 { ArchSpec::eCore_arm_armv4 , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK }, 169 { ArchSpec::eCore_arm_armv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK }, 170 { ArchSpec::eCore_arm_armv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK }, 171 { ArchSpec::eCore_arm_armv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK }, 172 { ArchSpec::eCore_arm_armv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK }, 173 { ArchSpec::eCore_arm_armv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK }, 174 { ArchSpec::eCore_arm_armv5t , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK }, 175 { ArchSpec::eCore_arm_xscale , llvm::MachO::CPU_TYPE_ARM , 8 , UINT32_MAX , SUBTYPE_MASK }, 176 { ArchSpec::eCore_arm_armv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK }, 177 { ArchSpec::eCore_arm_armv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK }, 178 { ArchSpec::eCore_arm_armv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK }, 179 { ArchSpec::eCore_arm_armv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK }, 180 { ArchSpec::eCore_arm_armv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK }, 181 { ArchSpec::eCore_arm_armv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK }, 182 { ArchSpec::eCore_thumb , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK }, 183 { ArchSpec::eCore_thumbv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK }, 184 { ArchSpec::eCore_thumbv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK }, 185 { ArchSpec::eCore_thumbv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK }, 186 { ArchSpec::eCore_thumbv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK }, 187 { ArchSpec::eCore_thumbv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK }, 188 { ArchSpec::eCore_thumbv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK }, 189 { ArchSpec::eCore_thumbv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK }, 190 { ArchSpec::eCore_thumbv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK }, 191 { ArchSpec::eCore_thumbv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK }, 192 { ArchSpec::eCore_thumbv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK }, 193 { ArchSpec::eCore_thumbv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK }, 194 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , CPU_ANY, UINT32_MAX , UINT32_MAX }, 195 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , 0 , UINT32_MAX , SUBTYPE_MASK }, 196 { ArchSpec::eCore_ppc_ppc601 , llvm::MachO::CPU_TYPE_POWERPC , 1 , UINT32_MAX , SUBTYPE_MASK }, 197 { ArchSpec::eCore_ppc_ppc602 , llvm::MachO::CPU_TYPE_POWERPC , 2 , UINT32_MAX , SUBTYPE_MASK }, 198 { ArchSpec::eCore_ppc_ppc603 , llvm::MachO::CPU_TYPE_POWERPC , 3 , UINT32_MAX , SUBTYPE_MASK }, 199 { ArchSpec::eCore_ppc_ppc603e , llvm::MachO::CPU_TYPE_POWERPC , 4 , UINT32_MAX , SUBTYPE_MASK }, 200 { ArchSpec::eCore_ppc_ppc603ev , llvm::MachO::CPU_TYPE_POWERPC , 5 , UINT32_MAX , SUBTYPE_MASK }, 201 { ArchSpec::eCore_ppc_ppc604 , llvm::MachO::CPU_TYPE_POWERPC , 6 , UINT32_MAX , SUBTYPE_MASK }, 202 { ArchSpec::eCore_ppc_ppc604e , llvm::MachO::CPU_TYPE_POWERPC , 7 , UINT32_MAX , SUBTYPE_MASK }, 203 { ArchSpec::eCore_ppc_ppc620 , llvm::MachO::CPU_TYPE_POWERPC , 8 , UINT32_MAX , SUBTYPE_MASK }, 204 { ArchSpec::eCore_ppc_ppc750 , llvm::MachO::CPU_TYPE_POWERPC , 9 , UINT32_MAX , SUBTYPE_MASK }, 205 { ArchSpec::eCore_ppc_ppc7400 , llvm::MachO::CPU_TYPE_POWERPC , 10 , UINT32_MAX , SUBTYPE_MASK }, 206 { ArchSpec::eCore_ppc_ppc7450 , llvm::MachO::CPU_TYPE_POWERPC , 11 , UINT32_MAX , SUBTYPE_MASK }, 207 { ArchSpec::eCore_ppc_ppc970 , llvm::MachO::CPU_TYPE_POWERPC , 100 , UINT32_MAX , SUBTYPE_MASK }, 208 { ArchSpec::eCore_ppc64_generic , llvm::MachO::CPU_TYPE_POWERPC64 , 0 , UINT32_MAX , SUBTYPE_MASK }, 209 { ArchSpec::eCore_ppc64_ppc970_64 , llvm::MachO::CPU_TYPE_POWERPC64 , 100 , UINT32_MAX , SUBTYPE_MASK }, 210 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , 3 , UINT32_MAX , SUBTYPE_MASK }, 211 { ArchSpec::eCore_x86_32_i486 , llvm::MachO::CPU_TYPE_I386 , 4 , UINT32_MAX , SUBTYPE_MASK }, 212 { ArchSpec::eCore_x86_32_i486sx , llvm::MachO::CPU_TYPE_I386 , 0x84 , UINT32_MAX , SUBTYPE_MASK }, 213 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , CPU_ANY, UINT32_MAX , UINT32_MAX }, 214 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 3 , UINT32_MAX , SUBTYPE_MASK }, 215 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 4 , UINT32_MAX , SUBTYPE_MASK }, 216 { ArchSpec::eCore_x86_64_x86_64h , llvm::MachO::CPU_TYPE_X86_64 , 8 , UINT32_MAX , SUBTYPE_MASK }, 217 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , CPU_ANY, UINT32_MAX , UINT32_MAX }, 218 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files 219 { ArchSpec::eCore_uknownMach32 , 0 , 0 , 0xFF000000u, 0x00000000u }, 220 { ArchSpec::eCore_uknownMach64 , llvm::MachO::CPU_ARCH_ABI64 , 0 , 0xFF000000u, 0x00000000u } 221}; 222static const ArchDefinition g_macho_arch_def = { 223 eArchTypeMachO, 224 sizeof(g_macho_arch_entries)/sizeof(g_macho_arch_entries[0]), 225 g_macho_arch_entries, 226 "mach-o" 227}; 228 229//===----------------------------------------------------------------------===// 230// A table that gets searched linearly for matches. This table is used to 231// convert cpu type and subtypes to architecture names, and to convert 232// architecture names to cpu types and subtypes. The ordering is important and 233// allows the precedence to be set when the table is built. 234static const ArchDefinitionEntry g_elf_arch_entries[] = 235{ 236 { ArchSpec::eCore_sparc_generic , llvm::ELF::EM_SPARC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Sparc 237 { ArchSpec::eCore_x86_32_i386 , llvm::ELF::EM_386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386 238 { ArchSpec::eCore_x86_32_i486 , llvm::ELF::EM_486 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 486 (deprecated) 239 { ArchSpec::eCore_ppc_generic , llvm::ELF::EM_PPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC 240 { ArchSpec::eCore_ppc64_generic , llvm::ELF::EM_PPC64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC64 241 { ArchSpec::eCore_arm_generic , llvm::ELF::EM_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM 242 { ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9 243 { ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64 244 { ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // MIPS 245 { ArchSpec::eCore_hexagon_generic , llvm::ELF::EM_HEXAGON, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // HEXAGON 246}; 247 248static const ArchDefinition g_elf_arch_def = { 249 eArchTypeELF, 250 sizeof(g_elf_arch_entries)/sizeof(g_elf_arch_entries[0]), 251 g_elf_arch_entries, 252 "elf", 253}; 254 255static const ArchDefinitionEntry g_coff_arch_entries[] = 256{ 257 { ArchSpec::eCore_x86_32_i386 , llvm::COFF::IMAGE_FILE_MACHINE_I386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386 258 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC 259 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC (with FPU) 260 { ArchSpec::eCore_arm_generic , llvm::COFF::IMAGE_FILE_MACHINE_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM 261 { ArchSpec::eCore_arm_armv7 , llvm::COFF::IMAGE_FILE_MACHINE_ARMV7 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7 262 { ArchSpec::eCore_thumb , llvm::COFF::IMAGE_FILE_MACHINE_THUMB , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7 263 { ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // AMD64 264}; 265 266static const ArchDefinition g_coff_arch_def = { 267 eArchTypeCOFF, 268 sizeof(g_coff_arch_entries)/sizeof(g_coff_arch_entries[0]), 269 g_coff_arch_entries, 270 "pe-coff", 271}; 272 273//===----------------------------------------------------------------------===// 274// Table of all ArchDefinitions 275static const ArchDefinition *g_arch_definitions[] = { 276 &g_macho_arch_def, 277 &g_elf_arch_def, 278 &g_coff_arch_def 279}; 280 281static const size_t k_num_arch_definitions = 282 sizeof(g_arch_definitions) / sizeof(g_arch_definitions[0]); 283 284//===----------------------------------------------------------------------===// 285// Static helper functions. 286 287 288// Get the architecture definition for a given object type. 289static const ArchDefinition * 290FindArchDefinition (ArchitectureType arch_type) 291{ 292 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) 293 { 294 const ArchDefinition *def = g_arch_definitions[i]; 295 if (def->type == arch_type) 296 return def; 297 } 298 return NULL; 299} 300 301// Get an architecture definition by name. 302static const CoreDefinition * 303FindCoreDefinition (llvm::StringRef name) 304{ 305 for (unsigned int i = 0; i < ArchSpec::kNumCores; ++i) 306 { 307 if (name.equals_lower(g_core_definitions[i].name)) 308 return &g_core_definitions[i]; 309 } 310 return NULL; 311} 312 313static inline const CoreDefinition * 314FindCoreDefinition (ArchSpec::Core core) 315{ 316 if (core >= 0 && core < ArchSpec::kNumCores) 317 return &g_core_definitions[core]; 318 return NULL; 319} 320 321// Get a definition entry by cpu type and subtype. 322static const ArchDefinitionEntry * 323FindArchDefinitionEntry (const ArchDefinition *def, uint32_t cpu, uint32_t sub) 324{ 325 if (def == NULL) 326 return NULL; 327 328 const ArchDefinitionEntry *entries = def->entries; 329 for (size_t i = 0; i < def->num_entries; ++i) 330 { 331 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 332 if (entries[i].sub == (sub & entries[i].sub_mask)) 333 return &entries[i]; 334 } 335 return NULL; 336} 337 338static const ArchDefinitionEntry * 339FindArchDefinitionEntry (const ArchDefinition *def, ArchSpec::Core core) 340{ 341 if (def == NULL) 342 return NULL; 343 344 const ArchDefinitionEntry *entries = def->entries; 345 for (size_t i = 0; i < def->num_entries; ++i) 346 { 347 if (entries[i].core == core) 348 return &entries[i]; 349 } 350 return NULL; 351} 352 353//===----------------------------------------------------------------------===// 354// Constructors and destructors. 355 356ArchSpec::ArchSpec() : 357 m_triple (), 358 m_core (kCore_invalid), 359 m_byte_order (eByteOrderInvalid), 360 m_distribution_id () 361{ 362} 363 364ArchSpec::ArchSpec (const char *triple_cstr, Platform *platform) : 365 m_triple (), 366 m_core (kCore_invalid), 367 m_byte_order (eByteOrderInvalid), 368 m_distribution_id () 369{ 370 if (triple_cstr) 371 SetTriple(triple_cstr, platform); 372} 373 374 375ArchSpec::ArchSpec (const char *triple_cstr) : 376 m_triple (), 377 m_core (kCore_invalid), 378 m_byte_order (eByteOrderInvalid), 379 m_distribution_id () 380{ 381 if (triple_cstr) 382 SetTriple(triple_cstr); 383} 384 385ArchSpec::ArchSpec(const llvm::Triple &triple) : 386 m_triple (), 387 m_core (kCore_invalid), 388 m_byte_order (eByteOrderInvalid), 389 m_distribution_id () 390{ 391 SetTriple(triple); 392} 393 394ArchSpec::ArchSpec (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) : 395 m_triple (), 396 m_core (kCore_invalid), 397 m_byte_order (eByteOrderInvalid), 398 m_distribution_id () 399{ 400 SetArchitecture (arch_type, cpu, subtype); 401} 402 403ArchSpec::~ArchSpec() 404{ 405} 406 407//===----------------------------------------------------------------------===// 408// Assignment and initialization. 409 410const ArchSpec& 411ArchSpec::operator= (const ArchSpec& rhs) 412{ 413 if (this != &rhs) 414 { 415 m_triple = rhs.m_triple; 416 m_core = rhs.m_core; 417 m_byte_order = rhs.m_byte_order; 418 m_distribution_id = rhs.m_distribution_id; 419 } 420 return *this; 421} 422 423void 424ArchSpec::Clear() 425{ 426 m_triple = llvm::Triple(); 427 m_core = kCore_invalid; 428 m_byte_order = eByteOrderInvalid; 429 m_distribution_id.Clear (); 430} 431 432//===----------------------------------------------------------------------===// 433// Predicates. 434 435 436const char * 437ArchSpec::GetArchitectureName () const 438{ 439 const CoreDefinition *core_def = FindCoreDefinition (m_core); 440 if (core_def) 441 return core_def->name; 442 return "unknown"; 443} 444 445uint32_t 446ArchSpec::GetMachOCPUType () const 447{ 448 const CoreDefinition *core_def = FindCoreDefinition (m_core); 449 if (core_def) 450 { 451 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core); 452 if (arch_def) 453 { 454 return arch_def->cpu; 455 } 456 } 457 return LLDB_INVALID_CPUTYPE; 458} 459 460uint32_t 461ArchSpec::GetMachOCPUSubType () const 462{ 463 const CoreDefinition *core_def = FindCoreDefinition (m_core); 464 if (core_def) 465 { 466 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core); 467 if (arch_def) 468 { 469 return arch_def->sub; 470 } 471 } 472 return LLDB_INVALID_CPUTYPE; 473} 474 475llvm::Triple::ArchType 476ArchSpec::GetMachine () const 477{ 478 const CoreDefinition *core_def = FindCoreDefinition (m_core); 479 if (core_def) 480 return core_def->machine; 481 482 return llvm::Triple::UnknownArch; 483} 484 485const ConstString& 486ArchSpec::GetDistributionId () const 487{ 488 return m_distribution_id; 489} 490 491void 492ArchSpec::SetDistributionId (const char* distribution_id) 493{ 494 m_distribution_id.SetCString (distribution_id); 495} 496 497uint32_t 498ArchSpec::GetAddressByteSize() const 499{ 500 const CoreDefinition *core_def = FindCoreDefinition (m_core); 501 if (core_def) 502 return core_def->addr_byte_size; 503 return 0; 504} 505 506ByteOrder 507ArchSpec::GetDefaultEndian () const 508{ 509 const CoreDefinition *core_def = FindCoreDefinition (m_core); 510 if (core_def) 511 return core_def->default_byte_order; 512 return eByteOrderInvalid; 513} 514 515lldb::ByteOrder 516ArchSpec::GetByteOrder () const 517{ 518 if (m_byte_order == eByteOrderInvalid) 519 return GetDefaultEndian(); 520 return m_byte_order; 521} 522 523//===----------------------------------------------------------------------===// 524// Mutators. 525 526bool 527ArchSpec::SetTriple (const llvm::Triple &triple) 528{ 529 m_triple = triple; 530 531 llvm::StringRef arch_name (m_triple.getArchName()); 532 const CoreDefinition *core_def = FindCoreDefinition (arch_name); 533 if (core_def) 534 { 535 m_core = core_def->core; 536 // Set the byte order to the default byte order for an architecture. 537 // This can be modified if needed for cases when cores handle both 538 // big and little endian 539 m_byte_order = core_def->default_byte_order; 540 } 541 else 542 { 543 Clear(); 544 } 545 546 547 return IsValid(); 548} 549 550static bool 551ParseMachCPUDashSubtypeTriple (const char *triple_cstr, ArchSpec &arch) 552{ 553 // Accept "12-10" or "12.10" as cpu type/subtype 554 if (isdigit(triple_cstr[0])) 555 { 556 char *end = NULL; 557 errno = 0; 558 uint32_t cpu = (uint32_t)::strtoul (triple_cstr, &end, 0); 559 if (errno == 0 && cpu != 0 && end && ((*end == '-') || (*end == '.'))) 560 { 561 errno = 0; 562 uint32_t sub = (uint32_t)::strtoul (end + 1, &end, 0); 563 if (errno == 0 && end && ((*end == '-') || (*end == '.') || (*end == '\0'))) 564 { 565 if (arch.SetArchitecture (eArchTypeMachO, cpu, sub)) 566 { 567 if (*end == '-') 568 { 569 llvm::StringRef vendor_os (end + 1); 570 size_t dash_pos = vendor_os.find('-'); 571 if (dash_pos != llvm::StringRef::npos) 572 { 573 llvm::StringRef vendor_str(vendor_os.substr(0, dash_pos)); 574 arch.GetTriple().setVendorName(vendor_str); 575 const size_t vendor_start_pos = dash_pos+1; 576 dash_pos = vendor_os.find('-', vendor_start_pos); 577 if (dash_pos == llvm::StringRef::npos) 578 { 579 if (vendor_start_pos < vendor_os.size()) 580 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos)); 581 } 582 else 583 { 584 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos, dash_pos - vendor_start_pos)); 585 } 586 } 587 } 588 return true; 589 } 590 } 591 } 592 } 593 return false; 594} 595bool 596ArchSpec::SetTriple (const char *triple_cstr) 597{ 598 if (triple_cstr && triple_cstr[0]) 599 { 600 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this)) 601 return true; 602 603 llvm::StringRef triple_stref (triple_cstr); 604 if (triple_stref.startswith (LLDB_ARCH_DEFAULT)) 605 { 606 // Special case for the current host default architectures... 607 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT)) 608 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture32); 609 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT)) 610 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture64); 611 else if (triple_stref.equals (LLDB_ARCH_DEFAULT)) 612 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture); 613 } 614 else 615 { 616 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref)); 617 triple_stref = normalized_triple_sstr; 618 SetTriple (llvm::Triple (triple_stref)); 619 } 620 } 621 else 622 Clear(); 623 return IsValid(); 624} 625 626bool 627ArchSpec::SetTriple (const char *triple_cstr, Platform *platform) 628{ 629 if (triple_cstr && triple_cstr[0]) 630 { 631 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this)) 632 return true; 633 634 llvm::StringRef triple_stref (triple_cstr); 635 if (triple_stref.startswith (LLDB_ARCH_DEFAULT)) 636 { 637 // Special case for the current host default architectures... 638 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT)) 639 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture32); 640 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT)) 641 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture64); 642 else if (triple_stref.equals (LLDB_ARCH_DEFAULT)) 643 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture); 644 } 645 else 646 { 647 ArchSpec raw_arch (triple_cstr); 648 649 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref)); 650 triple_stref = normalized_triple_sstr; 651 llvm::Triple normalized_triple (triple_stref); 652 653 const bool os_specified = normalized_triple.getOSName().size() > 0; 654 const bool vendor_specified = normalized_triple.getVendorName().size() > 0; 655 const bool env_specified = normalized_triple.getEnvironmentName().size() > 0; 656 657 // If we got an arch only, then default the vendor, os, environment 658 // to match the platform if one is supplied 659 if (!(os_specified || vendor_specified || env_specified)) 660 { 661 if (platform) 662 { 663 // If we were given a platform, use the platform's system 664 // architecture. If this is not available (might not be 665 // connected) use the first supported architecture. 666 ArchSpec compatible_arch; 667 if (platform->IsCompatibleArchitecture (raw_arch, false, &compatible_arch)) 668 { 669 if (compatible_arch.IsValid()) 670 { 671 const llvm::Triple &compatible_triple = compatible_arch.GetTriple(); 672 if (!vendor_specified) 673 normalized_triple.setVendor(compatible_triple.getVendor()); 674 if (!os_specified) 675 normalized_triple.setOS(compatible_triple.getOS()); 676 if (!env_specified && compatible_triple.getEnvironmentName().size()) 677 normalized_triple.setEnvironment(compatible_triple.getEnvironment()); 678 } 679 } 680 else 681 { 682 *this = raw_arch; 683 return IsValid(); 684 } 685 } 686 else 687 { 688 // No platform specified, fall back to the host system for 689 // the default vendor, os, and environment. 690 llvm::Triple host_triple(llvm::sys::getDefaultTargetTriple()); 691 if (!vendor_specified) 692 normalized_triple.setVendor(host_triple.getVendor()); 693 if (!vendor_specified) 694 normalized_triple.setOS(host_triple.getOS()); 695 if (!env_specified && host_triple.getEnvironmentName().size()) 696 normalized_triple.setEnvironment(host_triple.getEnvironment()); 697 } 698 } 699 SetTriple (normalized_triple); 700 } 701 } 702 else 703 Clear(); 704 return IsValid(); 705} 706 707bool 708ArchSpec::SetArchitecture (ArchitectureType arch_type, uint32_t cpu, uint32_t sub) 709{ 710 m_core = kCore_invalid; 711 bool update_triple = true; 712 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 713 if (arch_def) 714 { 715 const ArchDefinitionEntry *arch_def_entry = FindArchDefinitionEntry (arch_def, cpu, sub); 716 if (arch_def_entry) 717 { 718 const CoreDefinition *core_def = FindCoreDefinition (arch_def_entry->core); 719 if (core_def) 720 { 721 m_core = core_def->core; 722 update_triple = false; 723 // Always use the architecture name because it might be more descriptive 724 // than the architecture enum ("armv7" -> llvm::Triple::arm). 725 m_triple.setArchName(llvm::StringRef(core_def->name)); 726 if (arch_type == eArchTypeMachO) 727 { 728 m_triple.setVendor (llvm::Triple::Apple); 729 730 switch (core_def->machine) 731 { 732 case llvm::Triple::arm: 733 case llvm::Triple::thumb: 734 m_triple.setOS (llvm::Triple::IOS); 735 break; 736 737 case llvm::Triple::x86: 738 case llvm::Triple::x86_64: 739 default: 740 m_triple.setOS (llvm::Triple::MacOSX); 741 break; 742 } 743 } 744 else 745 { 746 m_triple.setVendor (llvm::Triple::UnknownVendor); 747 m_triple.setOS (llvm::Triple::UnknownOS); 748 } 749 // Fall back onto setting the machine type if the arch by name failed... 750 if (m_triple.getArch () == llvm::Triple::UnknownArch) 751 m_triple.setArch (core_def->machine); 752 } 753 } 754 } 755 CoreUpdated(update_triple); 756 return IsValid(); 757} 758 759uint32_t 760ArchSpec::GetMinimumOpcodeByteSize() const 761{ 762 const CoreDefinition *core_def = FindCoreDefinition (m_core); 763 if (core_def) 764 return core_def->min_opcode_byte_size; 765 return 0; 766} 767 768uint32_t 769ArchSpec::GetMaximumOpcodeByteSize() const 770{ 771 const CoreDefinition *core_def = FindCoreDefinition (m_core); 772 if (core_def) 773 return core_def->max_opcode_byte_size; 774 return 0; 775} 776 777bool 778ArchSpec::IsExactMatch (const ArchSpec& rhs) const 779{ 780 return IsEqualTo (rhs, true); 781} 782 783bool 784ArchSpec::IsCompatibleMatch (const ArchSpec& rhs) const 785{ 786 return IsEqualTo (rhs, false); 787} 788 789bool 790ArchSpec::IsEqualTo (const ArchSpec& rhs, bool exact_match) const 791{ 792 // explicitly ignoring m_distribution_id in this method. 793 794 if (GetByteOrder() != rhs.GetByteOrder()) 795 return false; 796 797 const ArchSpec::Core lhs_core = GetCore (); 798 const ArchSpec::Core rhs_core = rhs.GetCore (); 799 800 const bool core_match = cores_match (lhs_core, rhs_core, true, exact_match); 801 802 if (core_match) 803 { 804 const llvm::Triple &lhs_triple = GetTriple(); 805 const llvm::Triple &rhs_triple = rhs.GetTriple(); 806 807 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 808 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 809 if (lhs_triple_vendor != rhs_triple_vendor) 810 { 811 if (exact_match) 812 { 813 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 814 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 815 // Both architectures had the vendor specified, so if they aren't 816 // equal then we return false 817 if (rhs_vendor_specified && lhs_vendor_specified) 818 return false; 819 } 820 821 // Only fail if both vendor types are not unknown 822 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 823 rhs_triple_vendor != llvm::Triple::UnknownVendor) 824 return false; 825 } 826 827 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 828 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 829 if (lhs_triple_os != rhs_triple_os) 830 { 831 if (exact_match) 832 { 833 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 834 const bool lhs_os_specified = TripleOSWasSpecified(); 835 // Both architectures had the OS specified, so if they aren't 836 // equal then we return false 837 if (rhs_os_specified && lhs_os_specified) 838 return false; 839 } 840 // Only fail if both os types are not unknown 841 if (lhs_triple_os != llvm::Triple::UnknownOS && 842 rhs_triple_os != llvm::Triple::UnknownOS) 843 return false; 844 } 845 846 const llvm::Triple::EnvironmentType lhs_triple_env = lhs_triple.getEnvironment(); 847 const llvm::Triple::EnvironmentType rhs_triple_env = rhs_triple.getEnvironment(); 848 849 if (lhs_triple_env != rhs_triple_env) 850 { 851 // Only fail if both environment types are not unknown 852 if (lhs_triple_env != llvm::Triple::UnknownEnvironment && 853 rhs_triple_env != llvm::Triple::UnknownEnvironment) 854 return false; 855 } 856 return true; 857 } 858 return false; 859} 860 861//===----------------------------------------------------------------------===// 862// Helper methods. 863 864void 865ArchSpec::CoreUpdated (bool update_triple) 866{ 867 const CoreDefinition *core_def = FindCoreDefinition (m_core); 868 if (core_def) 869 { 870 if (update_triple) 871 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 872 m_byte_order = core_def->default_byte_order; 873 } 874 else 875 { 876 if (update_triple) 877 m_triple = llvm::Triple(); 878 m_byte_order = eByteOrderInvalid; 879 } 880} 881 882//===----------------------------------------------------------------------===// 883// Operators. 884 885static bool 886cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match) 887{ 888 if (core1 == core2) 889 return true; 890 891 switch (core1) 892 { 893 case ArchSpec::kCore_any: 894 return true; 895 896 case ArchSpec::kCore_arm_any: 897 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 898 return true; 899 if (core2 >= ArchSpec::kCore_thumb_first && core2 <= ArchSpec::kCore_thumb_last) 900 return true; 901 if (core2 == ArchSpec::kCore_arm_any) 902 return true; 903 break; 904 905 case ArchSpec::kCore_x86_32_any: 906 if ((core2 >= ArchSpec::kCore_x86_32_first && core2 <= ArchSpec::kCore_x86_32_last) || (core2 == ArchSpec::kCore_x86_32_any)) 907 return true; 908 break; 909 910 case ArchSpec::kCore_ppc_any: 911 if ((core2 >= ArchSpec::kCore_ppc_first && core2 <= ArchSpec::kCore_ppc_last) || (core2 == ArchSpec::kCore_ppc_any)) 912 return true; 913 break; 914 915 case ArchSpec::kCore_ppc64_any: 916 if ((core2 >= ArchSpec::kCore_ppc64_first && core2 <= ArchSpec::kCore_ppc64_last) || (core2 == ArchSpec::kCore_ppc64_any)) 917 return true; 918 break; 919 920 case ArchSpec::eCore_arm_armv6m: 921 if (!enforce_exact_match) 922 { 923 try_inverse = false; 924 if (core2 == ArchSpec::eCore_arm_armv7) 925 return true; 926 } 927 928 case ArchSpec::kCore_hexagon_any: 929 if ((core2 >= ArchSpec::kCore_hexagon_first && core2 <= ArchSpec::kCore_hexagon_last) || (core2 == ArchSpec::kCore_hexagon_any)) 930 return true; 931 break; 932 933 case ArchSpec::eCore_arm_armv7m: 934 case ArchSpec::eCore_arm_armv7em: 935 case ArchSpec::eCore_arm_armv7f: 936 case ArchSpec::eCore_arm_armv7k: 937 case ArchSpec::eCore_arm_armv7s: 938 if (!enforce_exact_match) 939 { 940 try_inverse = false; 941 if (core2 == ArchSpec::eCore_arm_armv7) 942 return true; 943 } 944 break; 945 946 default: 947 break; 948 } 949 if (try_inverse) 950 return cores_match (core2, core1, false, enforce_exact_match); 951 return false; 952} 953 954bool 955lldb_private::operator<(const ArchSpec& lhs, const ArchSpec& rhs) 956{ 957 const ArchSpec::Core lhs_core = lhs.GetCore (); 958 const ArchSpec::Core rhs_core = rhs.GetCore (); 959 return lhs_core < rhs_core; 960} 961