arm_neon.td revision 263508
1//===--- arm_neon.td - ARM NEON compiler interface ------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the TableGen definitions from which the ARM NEON header 11// file will be generated. See ARM document DUI0348B. 12// 13//===----------------------------------------------------------------------===// 14 15class Op; 16 17def OP_NONE : Op; 18def OP_UNAVAILABLE : Op; 19def OP_ADD : Op; 20def OP_ADDL : Op; 21def OP_ADDLHi : Op; 22def OP_ADDW : Op; 23def OP_ADDWHi : Op; 24def OP_SUB : Op; 25def OP_SUBL : Op; 26def OP_SUBLHi : Op; 27def OP_SUBW : Op; 28def OP_SUBWHi : Op; 29def OP_MUL : Op; 30def OP_MLA : Op; 31def OP_MLAL : Op; 32def OP_MULLHi : Op; 33def OP_MULLHi_N : Op; 34def OP_MLALHi : Op; 35def OP_MLALHi_N : Op; 36def OP_MLS : Op; 37def OP_MLSL : Op; 38def OP_MLSLHi : Op; 39def OP_MLSLHi_N : Op; 40def OP_MUL_N : Op; 41def OP_MLA_N : Op; 42def OP_MLS_N : Op; 43def OP_FMLA_N : Op; 44def OP_FMLS_N : Op; 45def OP_MLAL_N : Op; 46def OP_MLSL_N : Op; 47def OP_MUL_LN: Op; 48def OP_MULX_LN: Op; 49def OP_MULL_LN : Op; 50def OP_MULLHi_LN : Op; 51def OP_MLA_LN: Op; 52def OP_MLS_LN: Op; 53def OP_MLAL_LN : Op; 54def OP_MLALHi_LN : Op; 55def OP_MLSL_LN : Op; 56def OP_MLSLHi_LN : Op; 57def OP_QDMULL_LN : Op; 58def OP_QDMULLHi_LN : Op; 59def OP_QDMLAL_LN : Op; 60def OP_QDMLALHi_LN : Op; 61def OP_QDMLSL_LN : Op; 62def OP_QDMLSLHi_LN : Op; 63def OP_QDMULH_LN : Op; 64def OP_QRDMULH_LN : Op; 65def OP_FMS_LN : Op; 66def OP_FMS_LNQ : Op; 67def OP_TRN1 : Op; 68def OP_ZIP1 : Op; 69def OP_UZP1 : Op; 70def OP_TRN2 : Op; 71def OP_ZIP2 : Op; 72def OP_UZP2 : Op; 73def OP_EQ : Op; 74def OP_GE : Op; 75def OP_LE : Op; 76def OP_GT : Op; 77def OP_LT : Op; 78def OP_NEG : Op; 79def OP_NOT : Op; 80def OP_AND : Op; 81def OP_OR : Op; 82def OP_XOR : Op; 83def OP_ANDN : Op; 84def OP_ORN : Op; 85def OP_CAST : Op; 86def OP_HI : Op; 87def OP_LO : Op; 88def OP_CONC : Op; 89def OP_DUP : Op; 90def OP_DUP_LN: Op; 91def OP_SEL : Op; 92def OP_REV64 : Op; 93def OP_REV32 : Op; 94def OP_REV16 : Op; 95def OP_XTN : Op; 96def OP_SQXTUN : Op; 97def OP_QXTN : Op; 98def OP_VCVT_NA_HI : Op; 99def OP_VCVT_EX_HI : Op; 100def OP_VCVTX_HI : Op; 101def OP_REINT : Op; 102def OP_ADDHNHi : Op; 103def OP_RADDHNHi : Op; 104def OP_SUBHNHi : Op; 105def OP_RSUBHNHi : Op; 106def OP_ABDL : Op; 107def OP_ABDLHi : Op; 108def OP_ABA : Op; 109def OP_ABAL : Op; 110def OP_ABALHi : Op; 111def OP_QDMULLHi : Op; 112def OP_QDMULLHi_N : Op; 113def OP_QDMLALHi : Op; 114def OP_QDMLALHi_N : Op; 115def OP_QDMLSLHi : Op; 116def OP_QDMLSLHi_N : Op; 117def OP_DIV : Op; 118def OP_LONG_HI : Op; 119def OP_NARROW_HI : Op; 120def OP_MOVL_HI : Op; 121def OP_COPY_LN : Op; 122def OP_COPYQ_LN : Op; 123def OP_COPY_LNQ : Op; 124def OP_SCALAR_MUL_LN : Op; 125def OP_SCALAR_MUL_LNQ : Op; 126def OP_SCALAR_MULX_LN : Op; 127def OP_SCALAR_MULX_LNQ : Op; 128def OP_SCALAR_VMULX_LN : Op; 129def OP_SCALAR_VMULX_LNQ : Op; 130def OP_SCALAR_QDMULL_LN : Op; 131def OP_SCALAR_QDMULL_LNQ : Op; 132def OP_SCALAR_QDMULH_LN : Op; 133def OP_SCALAR_QDMULH_LNQ : Op; 134def OP_SCALAR_QRDMULH_LN : Op; 135def OP_SCALAR_QRDMULH_LNQ : Op; 136def OP_SCALAR_GET_LN : Op; 137def OP_SCALAR_SET_LN : Op; 138 139class Inst <string n, string p, string t, Op o> { 140 string Name = n; 141 string Prototype = p; 142 string Types = t; 143 Op Operand = o; 144 bit isShift = 0; 145 bit isScalarShift = 0; 146 bit isScalarNarrowShift = 0; 147 bit isVCVT_N = 0; 148 bit isA64 = 0; 149 bit isCrypto = 0; 150 151 // Certain intrinsics have different names than their representative 152 // instructions. This field allows us to handle this correctly when we 153 // are generating tests. 154 string InstName = ""; 155 156 // Certain intrinsics even though they are not a WOpInst or LOpInst, 157 // generate a WOpInst/LOpInst instruction (see below for definition 158 // of a WOpInst/LOpInst). For testing purposes we need to know 159 // this. Ex: vset_lane which outputs vmov instructions. 160 bit isHiddenWInst = 0; 161 bit isHiddenLInst = 0; 162} 163 164// The following instruction classes are implemented via builtins. 165// These declarations are used to generate Builtins.def: 166// 167// SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8") 168// IInst: Instruction with generic integer suffix (e.g., "i8") 169// WInst: Instruction with only bit size suffix (e.g., "8") 170class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 171class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 172class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 173 174// The following instruction classes are implemented via operators 175// instead of builtins. As such these declarations are only used for 176// the purpose of generating tests. 177// 178// SOpInst: Instruction with signed/unsigned suffix (e.g., "s8", 179// "u8", "p8"). 180// IOpInst: Instruction with generic integer suffix (e.g., "i8"). 181// WOpInst: Instruction with bit size only suffix (e.g., "8"). 182// LOpInst: Logical instruction with no bit size suffix. 183// NoTestOpInst: Intrinsic that has no corresponding instruction. 184class SOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 185class IOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 186class WOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 187class LOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 188class NoTestOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 189 190// prototype: return (arg, arg, ...) 191// v: void 192// t: best-fit integer (int/poly args) 193// x: signed integer (int/float args) 194// u: unsigned integer (int/float args) 195// f: float (int args) 196// F: double (int args) 197// d: default 198// g: default, ignore 'Q' size modifier. 199// j: default, force 'Q' size modifier. 200// w: double width elements, same num elts 201// n: double width elements, half num elts 202// h: half width elements, double num elts 203// q: half width elements, quad num elts 204// e: half width elements, double num elts, unsigned 205// m: half width elements, same num elts 206// i: constant int 207// l: constant uint64 208// s: scalar of element type 209// z: scalar of half width element type, signed 210// r: scalar of double width element type, signed 211// a: scalar of element type (splat to vector type) 212// b: scalar of unsigned integer/long type (int/float args) 213// $: scalar of signed integer/long type (int/float args) 214// y: scalar of float 215// o: scalar of double 216// k: default elt width, double num elts 217// 2,3,4: array of default vectors 218// B,C,D: array of default elts, force 'Q' size modifier. 219// p: pointer type 220// c: const pointer type 221 222// sizes: 223// c: char 224// s: short 225// i: int 226// l: long 227// f: float 228// h: half-float 229// d: double 230 231// size modifiers: 232// S: scalar, only used for function mangling. 233// U: unsigned 234// Q: 128b 235// H: 128b without mangling 'q' 236// P: polynomial 237 238//////////////////////////////////////////////////////////////////////////////// 239// E.3.1 Addition 240def VADD : IOpInst<"vadd", "ddd", 241 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>; 242def VADDL : SOpInst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>; 243def VADDW : SOpInst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>; 244def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 245def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 246def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 247def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">; 248def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">; 249 250//////////////////////////////////////////////////////////////////////////////// 251// E.3.2 Multiplication 252def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>; 253def VMULP : SInst<"vmul", "ddd", "PcQPc">; 254def VMLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>; 255def VMLAL : SOpInst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>; 256def VMLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>; 257def VMLSL : SOpInst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>; 258def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">; 259def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">; 260def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">; 261def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">; 262def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">; 263def VQDMULL : SInst<"vqdmull", "wdd", "si">; 264 265//////////////////////////////////////////////////////////////////////////////// 266// E.3.3 Subtraction 267def VSUB : IOpInst<"vsub", "ddd", 268 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>; 269def VSUBL : SOpInst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>; 270def VSUBW : SOpInst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>; 271def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 272def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 273def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">; 274def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">; 275 276//////////////////////////////////////////////////////////////////////////////// 277// E.3.4 Comparison 278def VCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>; 279def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>; 280let InstName = "vcge" in 281def VCLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>; 282def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>; 283let InstName = "vcgt" in 284def VCLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>; 285let InstName = "vacge" in { 286def VCAGE : IInst<"vcage", "udd", "fQf">; 287def VCALE : IInst<"vcale", "udd", "fQf">; 288} 289let InstName = "vacgt" in { 290def VCAGT : IInst<"vcagt", "udd", "fQf">; 291def VCALT : IInst<"vcalt", "udd", "fQf">; 292} 293def VTST : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">; 294 295//////////////////////////////////////////////////////////////////////////////// 296// E.3.5 Absolute Difference 297def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 298def VABDL : SOpInst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>; 299def VABA : SOpInst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>; 300def VABAL : SOpInst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>; 301 302//////////////////////////////////////////////////////////////////////////////// 303// E.3.6 Max/Min 304def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 305def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 306 307//////////////////////////////////////////////////////////////////////////////// 308// E.3.7 Pairwise Addition 309def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">; 310def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">; 311def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">; 312 313//////////////////////////////////////////////////////////////////////////////// 314// E.3.8-9 Folding Max/Min 315def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">; 316def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">; 317 318//////////////////////////////////////////////////////////////////////////////// 319// E.3.10 Reciprocal/Sqrt 320def VRECPS : IInst<"vrecps", "ddd", "fQf">; 321def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">; 322 323//////////////////////////////////////////////////////////////////////////////// 324// E.3.11 Shifts by signed variable 325def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 326def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 327def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 328def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 329 330//////////////////////////////////////////////////////////////////////////////// 331// E.3.12 Shifts by constant 332let isShift = 1 in { 333def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 334def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 335def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 336def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 337def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 338def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 339def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">; 340def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">; 341def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">; 342def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">; 343def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">; 344def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">; 345def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">; 346def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">; 347 348//////////////////////////////////////////////////////////////////////////////// 349// E.3.13 Shifts with insert 350def VSRI_N : WInst<"vsri_n", "dddi", 351 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 352def VSLI_N : WInst<"vsli_n", "dddi", 353 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 354} 355 356//////////////////////////////////////////////////////////////////////////////// 357// E.3.14 Loads and stores of a single vector 358def VLD1 : WInst<"vld1", "dc", 359 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 360def VLD1_LANE : WInst<"vld1_lane", "dcdi", 361 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 362def VLD1_DUP : WInst<"vld1_dup", "dc", 363 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 364def VST1 : WInst<"vst1", "vpd", 365 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 366def VST1_LANE : WInst<"vst1_lane", "vpdi", 367 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 368 369//////////////////////////////////////////////////////////////////////////////// 370// E.3.15 Loads and stores of an N-element structure 371def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 372def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 373def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 374def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">; 375def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">; 376def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">; 377def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 378def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 379def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 380def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 381def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 382def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 383def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 384def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 385def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 386 387//////////////////////////////////////////////////////////////////////////////// 388// E.3.16 Extract lanes from a vector 389let InstName = "vmov" in 390def VGET_LANE : IInst<"vget_lane", "sdi", 391 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 392 393//////////////////////////////////////////////////////////////////////////////// 394// E.3.17 Set lanes within a vector 395let InstName = "vmov" in 396def VSET_LANE : IInst<"vset_lane", "dsdi", 397 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 398 399//////////////////////////////////////////////////////////////////////////////// 400// E.3.18 Initialize a vector from bit pattern 401def VCREATE : NoTestOpInst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST>; 402 403//////////////////////////////////////////////////////////////////////////////// 404// E.3.19 Set all lanes to same value 405let InstName = "vmov" in { 406def VDUP_N : WOpInst<"vdup_n", "ds", 407 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>; 408def VMOV_N : WOpInst<"vmov_n", "ds", 409 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>; 410} 411let InstName = "" in 412def VDUP_LANE: WOpInst<"vdup_lane", "dgi", 413 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", 414 OP_DUP_LN>; 415 416//////////////////////////////////////////////////////////////////////////////// 417// E.3.20 Combining vectors 418def VCOMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>; 419 420//////////////////////////////////////////////////////////////////////////////// 421// E.3.21 Splitting vectors 422let InstName = "vmov" in { 423def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>; 424def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>; 425} 426 427//////////////////////////////////////////////////////////////////////////////// 428// E.3.22 Converting vectors 429def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">; 430def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">; 431def VCVT_F16 : SInst<"vcvt_f16", "hk", "f">; 432def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">; 433def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "fd", "h">; 434let isVCVT_N = 1 in { 435def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">; 436def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">; 437def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">; 438} 439def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">; 440def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">; 441def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">; 442def VQMOVUN : SInst<"vqmovun", "ek", "sil">; 443 444//////////////////////////////////////////////////////////////////////////////// 445// E.3.23-24 Table lookup, Extended table lookup 446let InstName = "vtbl" in { 447def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">; 448def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">; 449def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">; 450def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">; 451} 452let InstName = "vtbx" in { 453def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">; 454def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">; 455def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">; 456def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">; 457} 458 459//////////////////////////////////////////////////////////////////////////////// 460// E.3.25 Operations with a scalar value 461def VMLA_LANE : IOpInst<"vmla_lane", "dddgi", 462 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 463def VMLAL_LANE : SOpInst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>; 464def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>; 465def VMLS_LANE : IOpInst<"vmls_lane", "dddgi", 466 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 467def VMLSL_LANE : SOpInst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>; 468def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>; 469def VMUL_N : IOpInst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>; 470def VMUL_LANE : IOpInst<"vmul_lane", "ddgi", 471 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>; 472def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">; 473def VMULL_LANE : SOpInst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>; 474def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">; 475def VQDMULL_LANE : SOpInst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>; 476def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">; 477def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>; 478def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">; 479def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>; 480def VMLA_N : IOpInst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>; 481def VMLAL_N : SOpInst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>; 482def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">; 483def VMLS_N : IOpInst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>; 484def VMLSL_N : SOpInst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>; 485def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">; 486 487//////////////////////////////////////////////////////////////////////////////// 488// E.3.26 Vector Extract 489def VEXT : WInst<"vext", "dddi", 490 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">; 491 492//////////////////////////////////////////////////////////////////////////////// 493// E.3.27 Reverse vector elements 494def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", 495 OP_REV64>; 496def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>; 497def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>; 498 499//////////////////////////////////////////////////////////////////////////////// 500// E.3.28 Other single operand arithmetic 501def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">; 502def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">; 503def VNEG : SOpInst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>; 504def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">; 505def VCLS : SInst<"vcls", "dd", "csiQcQsQi">; 506def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">; 507def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">; 508def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">; 509def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">; 510 511//////////////////////////////////////////////////////////////////////////////// 512// E.3.29 Logical operations 513def VMVN : LOpInst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>; 514def VAND : LOpInst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>; 515def VORR : LOpInst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>; 516def VEOR : LOpInst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>; 517def VBIC : LOpInst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>; 518def VORN : LOpInst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>; 519let isHiddenLInst = 1 in 520def VBSL : SInst<"vbsl", "dudd", 521 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">; 522 523//////////////////////////////////////////////////////////////////////////////// 524// E.3.30 Transposition operations 525def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 526def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 527def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 528 529//////////////////////////////////////////////////////////////////////////////// 530// E.3.31 Vector reinterpret cast operations 531def VREINTERPRET 532 : NoTestOpInst<"vreinterpret", "dd", 533 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT>; 534 535//////////////////////////////////////////////////////////////////////////////// 536// Vector fused multiply-add operations 537 538def VFMA : SInst<"vfma", "dddd", "fQf">; 539 540//////////////////////////////////////////////////////////////////////////////// 541// AArch64 Intrinsics 542 543let isA64 = 1 in { 544 545//////////////////////////////////////////////////////////////////////////////// 546// Load/Store 547// With additional QUl, Ql, d, Qd, Pl, QPl type. 548def LD1 : WInst<"vld1", "dc", 549 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 550def LD2 : WInst<"vld2", "2c", 551 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 552def LD3 : WInst<"vld3", "3c", 553 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 554def LD4 : WInst<"vld4", "4c", 555 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 556def ST1 : WInst<"vst1", "vpd", 557 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 558def ST2 : WInst<"vst2", "vp2", 559 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 560def ST3 : WInst<"vst3", "vp3", 561 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 562def ST4 : WInst<"vst4", "vp4", 563 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; 564 565def LD1_X2 : WInst<"vld1_x2", "2c", 566 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 567def LD3_x3 : WInst<"vld1_x3", "3c", 568 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 569def LD4_x4 : WInst<"vld1_x4", "4c", 570 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 571 572def ST1_X2 : WInst<"vst1_x2", "vp2", 573 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 574def ST1_X3 : WInst<"vst1_x3", "vp3", 575 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 576def ST1_X4 : WInst<"vst1_x4", "vp4", 577 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 578 579// With additional QUl, Ql, d, Qd, Pl, QPl type. 580def LD1_LANE : WInst<"vld1_lane", "dcdi", 581 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 582def LD2_LANE : WInst<"vld2_lane", "2c2i", 583 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 584def LD3_LANE : WInst<"vld3_lane", "3c3i", 585 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 586def LD4_LANE : WInst<"vld4_lane", "4c4i", 587 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 588def ST1_LANE : WInst<"vst1_lane", "vpdi", 589 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 590def ST2_LANE : WInst<"vst2_lane", "vp2i", 591 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 592def ST3_LANE : WInst<"vst3_lane", "vp3i", 593 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 594def ST4_LANE : WInst<"vst4_lane", "vp4i", 595 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 596 597def LD1_DUP : WInst<"vld1_dup", "dc", 598 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 599def LD2_DUP : WInst<"vld2_dup", "2c", 600 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 601def LD3_DUP : WInst<"vld3_dup", "3c", 602 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 603def LD4_DUP : WInst<"vld4_dup", "4c", 604 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; 605 606//////////////////////////////////////////////////////////////////////////////// 607// Addition 608// With additional d, Qd type. 609def ADD : IOpInst<"vadd", "ddd", "csilfdUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd", 610 OP_ADD>; 611 612//////////////////////////////////////////////////////////////////////////////// 613// Subtraction 614// With additional Qd type. 615def SUB : IOpInst<"vsub", "ddd", "csildfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd", 616 OP_SUB>; 617 618//////////////////////////////////////////////////////////////////////////////// 619// Multiplication 620// With additional Qd type. 621def MUL : IOpInst<"vmul", "ddd", "csifdUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MUL>; 622def MLA : IOpInst<"vmla", "dddd", "csifdUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLA>; 623def MLS : IOpInst<"vmls", "dddd", "csifdUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLS>; 624 625//////////////////////////////////////////////////////////////////////////////// 626// Multiplication Extended 627def MULX : SInst<"vmulx", "ddd", "fdQfQd">; 628 629//////////////////////////////////////////////////////////////////////////////// 630// Division 631def FDIV : IOpInst<"vdiv", "ddd", "fdQfQd", OP_DIV>; 632 633//////////////////////////////////////////////////////////////////////////////// 634// Vector fused multiply-add operations 635// With additional d, Qd type. 636def FMLA : SInst<"vfma", "dddd", "fdQfQd">; 637def FMLS : SInst<"vfms", "dddd", "fdQfQd">; 638 639//////////////////////////////////////////////////////////////////////////////// 640// MUL, FMA, FMS definitions with scalar argument 641def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>; 642def FMLA_N : SOpInst<"vfma_n", "ddds", "fQf", OP_FMLA_N>; 643def FMLS_N : SOpInst<"vfms_n", "ddds", "fQf", OP_FMLS_N>; 644 645//////////////////////////////////////////////////////////////////////////////// 646// Logical operations 647// With additional Qd, Ql, QPl type. 648def BSL : SInst<"vbsl", "dudd", 649 "csilUcUsUiUlfdPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPsQdPlQPl">; 650 651//////////////////////////////////////////////////////////////////////////////// 652// Absolute Difference 653// With additional Qd type. 654def ABD : SInst<"vabd", "ddd", "csiUcUsUifdQcQsQiQUcQUsQUiQfQd">; 655 656//////////////////////////////////////////////////////////////////////////////// 657// saturating absolute/negate 658// With additional Qd/Ql type. 659def ABS : SInst<"vabs", "dd", "csilfdQcQsQiQfQlQd">; 660def QABS : SInst<"vqabs", "dd", "csilQcQsQiQl">; 661def NEG : SOpInst<"vneg", "dd", "csilfdQcQsQiQfQdQl", OP_NEG>; 662def QNEG : SInst<"vqneg", "dd", "csilQcQsQiQl">; 663 664//////////////////////////////////////////////////////////////////////////////// 665// Signed Saturating Accumulated of Unsigned Value 666def SUQADD : SInst<"vuqadd", "ddd", "csilQcQsQiQl">; 667 668//////////////////////////////////////////////////////////////////////////////// 669// Unsigned Saturating Accumulated of Signed Value 670def USQADD : SInst<"vsqadd", "ddd", "UcUsUiUlQUcQUsQUiQUl">; 671 672//////////////////////////////////////////////////////////////////////////////// 673// Reciprocal/Sqrt 674// With additional d, Qd type. 675def FRECPS : IInst<"vrecps", "ddd", "fdQfQd">; 676def FRSQRTS : IInst<"vrsqrts", "ddd", "fdQfQd">; 677 678//////////////////////////////////////////////////////////////////////////////// 679// bitwise reverse 680def RBIT : IInst<"vrbit", "dd", "cUcPcQcQUcQPc">; 681 682//////////////////////////////////////////////////////////////////////////////// 683// Integer extract and narrow to high 684def XTN2 : SOpInst<"vmovn_high", "qhk", "silUsUiUl", OP_XTN>; 685 686//////////////////////////////////////////////////////////////////////////////// 687// Signed integer saturating extract and unsigned narrow to high 688def SQXTUN2 : SOpInst<"vqmovun_high", "qhk", "sil", OP_SQXTUN>; 689 690//////////////////////////////////////////////////////////////////////////////// 691// Integer saturating extract and narrow to high 692def QXTN2 : SOpInst<"vqmovn_high", "qhk", "silUsUiUl", OP_QXTN>; 693 694//////////////////////////////////////////////////////////////////////////////// 695// Converting vectors 696def VCVT_HIGH_F16 : SOpInst<"vcvt_high_f16", "qhj", "f", OP_VCVT_NA_HI>; 697def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "wk", "h", OP_VCVT_EX_HI>; 698def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "fj", "d">; 699def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "qfj", "d", OP_VCVT_NA_HI>; 700def VCVT_F64_F32 : SInst<"vcvt_f64_f32", "wd", "f">; 701def VCVT_F64 : SInst<"vcvt_f64", "Fd", "lUlQlQUl">; 702def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "wj", "f", OP_VCVT_EX_HI>; 703def VCVTX_F32_F64 : SInst<"vcvtx_f32", "fj", "d">; 704def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "qfj", "d", OP_VCVTX_HI>; 705def FRINTN : SInst<"vrndn", "dd", "fdQfQd">; 706def FRINTA : SInst<"vrnda", "dd", "fdQfQd">; 707def FRINTP : SInst<"vrndp", "dd", "fdQfQd">; 708def FRINTM : SInst<"vrndm", "dd", "fdQfQd">; 709def FRINTX : SInst<"vrndx", "dd", "fdQfQd">; 710def FRINTZ : SInst<"vrnd", "dd", "fdQfQd">; 711def FRINTI : SInst<"vrndi", "dd", "fdQfQd">; 712def VCVT_S64 : SInst<"vcvt_s64", "xd", "dQd">; 713def VCVT_U64 : SInst<"vcvt_u64", "ud", "dQd">; 714def FCVTNS_S32 : SInst<"vcvtn_s32", "xd", "fQf">; 715def FCVTNS_S64 : SInst<"vcvtn_s64", "xd", "dQd">; 716def FCVTNU_S32 : SInst<"vcvtn_u32", "ud", "fQf">; 717def FCVTNU_S64 : SInst<"vcvtn_u64", "ud", "dQd">; 718def FCVTPS_S32 : SInst<"vcvtp_s32", "xd", "fQf">; 719def FCVTPS_S64 : SInst<"vcvtp_s64", "xd", "dQd">; 720def FCVTPU_S32 : SInst<"vcvtp_u32", "ud", "fQf">; 721def FCVTPU_S64 : SInst<"vcvtp_u64", "ud", "dQd">; 722def FCVTMS_S32 : SInst<"vcvtm_s32", "xd", "fQf">; 723def FCVTMS_S64 : SInst<"vcvtm_s64", "xd", "dQd">; 724def FCVTMU_S32 : SInst<"vcvtm_u32", "ud", "fQf">; 725def FCVTMU_S64 : SInst<"vcvtm_u64", "ud", "dQd">; 726def FCVTAS_S32 : SInst<"vcvta_s32", "xd", "fQf">; 727def FCVTAS_S64 : SInst<"vcvta_s64", "xd", "dQd">; 728def FCVTAU_S32 : SInst<"vcvta_u32", "ud", "fQf">; 729def FCVTAU_S64 : SInst<"vcvta_u64", "ud", "dQd">; 730def FRECPE : SInst<"vrecpe", "dd", "fdUiQfQUiQd">; 731def FRSQRTE : SInst<"vrsqrte", "dd", "fdUiQfQUiQd">; 732def FSQRT : SInst<"vsqrt", "dd", "fdQfQd">; 733 734//////////////////////////////////////////////////////////////////////////////// 735// Comparison 736// With additional Qd, Ql, QPl type. 737def FCAGE : IInst<"vcage", "udd", "fdQfQd">; 738def FCAGT : IInst<"vcagt", "udd", "fdQfQd">; 739def FCALE : IInst<"vcale", "udd", "fdQfQd">; 740def FCALT : IInst<"vcalt", "udd", "fdQfQd">; 741// With additional Ql, QUl, Qd types. 742def CMTST : WInst<"vtst", "udd", 743 "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPslUlQlQUlPlQPl">; 744// With additional l, Ul,d, Qd, Ql, QUl, Qd types. 745def CFMEQ : SOpInst<"vceq", "udd", 746 "csilfUcUsUiUlPcQcdQdQsQiQfQUcQUsQUiQUlQlQPcPlQPl", OP_EQ>; 747def CFMGE : SOpInst<"vcge", "udd", 748 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_GE>; 749def CFMLE : SOpInst<"vcle", "udd", 750 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_LE>; 751def CFMGT : SOpInst<"vcgt", "udd", 752 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_GT>; 753def CFMLT : SOpInst<"vclt", "udd", 754 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_LT>; 755 756def CMEQ : SInst<"vceqz", "ud", 757 "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">; 758def CMGE : SInst<"vcgez", "ud", "csilfdQcQsQiQlQfQd">; 759def CMLE : SInst<"vclez", "ud", "csilfdQcQsQiQlQfQd">; 760def CMGT : SInst<"vcgtz", "ud", "csilfdQcQsQiQlQfQd">; 761def CMLT : SInst<"vcltz", "ud", "csilfdQcQsQiQlQfQd">; 762 763//////////////////////////////////////////////////////////////////////////////// 764// Max/Min Integer 765// With additional Qd type. 766def MAX : SInst<"vmax", "ddd", "csiUcUsUifdQcQsQiQUcQUsQUiQfQd">; 767def MIN : SInst<"vmin", "ddd", "csiUcUsUifdQcQsQiQUcQUsQUiQfQd">; 768 769//////////////////////////////////////////////////////////////////////////////// 770// MaxNum/MinNum Floating Point 771def FMAXNM : SInst<"vmaxnm", "ddd", "fdQfQd">; 772def FMINNM : SInst<"vminnm", "ddd", "fdQfQd">; 773 774//////////////////////////////////////////////////////////////////////////////// 775// Pairwise Max/Min 776// With additional Qc Qs Qi QUc QUs QUi Qf Qd types. 777def MAXP : SInst<"vpmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 778def MINP : SInst<"vpmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 779 780//////////////////////////////////////////////////////////////////////////////// 781// Pairwise MaxNum/MinNum Floating Point 782def FMAXNMP : SInst<"vpmaxnm", "ddd", "fQfQd">; 783def FMINNMP : SInst<"vpminnm", "ddd", "fQfQd">; 784 785//////////////////////////////////////////////////////////////////////////////// 786// Pairwise Addition 787// With additional Qc Qs Qi QUc QUs QUi Qf Qd types. 788def ADDP : IInst<"vpadd", "ddd", "csiUcUsUifQcQsQiQlQUcQUsQUiQUlQfQd">; 789 790//////////////////////////////////////////////////////////////////////////////// 791// Shifts by constant 792let isShift = 1 in { 793// Left shift long high 794def SHLL_HIGH_N : SOpInst<"vshll_high_n", "ndi", "HcHsHiHUcHUsHUi", 795 OP_LONG_HI>; 796 797//////////////////////////////////////////////////////////////////////////////// 798// Shifts with insert, with additional Ql, QPl type. 799def SRI_N : WInst<"vsri_n", "dddi", 800 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPsPlQPl">; 801def SLI_N : WInst<"vsli_n", "dddi", 802 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPsPlQPl">; 803 804// Right shift narrow high 805def SHRN_HIGH_N : IOpInst<"vshrn_high_n", "hmdi", 806 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 807def QSHRUN_HIGH_N : SOpInst<"vqshrun_high_n", "hmdi", 808 "HsHiHl", OP_NARROW_HI>; 809def RSHRN_HIGH_N : IOpInst<"vrshrn_high_n", "hmdi", 810 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 811def QRSHRUN_HIGH_N : SOpInst<"vqrshrun_high_n", "hmdi", 812 "HsHiHl", OP_NARROW_HI>; 813def QSHRN_HIGH_N : SOpInst<"vqshrn_high_n", "hmdi", 814 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 815def QRSHRN_HIGH_N : SOpInst<"vqrshrn_high_n", "hmdi", 816 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 817} 818 819//////////////////////////////////////////////////////////////////////////////// 820// Converting vectors 821def VMOVL_HIGH : SOpInst<"vmovl_high", "nd", "HcHsHiHUcHUsHUi", OP_MOVL_HI>; 822 823let isVCVT_N = 1 in { 824def CVTF_N_F64 : SInst<"vcvt_n_f64", "Fdi", "lUlQlQUl">; 825def FCVTZS_N_S64 : SInst<"vcvt_n_s64", "xdi", "dQd">; 826def FCVTZS_N_U64 : SInst<"vcvt_n_u64", "udi", "dQd">; 827} 828 829//////////////////////////////////////////////////////////////////////////////// 830// 3VDiff class using high 64-bit in operands 831def VADDL_HIGH : SOpInst<"vaddl_high", "wkk", "csiUcUsUi", OP_ADDLHi>; 832def VADDW_HIGH : SOpInst<"vaddw_high", "wwk", "csiUcUsUi", OP_ADDWHi>; 833def VSUBL_HIGH : SOpInst<"vsubl_high", "wkk", "csiUcUsUi", OP_SUBLHi>; 834def VSUBW_HIGH : SOpInst<"vsubw_high", "wwk", "csiUcUsUi", OP_SUBWHi>; 835 836def VABDL_HIGH : SOpInst<"vabdl_high", "wkk", "csiUcUsUi", OP_ABDLHi>; 837def VABAL_HIGH : SOpInst<"vabal_high", "wwkk", "csiUcUsUi", OP_ABALHi>; 838 839def VMULL_HIGH : SOpInst<"vmull_high", "wkk", "csiUcUsUiPc", OP_MULLHi>; 840def VMULL_HIGH_N : SOpInst<"vmull_high_n", "wks", "siUsUi", OP_MULLHi_N>; 841def VMLAL_HIGH : SOpInst<"vmlal_high", "wwkk", "csiUcUsUi", OP_MLALHi>; 842def VMLAL_HIGH_N : SOpInst<"vmlal_high_n", "wwks", "siUsUi", OP_MLALHi_N>; 843def VMLSL_HIGH : SOpInst<"vmlsl_high", "wwkk", "csiUcUsUi", OP_MLSLHi>; 844def VMLSL_HIGH_N : SOpInst<"vmlsl_high_n", "wwks", "siUsUi", OP_MLSLHi_N>; 845 846def VADDHN_HIGH : SOpInst<"vaddhn_high", "qhkk", "silUsUiUl", OP_ADDHNHi>; 847def VRADDHN_HIGH : SOpInst<"vraddhn_high", "qhkk", "silUsUiUl", OP_RADDHNHi>; 848def VSUBHN_HIGH : SOpInst<"vsubhn_high", "qhkk", "silUsUiUl", OP_SUBHNHi>; 849def VRSUBHN_HIGH : SOpInst<"vrsubhn_high", "qhkk", "silUsUiUl", OP_RSUBHNHi>; 850 851def VQDMULL_HIGH : SOpInst<"vqdmull_high", "wkk", "si", OP_QDMULLHi>; 852def VQDMULL_HIGH_N : SOpInst<"vqdmull_high_n", "wks", "si", OP_QDMULLHi_N>; 853def VQDMLAL_HIGH : SOpInst<"vqdmlal_high", "wwkk", "si", OP_QDMLALHi>; 854def VQDMLAL_HIGH_N : SOpInst<"vqdmlal_high_n", "wwks", "si", OP_QDMLALHi_N>; 855def VQDMLSL_HIGH : SOpInst<"vqdmlsl_high", "wwkk", "si", OP_QDMLSLHi>; 856def VQDMLSL_HIGH_N : SOpInst<"vqdmlsl_high_n", "wwks", "si", OP_QDMLSLHi_N>; 857 858//////////////////////////////////////////////////////////////////////////////// 859// Extract or insert element from vector 860def GET_LANE : IInst<"vget_lane", "sdi", 861 "csilPcPsUcUsUiUlQcQsQiQlQUcQUsQUiQUlPcPsQPcQPsfdQfQdPlQPl">; 862def SET_LANE : IInst<"vset_lane", "dsdi", 863 "csilPcPsUcUsUiUlQcQsQiQlQUcQUsQUiQUlPcPsQPcQPsfdQfQdPlQPl">; 864def COPY_LANE : IOpInst<"vcopy_lane", "ddidi", 865 "csilPcPsUcUsUiUlPcPsPlfd", OP_COPY_LN>; 866def COPYQ_LANE : IOpInst<"vcopy_lane", "ddigi", 867 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPYQ_LN>; 868def COPY_LANEQ : IOpInst<"vcopy_laneq", "ddiki", 869 "csilPcPsPlUcUsUiUlfd", OP_COPY_LNQ>; 870def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "ddidi", 871 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>; 872 873//////////////////////////////////////////////////////////////////////////////// 874// Set all lanes to same value 875def VDUP_LANE1: WOpInst<"vdup_lane", "dgi", 876 "csilPcPsUcUsUiUlhfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl", 877 OP_DUP_LN>; 878def VDUP_LANE2: WOpInst<"vdup_laneq", "dki", 879 "csilPcPsUcUsUiUlhfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl", 880 OP_DUP_LN>; 881def DUP_N : WOpInst<"vdup_n", "ds", 882 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUldQdPlQPl", 883 OP_DUP>; 884def MOV_N : WOpInst<"vmov_n", "ds", 885 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUldQd", 886 OP_DUP>; 887 888//////////////////////////////////////////////////////////////////////////////// 889// Combining vectors, with additional Pl 890def COMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfdUcUsUiUlPcPsPl", OP_CONC>; 891 892//////////////////////////////////////////////////////////////////////////////// 893//Initialize a vector from bit pattern, with additional Pl 894def CREATE : NoTestOpInst<"vcreate", "dl", "csihfdUcUsUiUlPcPslPl", OP_CAST>; 895 896//////////////////////////////////////////////////////////////////////////////// 897 898def VMLA_LANEQ : IOpInst<"vmla_laneq", "dddji", 899 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 900def VMLS_LANEQ : IOpInst<"vmls_laneq", "dddji", 901 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 902 903def VFMA_LANE : IInst<"vfma_lane", "dddgi", "fdQfQd">; 904def VFMA_LANEQ : IInst<"vfma_laneq", "dddji", "fdQfQd">; 905def VFMS_LANE : IOpInst<"vfms_lane", "dddgi", "fdQfQd", OP_FMS_LN>; 906def VFMS_LANEQ : IOpInst<"vfms_laneq", "dddji", "fdQfQd", OP_FMS_LNQ>; 907 908def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "wwdki", "siUsUi", OP_MLAL_LN>; 909def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "wwkdi", "siUsUi", 910 OP_MLALHi_LN>; 911def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "wwkki", "siUsUi", 912 OP_MLALHi_LN>; 913def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "wwdki", "siUsUi", OP_MLSL_LN>; 914def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "wwkdi", "siUsUi", 915 OP_MLSLHi_LN>; 916def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "wwkki", "siUsUi", 917 OP_MLSLHi_LN>; 918 919def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "wwdki", "si", OP_QDMLAL_LN>; 920def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "wwkdi", "si", 921 OP_QDMLALHi_LN>; 922def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "wwkki", "si", 923 OP_QDMLALHi_LN>; 924def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "wwdki", "si", OP_QDMLSL_LN>; 925def VQDMLSL_HIGH_LANE : SOpInst<"vqdmlsl_high_lane", "wwkdi", "si", 926 OP_QDMLSLHi_LN>; 927def VQDMLSL_HIGH_LANEQ : SOpInst<"vqdmlsl_high_laneq", "wwkki", "si", 928 OP_QDMLSLHi_LN>; 929 930// Newly add double parameter for vmul_lane in aarch64 931// Note: d type is handled by SCALAR_VMUL_LANE 932def VMUL_LANE_A64 : IOpInst<"vmul_lane", "ddgi", "Qd", OP_MUL_LN>; 933 934// Note: d type is handled by SCALAR_VMUL_LANEQ 935def VMUL_LANEQ : IOpInst<"vmul_laneq", "ddji", 936 "sifUsUiQsQiQfQUsQUiQfQd", OP_MUL_LN>; 937def VMULL_LANEQ : SOpInst<"vmull_laneq", "wdki", "siUsUi", OP_MULL_LN>; 938def VMULL_HIGH_LANE : SOpInst<"vmull_high_lane", "wkdi", "siUsUi", 939 OP_MULLHi_LN>; 940def VMULL_HIGH_LANEQ : SOpInst<"vmull_high_laneq", "wkki", "siUsUi", 941 OP_MULLHi_LN>; 942 943def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "wdki", "si", OP_QDMULL_LN>; 944def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane", "wkdi", "si", 945 OP_QDMULLHi_LN>; 946def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "wkki", "si", 947 OP_QDMULLHi_LN>; 948 949def VQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ddji", "siQsQi", OP_QDMULH_LN>; 950def VQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ddji", "siQsQi", OP_QRDMULH_LN>; 951 952// Note: d type implemented by SCALAR_VMULX_LANE 953def VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "fQfQd", OP_MULX_LN>; 954// Note: d type is implemented by SCALAR_VMULX_LANEQ 955def VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "fQfQd", OP_MULX_LN>; 956 957//////////////////////////////////////////////////////////////////////////////// 958// Across vectors class 959def VADDLV : SInst<"vaddlv", "rd", "csiUcUsUiQcQsQiQUcQUsQUi">; 960def VMAXV : SInst<"vmaxv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">; 961def VMINV : SInst<"vminv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">; 962def VADDV : SInst<"vaddv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQdQlQUl">; 963def FMAXNMV : SInst<"vmaxnmv", "sd", "fQfQd">; 964def FMINNMV : SInst<"vminnmv", "sd", "fQfQd">; 965 966//////////////////////////////////////////////////////////////////////////////// 967// Newly added Vector Extract for f64 968def VEXT_A64 : WInst<"vext", "dddi", 969 "cUcPcsUsPsiUilUlfdQcQUcQPcQsQUsQPsQiQUiQlQUlQfQdPlQPl">; 970 971//////////////////////////////////////////////////////////////////////////////// 972// Crypto 973let isCrypto = 1 in { 974def AESE : SInst<"vaese", "ddd", "QUc">; 975def AESD : SInst<"vaesd", "ddd", "QUc">; 976def AESMC : SInst<"vaesmc", "dd", "QUc">; 977def AESIMC : SInst<"vaesimc", "dd", "QUc">; 978 979def SHA1H : SInst<"vsha1h", "ss", "Ui">; 980def SHA1SU1 : SInst<"vsha1su1", "ddd", "QUi">; 981def SHA256SU0 : SInst<"vsha256su0", "ddd", "QUi">; 982 983def SHA1C : SInst<"vsha1c", "ddsd", "QUi">; 984def SHA1P : SInst<"vsha1p", "ddsd", "QUi">; 985def SHA1M : SInst<"vsha1m", "ddsd", "QUi">; 986def SHA1SU0 : SInst<"vsha1su0", "dddd", "QUi">; 987def SHA256H : SInst<"vsha256h", "dddd", "QUi">; 988def SHA256H2 : SInst<"vsha256h2", "dddd", "QUi">; 989def SHA256SU1 : SInst<"vsha256su1", "dddd", "QUi">; 990} 991 992//////////////////////////////////////////////////////////////////////////////// 993// Permutation 994def VTRN1 : SOpInst<"vtrn1", "ddd", 995 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN1>; 996def VZIP1 : SOpInst<"vzip1", "ddd", 997 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP1>; 998def VUZP1 : SOpInst<"vuzp1", "ddd", 999 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP1>; 1000def VTRN2 : SOpInst<"vtrn2", "ddd", 1001 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN2>; 1002def VZIP2 : SOpInst<"vzip2", "ddd", 1003 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP2>; 1004def VUZP2 : SOpInst<"vuzp2", "ddd", 1005 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP2>; 1006 1007//////////////////////////////////////////////////////////////////////////////// 1008// Table lookup 1009let InstName = "vtbl" in { 1010def VQTBL1_A64 : WInst<"vqtbl1", "djt", "UccPcQUcQcQPc">; 1011def VQTBL2_A64 : WInst<"vqtbl2", "dBt", "UccPcQUcQcQPc">; 1012def VQTBL3_A64 : WInst<"vqtbl3", "dCt", "UccPcQUcQcQPc">; 1013def VQTBL4_A64 : WInst<"vqtbl4", "dDt", "UccPcQUcQcQPc">; 1014} 1015let InstName = "vtbx" in { 1016def VQTBX1_A64 : WInst<"vqtbx1", "ddjt", "UccPcQUcQcQPc">; 1017def VQTBX2_A64 : WInst<"vqtbx2", "ddBt", "UccPcQUcQcQPc">; 1018def VQTBX3_A64 : WInst<"vqtbx3", "ddCt", "UccPcQUcQcQPc">; 1019def VQTBX4_A64 : WInst<"vqtbx4", "ddDt", "UccPcQUcQcQPc">; 1020} 1021 1022//////////////////////////////////////////////////////////////////////////////// 1023// Vector reinterpret cast operations 1024// With additional d, Qd, pl, Qpl types 1025def REINTERPRET 1026 : NoTestOpInst<"vreinterpret", "dd", 1027 "csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPl", OP_REINT>; 1028 1029 1030//////////////////////////////////////////////////////////////////////////////// 1031// Scalar Intrinsics 1032// Scalar Arithmetic 1033 1034// Scalar Addition 1035def SCALAR_ADD : SInst<"vadd", "sss", "SlSUl">; 1036// Scalar Saturating Add 1037def SCALAR_QADD : SInst<"vqadd", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1038 1039// Scalar Subtraction 1040def SCALAR_SUB : SInst<"vsub", "sss", "SlSUl">; 1041// Scalar Saturating Sub 1042def SCALAR_QSUB : SInst<"vqsub", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1043 1044let InstName = "vmov" in { 1045def VGET_HIGH_A64 : NoTestOpInst<"vget_high", "dk", "csilhfdUcUsUiUlPcPsPl", 1046 OP_HI>; 1047def VGET_LOW_A64 : NoTestOpInst<"vget_low", "dk", "csilhfdUcUsUiUlPcPsPl", 1048 OP_LO>; 1049} 1050 1051//////////////////////////////////////////////////////////////////////////////// 1052// Scalar Shift 1053// Scalar Shift Left 1054def SCALAR_SHL: SInst<"vshl", "sss", "SlSUl">; 1055// Scalar Saturating Shift Left 1056def SCALAR_QSHL: SInst<"vqshl", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1057// Scalar Saturating Rounding Shift Left 1058def SCALAR_QRSHL: SInst<"vqrshl", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1059// Scalar Shift Rouding Left 1060def SCALAR_RSHL: SInst<"vrshl", "sss", "SlSUl">; 1061 1062//////////////////////////////////////////////////////////////////////////////// 1063// Scalar Shift (Immediate) 1064let isScalarShift = 1 in { 1065// Signed/Unsigned Shift Right (Immediate) 1066def SCALAR_SSHR_N: SInst<"vshr_n", "ssi", "SlSUl">; 1067// Signed/Unsigned Rounding Shift Right (Immediate) 1068def SCALAR_SRSHR_N: SInst<"vrshr_n", "ssi", "SlSUl">; 1069 1070// Signed/Unsigned Shift Right and Accumulate (Immediate) 1071def SCALAR_SSRA_N: SInst<"vsra_n", "sssi", "SlSUl">; 1072// Signed/Unsigned Rounding Shift Right and Accumulate (Immediate) 1073def SCALAR_SRSRA_N: SInst<"vrsra_n", "sssi", "SlSUl">; 1074 1075// Shift Left (Immediate) 1076def SCALAR_SHL_N: SInst<"vshl_n", "ssi", "SlSUl">; 1077// Signed/Unsigned Saturating Shift Left (Immediate) 1078def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">; 1079// Signed Saturating Shift Left Unsigned (Immediate) 1080def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">; 1081 1082// Shift Right And Insert (Immediate) 1083def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">; 1084// Shift Left And Insert (Immediate) 1085def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">; 1086 1087let isScalarNarrowShift = 1 in { 1088 // Signed/Unsigned Saturating Shift Right Narrow (Immediate) 1089 def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">; 1090 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate) 1091 def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "zsi", "SsSiSlSUsSUiSUl">; 1092 // Signed Saturating Shift Right Unsigned Narrow (Immediate) 1093 def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "zsi", "SsSiSl">; 1094 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate) 1095 def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "zsi", "SsSiSl">; 1096} 1097 1098//////////////////////////////////////////////////////////////////////////////// 1099// Scalar Signed/Unsigned Fixed-point Convert To Floating-Point (Immediate) 1100def SCALAR_SCVTF_N_F32: SInst<"vcvt_n_f32", "ysi", "SiSUi">; 1101def SCALAR_SCVTF_N_F64: SInst<"vcvt_n_f64", "osi", "SlSUl">; 1102 1103//////////////////////////////////////////////////////////////////////////////// 1104// Scalar Floating-point Convert To Signed/Unsigned Fixed-point (Immediate) 1105def SCALAR_FCVTZS_N_S32 : SInst<"vcvt_n_s32", "$si", "Sf">; 1106def SCALAR_FCVTZU_N_U32 : SInst<"vcvt_n_u32", "bsi", "Sf">; 1107def SCALAR_FCVTZS_N_S64 : SInst<"vcvt_n_s64", "$si", "Sd">; 1108def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "bsi", "Sd">; 1109} 1110 1111//////////////////////////////////////////////////////////////////////////////// 1112// Scalar Reduce Pairwise Addition (Scalar and Floating Point) 1113def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHdSHUl">; 1114 1115//////////////////////////////////////////////////////////////////////////////// 1116// Scalar Reduce Floating Point Pairwise Max/Min 1117def SCALAR_FMAXP : SInst<"vpmax", "sd", "SfSQd">; 1118 1119def SCALAR_FMINP : SInst<"vpmin", "sd", "SfSQd">; 1120 1121//////////////////////////////////////////////////////////////////////////////// 1122// Scalar Reduce Floating Point Pairwise maxNum/minNum 1123def SCALAR_FMAXNMP : SInst<"vpmaxnm", "sd", "SfSQd">; 1124def SCALAR_FMINNMP : SInst<"vpminnm", "sd", "SfSQd">; 1125 1126//////////////////////////////////////////////////////////////////////////////// 1127// Scalar Integer Saturating Doubling Multiply Half High 1128def SCALAR_SQDMULH : SInst<"vqdmulh", "sss", "SsSi">; 1129 1130//////////////////////////////////////////////////////////////////////////////// 1131// Scalar Integer Saturating Rounding Doubling Multiply Half High 1132def SCALAR_SQRDMULH : SInst<"vqrdmulh", "sss", "SsSi">; 1133 1134//////////////////////////////////////////////////////////////////////////////// 1135// Scalar Floating-point Multiply Extended 1136def SCALAR_FMULX : IInst<"vmulx", "sss", "SfSd">; 1137 1138//////////////////////////////////////////////////////////////////////////////// 1139// Scalar Floating-point Reciprocal Step 1140def SCALAR_FRECPS : IInst<"vrecps", "sss", "SfSd">; 1141 1142//////////////////////////////////////////////////////////////////////////////// 1143// Scalar Floating-point Reciprocal Square Root Step 1144def SCALAR_FRSQRTS : IInst<"vrsqrts", "sss", "SfSd">; 1145 1146//////////////////////////////////////////////////////////////////////////////// 1147// Scalar Signed Integer Convert To Floating-point 1148def SCALAR_SCVTFS : SInst<"vcvt_f32", "ys", "Si">; 1149def SCALAR_SCVTFD : SInst<"vcvt_f64", "os", "Sl">; 1150 1151//////////////////////////////////////////////////////////////////////////////// 1152// Scalar Unsigned Integer Convert To Floating-point 1153def SCALAR_UCVTFS : SInst<"vcvt_f32", "ys", "SUi">; 1154def SCALAR_UCVTFD : SInst<"vcvt_f64", "os", "SUl">; 1155 1156//////////////////////////////////////////////////////////////////////////////// 1157// Scalar Floating-point Converts 1158def SCALAR_FCVTXN : IInst<"vcvtx_f32", "ys", "Sd">; 1159def SCALAR_FCVTNSS : SInst<"vcvtn_s32", "$s", "Sf">; 1160def SCALAR_FCVTNUS : SInst<"vcvtn_u32", "bs", "Sf">; 1161def SCALAR_FCVTNSD : SInst<"vcvtn_s64", "$s", "Sd">; 1162def SCALAR_FCVTNUD : SInst<"vcvtn_u64", "bs", "Sd">; 1163def SCALAR_FCVTMSS : SInst<"vcvtm_s32", "$s", "Sf">; 1164def SCALAR_FCVTMUS : SInst<"vcvtm_u32", "bs", "Sf">; 1165def SCALAR_FCVTMSD : SInst<"vcvtm_s64", "$s", "Sd">; 1166def SCALAR_FCVTMUD : SInst<"vcvtm_u64", "bs", "Sd">; 1167def SCALAR_FCVTASS : SInst<"vcvta_s32", "$s", "Sf">; 1168def SCALAR_FCVTAUS : SInst<"vcvta_u32", "bs", "Sf">; 1169def SCALAR_FCVTASD : SInst<"vcvta_s64", "$s", "Sd">; 1170def SCALAR_FCVTAUD : SInst<"vcvta_u64", "bs", "Sd">; 1171def SCALAR_FCVTPSS : SInst<"vcvtp_s32", "$s", "Sf">; 1172def SCALAR_FCVTPUS : SInst<"vcvtp_u32", "bs", "Sf">; 1173def SCALAR_FCVTPSD : SInst<"vcvtp_s64", "$s", "Sd">; 1174def SCALAR_FCVTPUD : SInst<"vcvtp_u64", "bs", "Sd">; 1175def SCALAR_FCVTZSS : SInst<"vcvt_s32", "$s", "Sf">; 1176def SCALAR_FCVTZUS : SInst<"vcvt_u32", "bs", "Sf">; 1177def SCALAR_FCVTZSD : SInst<"vcvt_s64", "$s", "Sd">; 1178def SCALAR_FCVTZUD : SInst<"vcvt_u64", "bs", "Sd">; 1179 1180//////////////////////////////////////////////////////////////////////////////// 1181// Scalar Floating-point Reciprocal Estimate 1182def SCALAR_FRECPE : IInst<"vrecpe", "ss", "SfSd">; 1183 1184//////////////////////////////////////////////////////////////////////////////// 1185// Scalar Floating-point Reciprocal Exponent 1186def SCALAR_FRECPX : IInst<"vrecpx", "ss", "SfSd">; 1187 1188//////////////////////////////////////////////////////////////////////////////// 1189// Scalar Floating-point Reciprocal Square Root Estimate 1190def SCALAR_FRSQRTE : IInst<"vrsqrte", "ss", "SfSd">; 1191 1192//////////////////////////////////////////////////////////////////////////////// 1193// Scalar Integer Comparison 1194def SCALAR_CMEQ : SInst<"vceq", "sss", "SlSUl">; 1195def SCALAR_CMEQZ : SInst<"vceqz", "ss", "SlSUl">; 1196def SCALAR_CMGE : SInst<"vcge", "sss", "Sl">; 1197def SCALAR_CMGEZ : SInst<"vcgez", "ss", "Sl">; 1198def SCALAR_CMHS : SInst<"vcge", "sss", "SUl">; 1199def SCALAR_CMLE : SInst<"vcle", "sss", "SlSUl">; 1200def SCALAR_CMLEZ : SInst<"vclez", "ss", "Sl">; 1201def SCALAR_CMLT : SInst<"vclt", "sss", "SlSUl">; 1202def SCALAR_CMLTZ : SInst<"vcltz", "ss", "Sl">; 1203def SCALAR_CMGT : SInst<"vcgt", "sss", "Sl">; 1204def SCALAR_CMGTZ : SInst<"vcgtz", "ss", "Sl">; 1205def SCALAR_CMHI : SInst<"vcgt", "sss", "SUl">; 1206def SCALAR_CMTST : SInst<"vtst", "sss", "SlSUl">; 1207 1208//////////////////////////////////////////////////////////////////////////////// 1209// Scalar Floating-point Comparison 1210def SCALAR_FCMEQ : IInst<"vceq", "bss", "SfSd">; 1211def SCALAR_FCMEQZ : IInst<"vceqz", "bs", "SfSd">; 1212def SCALAR_FCMGE : IInst<"vcge", "bss", "SfSd">; 1213def SCALAR_FCMGEZ : IInst<"vcgez", "bs", "SfSd">; 1214def SCALAR_FCMGT : IInst<"vcgt", "bss", "SfSd">; 1215def SCALAR_FCMGTZ : IInst<"vcgtz", "bs", "SfSd">; 1216def SCALAR_FCMLE : IInst<"vcle", "bss", "SfSd">; 1217def SCALAR_FCMLEZ : IInst<"vclez", "bs", "SfSd">; 1218def SCALAR_FCMLT : IInst<"vclt", "bss", "SfSd">; 1219def SCALAR_FCMLTZ : IInst<"vcltz", "bs", "SfSd">; 1220 1221//////////////////////////////////////////////////////////////////////////////// 1222// Scalar Floating-point Absolute Compare Mask Greater Than Or Equal 1223def SCALAR_FACGE : IInst<"vcage", "bss", "SfSd">; 1224def SCALAR_FACLE : IInst<"vcale", "bss", "SfSd">; 1225 1226//////////////////////////////////////////////////////////////////////////////// 1227// Scalar Floating-point Absolute Compare Mask Greater Than 1228def SCALAR_FACGT : IInst<"vcagt", "bss", "SfSd">; 1229def SCALAR_FACLT : IInst<"vcalt", "bss", "SfSd">; 1230 1231//////////////////////////////////////////////////////////////////////////////// 1232// Scalar Absolute Value 1233def SCALAR_ABS : SInst<"vabs", "ss", "Sl">; 1234 1235//////////////////////////////////////////////////////////////////////////////// 1236// Scalar Absolute Difference 1237def SCALAR_ABD : IInst<"vabd", "sss", "SfSd">; 1238 1239//////////////////////////////////////////////////////////////////////////////// 1240// Scalar Signed Saturating Absolute Value 1241def SCALAR_SQABS : SInst<"vqabs", "ss", "ScSsSiSl">; 1242 1243//////////////////////////////////////////////////////////////////////////////// 1244// Scalar Negate 1245def SCALAR_NEG : SInst<"vneg", "ss", "Sl">; 1246 1247//////////////////////////////////////////////////////////////////////////////// 1248// Scalar Signed Saturating Negate 1249def SCALAR_SQNEG : SInst<"vqneg", "ss", "ScSsSiSl">; 1250 1251//////////////////////////////////////////////////////////////////////////////// 1252// Scalar Signed Saturating Accumulated of Unsigned Value 1253def SCALAR_SUQADD : SInst<"vuqadd", "sss", "ScSsSiSl">; 1254 1255//////////////////////////////////////////////////////////////////////////////// 1256// Scalar Unsigned Saturating Accumulated of Signed Value 1257def SCALAR_USQADD : SInst<"vsqadd", "sss", "SUcSUsSUiSUl">; 1258 1259//////////////////////////////////////////////////////////////////////////////// 1260// Signed Saturating Doubling Multiply-Add Long 1261def SCALAR_SQDMLAL : SInst<"vqdmlal", "rrss", "SsSi">; 1262 1263//////////////////////////////////////////////////////////////////////////////// 1264// Signed Saturating Doubling Multiply-Subtract Long 1265def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">; 1266 1267//////////////////////////////////////////////////////////////////////////////// 1268// Signed Saturating Doubling Multiply Long 1269def SCALAR_SQDMULL : SInst<"vqdmull", "rss", "SsSi">; 1270 1271//////////////////////////////////////////////////////////////////////////////// 1272// Scalar Signed Saturating Extract Unsigned Narrow 1273def SCALAR_SQXTUN : SInst<"vqmovun", "zs", "SsSiSl">; 1274 1275//////////////////////////////////////////////////////////////////////////////// 1276// Scalar Signed Saturating Extract Narrow 1277def SCALAR_SQXTN : SInst<"vqmovn", "zs", "SsSiSl">; 1278 1279//////////////////////////////////////////////////////////////////////////////// 1280// Scalar Unsigned Saturating Extract Narrow 1281def SCALAR_UQXTN : SInst<"vqmovn", "zs", "SUsSUiSUl">; 1282 1283// Scalar Floating Point multiply (scalar, by element) 1284def SCALAR_FMUL_LANE : IOpInst<"vmul_lane", "ssdi", "SfSd", OP_SCALAR_MUL_LN>; 1285def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "ssji", "SfSd", OP_SCALAR_MUL_LNQ>; 1286 1287// Scalar Floating Point multiply extended (scalar, by element) 1288def SCALAR_FMULX_LANE : IOpInst<"vmulx_lane", "ssdi", "SfSd", OP_SCALAR_MULX_LN>; 1289def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "ssji", "SfSd", OP_SCALAR_MULX_LNQ>; 1290 1291def SCALAR_VMUL_N : IInst<"vmul_n", "dds", "d">; 1292 1293// VMUL_LANE_A64 d type implemented using scalar mul lane 1294def SCALAR_VMUL_LANE : IInst<"vmul_lane", "ddgi", "d">; 1295 1296// VMUL_LANEQ d type implemented using scalar mul lane 1297def SCALAR_VMUL_LANEQ : IInst<"vmul_laneq", "ddji", "d">; 1298 1299// VMULX_LANE d type implemented using scalar vmulx_lane 1300def SCALAR_VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "d", OP_SCALAR_VMULX_LN>; 1301 1302// VMULX_LANEQ d type implemented using scalar vmulx_laneq 1303def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "d", OP_SCALAR_VMULX_LNQ>; 1304 1305// Scalar Floating Point fused multiply-add (scalar, by element) 1306def SCALAR_FMLA_LANE : IInst<"vfma_lane", "sssdi", "SfSd">; 1307def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "sssji", "SfSd">; 1308 1309// Scalar Floating Point fused multiply-subtract (scalar, by element) 1310def SCALAR_FMLS_LANE : IOpInst<"vfms_lane", "sssdi", "SfSd", OP_FMS_LN>; 1311def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "sssji", "SfSd", OP_FMS_LNQ>; 1312 1313// Signed Saturating Doubling Multiply Long (scalar by element) 1314def SCALAR_SQDMULL_LANE : SOpInst<"vqdmull_lane", "rsdi", "SsSi", OP_SCALAR_QDMULL_LN>; 1315def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "rsji", "SsSi", OP_SCALAR_QDMULL_LNQ>; 1316 1317// Signed Saturating Doubling Multiply-Add Long (scalar by element) 1318def SCALAR_SQDMLAL_LANE : SInst<"vqdmlal_lane", "rrsdi", "SsSi">; 1319def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "rrsji", "SsSi">; 1320 1321// Signed Saturating Doubling Multiply-Subtract Long (scalar by element) 1322def SCALAR_SQDMLS_LANE : SInst<"vqdmlsl_lane", "rrsdi", "SsSi">; 1323def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "rrsji", "SsSi">; 1324 1325// Scalar Integer Saturating Doubling Multiply Half High (scalar by element) 1326def SCALAR_SQDMULH_LANE : SOpInst<"vqdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QDMULH_LN>; 1327def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QDMULH_LNQ>; 1328 1329// Scalar Integer Saturating Rounding Doubling Multiply Half High 1330def SCALAR_SQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QRDMULH_LN>; 1331def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QRDMULH_LNQ>; 1332 1333def SCALAR_VDUP_LANE : IInst<"vdup_lane", "sdi", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1334def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "sji", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1335 1336def SCALAR_GET_LANE : IOpInst<"vget_lane", "sdi", "hQh", OP_SCALAR_GET_LN>; 1337def SCALAR_SET_LANE : IOpInst<"vset_lane", "dsdi", "hQh", OP_SCALAR_SET_LN>; 1338} 1339