patch-r271024-llvm-r216989-r216990-fix-movw-armv6.diff revision 278716 
1Pull in r216989 from upstream llvm trunk (by Renato Golin):
2
3  MFV:  Only emit movw on ARMv6T2+
4
5Pull in r216990 from upstream llvm trunk (by Renato Golin):
6
7  Missing test from r216989
8
9Building for the FreeBSD default target ARMv6 was emitting movw ASM on certain
10test cases (found building qmake4/5 for ARM).  Don't do that, moreover, the AS
11in base doesn't understand this instruction for this target.  One would need
12to use --integrated-as to get this to build if desired.
13
14Introduced here: http://svnweb.freebsd.org/changeset/base/271025
15
16Index: lib/Target/ARM/ARMInstrInfo.td
17===================================================================
18--- lib/Target/ARM/ARMInstrInfo.td
19+++ lib/Target/ARM/ARMInstrInfo.td
20@@ -3248,7 +3248,8 @@
21 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
22              (SBCri   GPR:$src, so_imm_not:$imm)>;
23 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
24-             (SBCrr   GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
25+             (SBCrr   GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
26+             Requires<[IsARM, HasV6T2]>;
27 
28 // Note: These are implemented in C++ code, because they have to generate
29 // ADD/SUBrs instructions, which use a complex pattern that a xform function
30Index: test/CodeGen/ARM/carry.ll
31===================================================================
32--- test/CodeGen/ARM/carry.ll
33+++ test/CodeGen/ARM/carry.ll
34@@ -1,4 +1,4 @@
35-; RUN: llc < %s -march=arm | FileCheck %s
36+; RUN: llc < %s -mtriple=armv6t2-eabi | FileCheck %s
37 
38 define i64 @f1(i64 %a, i64 %b) {
39 ; CHECK-LABEL: f1:
40Index: test/CodeGen/ARM/pr18364-movw.ll
41===================================================================
42--- test/CodeGen/ARM/pr18364-movw.ll
43+++ test/CodeGen/ARM/pr18364-movw.ll
44@@ -0,0 +1,34 @@
45+; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
46+; RUN: llc < %s -mtriple=armv6   | FileCheck %s --check-prefix=V6
47+; RUN: llc < %s -mtriple=armv6t2 | FileCheck %s --check-prefix=V6T2
48+; RUN: llc < %s -mtriple=armv7   | FileCheck %s --check-prefix=V7
49+; PR18364
50+
51+define i64 @f() #0 {
52+entry:
53+; V5-NOT: movw
54+; V6-NOT: movw
55+; V6T2: movw
56+; V7: movw
57+  %y = alloca i64, align 8
58+  %z = alloca i64, align 8
59+  store i64 1, i64* %y, align 8
60+  store i64 11579764786944, i64* %z, align 8
61+  %0 = load i64* %y, align 8
62+  %1 = load i64* %z, align 8
63+  %sub = sub i64 %0, %1
64+  ret i64 %sub
65+}
66+
67+define i64 @g(i64 %a, i32 %b) #0 {
68+entry:
69+; V5-NOT: movw
70+; V6-NOT: movw
71+; V6T2: movw
72+; V7: movw
73+  %0 = mul i64 %a, 86400000
74+  %mul = add i64 %0, -210866803200000
75+  %conv = sext i32 %b to i64
76+  %add = add nsw i64 %mul, %conv
77+  ret i64 %add
78+}
79