patch-r263313-llvm-r203311-fix-sse1-oom.diff revision 269012 
1Pull in r203311 from upstream llvm trunk (by Arnold Schwaighofer):
2
3  ISel: Make VSELECT selection terminate in cases where the condition type has to
4  be split and the result type widened.
5
6  When the condition of a vselect has to be split it makes no sense widening the
7  vselect and thereby widening the condition. We end up in an endless loop of
8  widening (vselect result type) and splitting (condition mask type) doing this.
9  Instead, split both the condition and the vselect and widen the result.
10
11  I ran this over the test suite with i686 and mattr=+sse and saw no regressions.
12
13  Fixes PR18036.
14
15Introduced here: http://svnweb.freebsd.org/changeset/base/263313
16
17Index: test/CodeGen/X86/sse1.ll
18===================================================================
19--- test/CodeGen/X86/sse1.ll
20+++ test/CodeGen/X86/sse1.ll
21@@ -43,3 +43,17 @@ entry:
22 ; CHECK-NOT: shufps	$16
23 ; CHECK: ret
24 }
25+
26+; We used to get stuck in type legalization for this example when lowering the
27+; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type)
28+; is not. We used to ping pong between splitting the vselect for the v4i
29+; condition operand and widening the resulting vselect for the v4f32 result.
30+; PR18036
31+
32+; CHECK-LABEL: vselect
33+define <4 x float> @vselect(<4 x float>*%p, <4 x i32> %q) {
34+entry:
35+  %a1 = icmp eq <4 x i32> %q, zeroinitializer
36+  %a14 = select <4 x i1> %a1, <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+0> , <4 x float> zeroinitializer
37+  ret <4 x float> %a14
38+}
39Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
40===================================================================
41--- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
42+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
43@@ -2180,6 +2180,17 @@ SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNod
44     if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
45       Cond1 = GetWidenedVector(Cond1);
46 
47+    // If we have to split the condition there is no point in widening the
48+    // select. This would result in an cycle of widening the select ->
49+    // widening the condition operand -> splitting the condition operand ->
50+    // splitting the select -> widening the select. Instead split this select
51+    // further and widen the resulting type.
52+    if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
53+      SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
54+      SDValue Res = ModifyToType(SplitSelect, WidenVT);
55+      return Res;
56+    }
57+
58     if (Cond1.getValueType() != CondWidenVT)
59       Cond1 = ModifyToType(Cond1, CondWidenVT);
60   }
61