patch-r262261-llvm-r198740-sparc.diff revision 269012 
1Pull in r198740 from upstream llvm trunk (by Venkatraman Govindaraju):
2
3  [SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly. 
4
5Introduced here: http://svnweb.freebsd.org/changeset/base/262261
6
7Index: test/MC/Sparc/sparc64-alu-instructions.s
8===================================================================
9--- test/MC/Sparc/sparc64-alu-instructions.s
10+++ test/MC/Sparc/sparc64-alu-instructions.s
11@@ -0,0 +1,38 @@
12+! RUN: llvm-mc %s -triple=sparc64-unknown-linux-gnu -show-encoding | FileCheck %s
13+
14+        ! CHECK: sllx %g1, %i2, %i0  ! encoding: [0xb1,0x28,0x50,0x1a]
15+        sllx %g1, %i2, %i0
16+
17+        ! CHECK: sllx %g1, 63, %i0   ! encoding: [0xb1,0x28,0x70,0x3f]
18+        sllx %g1, 63, %i0
19+
20+        ! CHECK: srlx %g1, %i2, %i0  ! encoding: [0xb1,0x30,0x50,0x1a]
21+        srlx %g1, %i2, %i0
22+
23+        ! CHECK: srlx %g1, 63, %i0   ! encoding: [0xb1,0x30,0x70,0x3f]
24+        srlx %g1, 63, %i0
25+
26+        ! CHECK: srax %g1, %i2, %i0  ! encoding: [0xb1,0x38,0x50,0x1a]
27+        srax %g1, %i2, %i0
28+
29+        ! CHECK: srax %g1, 63, %i0   ! encoding: [0xb1,0x38,0x70,0x3f]
30+        srax %g1, 63, %i0
31+
32+        ! CHECK: mulx %g1, %i2, %i0  ! encoding: [0xb0,0x48,0x40,0x1a]
33+        mulx %g1, %i2, %i0
34+
35+        ! CHECK: mulx %g1, 63, %i0   ! encoding: [0xb0,0x48,0x60,0x3f]
36+        mulx %g1, 63, %i0
37+
38+        ! CHECK: sdivx %g1, %i2, %i0 ! encoding: [0xb1,0x68,0x40,0x1a]
39+        sdivx %g1, %i2, %i0
40+
41+        ! CHECK: sdivx %g1, 63, %i0  ! encoding: [0xb1,0x68,0x60,0x3f]
42+        sdivx %g1, 63, %i0
43+
44+        ! CHECK: udivx %g1, %i2, %i0 ! encoding: [0xb0,0x68,0x40,0x1a]
45+        udivx %g1, %i2, %i0
46+
47+        ! CHECK: udivx %g1, 63, %i0  ! encoding: [0xb0,0x68,0x60,0x3f]
48+        udivx %g1, 63, %i0
49+
50Index: lib/Target/Sparc/SparcInstr64Bit.td
51===================================================================
52--- lib/Target/Sparc/SparcInstr64Bit.td
53+++ lib/Target/Sparc/SparcInstr64Bit.td
54@@ -193,9 +193,9 @@ def MULXrr : F3_1<2, 0b001001,
55                   "mulx $rs1, $rs2, $rd",
56                   [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
57 def MULXri : F3_2<2, 0b001001,
58-                  (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
59-                  "mulx $rs1, $i, $rd",
60-                  [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$i)))]>;
61+                  (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
62+                  "mulx $rs1, $simm13, $rd",
63+                  [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
64 
65 // Division can trap.
66 let hasSideEffects = 1 in {
67@@ -204,9 +204,9 @@ def SDIVXrr : F3_1<2, 0b101101,
68                    "sdivx $rs1, $rs2, $rd",
69                    [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
70 def SDIVXri : F3_2<2, 0b101101,
71-                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
72-                   "sdivx $rs1, $i, $rd",
73-                   [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$i)))]>;
74+                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
75+                   "sdivx $rs1, $simm13, $rd",
76+                   [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;
77 
78 def UDIVXrr : F3_1<2, 0b001101,
79                    (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
80@@ -213,9 +213,9 @@ def UDIVXrr : F3_1<2, 0b001101,
81                    "udivx $rs1, $rs2, $rd",
82                    [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
83 def UDIVXri : F3_2<2, 0b001101,
84-                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
85-                   "udivx $rs1, $i, $rd",
86-                   [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$i)))]>;
87+                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
88+                   "udivx $rs1, $simm13, $rd",
89+                   [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
90 } // hasSideEffects = 1
91 
92 } // Predicates = [Is64Bit]
93Index: lib/Target/Sparc/SparcInstrFormats.td
94===================================================================
95--- lib/Target/Sparc/SparcInstrFormats.td
96+++ lib/Target/Sparc/SparcInstrFormats.td
97@@ -193,12 +193,12 @@ class F3_Si<bits<2> opVal, bits<6> op3val, bit xVa
98 // Define rr and ri shift instructions with patterns.
99 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
100                 ValueType VT, RegisterClass RC> {
101-  def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2),
102-                 !strconcat(OpcStr, " $rs, $rs2, $rd"),
103-                 [(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
104-  def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt),
105-                 !strconcat(OpcStr, " $rs, $shcnt, $rd"),
106-                 [(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
107+  def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
108+                 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
109+                 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
110+  def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
111+                 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
112+                 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
113 }
114 
115 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
116