XCoreISelDAGToDAG.cpp revision 263508
1184989Srafan//===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===// 250276Speter// 3176187Srafan// The LLVM Compiler Infrastructure 450276Speter// 550276Speter// This file is distributed under the University of Illinois Open Source 650276Speter// License. See LICENSE.TXT for details. 750276Speter// 850276Speter//===----------------------------------------------------------------------===// 950276Speter// 1050276Speter// This file defines an instruction selector for the XCore target. 1150276Speter// 1250276Speter//===----------------------------------------------------------------------===// 1350276Speter 1450276Speter#include "XCore.h" 1550276Speter#include "XCoreTargetMachine.h" 1650276Speter#include "llvm/CodeGen/MachineFrameInfo.h" 1750276Speter#include "llvm/CodeGen/MachineFunction.h" 1850276Speter#include "llvm/CodeGen/MachineInstrBuilder.h" 1950276Speter#include "llvm/CodeGen/MachineRegisterInfo.h" 2050276Speter#include "llvm/CodeGen/SelectionDAG.h" 2150276Speter#include "llvm/CodeGen/SelectionDAGISel.h" 2250276Speter#include "llvm/IR/CallingConv.h" 2350276Speter#include "llvm/IR/Constants.h" 2450276Speter#include "llvm/IR/DerivedTypes.h" 2550276Speter#include "llvm/IR/Function.h" 2650276Speter#include "llvm/IR/Intrinsics.h" 2750276Speter#include "llvm/IR/LLVMContext.h" 2850276Speter#include "llvm/Support/Compiler.h" 2950276Speter#include "llvm/Support/Debug.h" 30176187Srafan#include "llvm/Support/ErrorHandling.h" 3150276Speter#include "llvm/Support/raw_ostream.h" 3250276Speter#include "llvm/Target/TargetLowering.h" 3350276Speterusing namespace llvm; 3450276Speter 3550276Speter/// XCoreDAGToDAGISel - XCore specific code to select XCore machine 3650276Speter/// instructions for SelectionDAG operations. 37176187Srafan/// 3850276Speternamespace { 39176187Srafan class XCoreDAGToDAGISel : public SelectionDAGISel { 40176187Srafan const XCoreSubtarget &Subtarget; 41176187Srafan 42176187Srafan public: 43176187Srafan XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel) 44176187Srafan : SelectionDAGISel(TM, OptLevel), 4550276Speter Subtarget(*TM.getSubtargetImpl()) { } 4650276Speter 4750276Speter SDNode *Select(SDNode *N); 4850276Speter SDNode *SelectBRIND(SDNode *N); 49184989Srafan 5050276Speter /// getI32Imm - Return a target constant with the specified value, of type 51166124Srafan /// i32. 52174993Srafan inline SDValue getI32Imm(unsigned Imm) { 53174993Srafan return CurDAG->getTargetConstant(Imm, MVT::i32); 54174993Srafan } 55174993Srafan 56174993Srafan inline bool immMskBitp(SDNode *inN) const { 57174993Srafan ConstantSDNode *N = cast<ConstantSDNode>(inN); 58174993Srafan uint32_t value = (uint32_t)N->getZExtValue(); 5950276Speter if (!isMask_32(value)) { 6050276Speter return false; 61174993Srafan } 62174993Srafan int msksize = 32 - countLeadingZeros(value); 6350276Speter return (msksize >= 1 && msksize <= 8) || 64174993Srafan msksize == 16 || msksize == 24 || msksize == 32; 65174993Srafan } 66174993Srafan 67174993Srafan // Complex Pattern Selectors. 68174993Srafan bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset); 69174993Srafan 7050276Speter virtual const char *getPassName() const { 71174993Srafan return "XCore DAG->DAG Pattern Instruction Selection"; 72174993Srafan } 7350276Speter 74174993Srafan // Include the pieces autogenerated from the target description. 75174993Srafan #include "XCoreGenDAGISel.inc" 7662449Speter }; 77174993Srafan} // end anonymous namespace 78174993Srafan 79176187Srafan/// createXCoreISelDag - This pass converts a legalized DAG into a 80176187Srafan/// XCore-specific DAG, ready for instruction scheduling. 81176187Srafan/// 82176187SrafanFunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM, 83176187Srafan CodeGenOpt::Level OptLevel) { 84176187Srafan return new XCoreDAGToDAGISel(TM, OptLevel); 8550276Speter} 8650276Speter 87174993Srafanbool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, 88174993Srafan SDValue &Offset) { 8950276Speter FrameIndexSDNode *FIN = 0; 9050276Speter if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) { 9150276Speter Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 9250276Speter Offset = CurDAG->getTargetConstant(0, MVT::i32); 9350276Speter return true; 94174993Srafan } 95174993Srafan if (Addr.getOpcode() == ISD::ADD) { 96174993Srafan ConstantSDNode *CN = 0; 97174993Srafan if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) 98174993Srafan && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) 9950276Speter && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { 10050276Speter // Constant positive word offset from frame index 101174993Srafan Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 102166124Srafan Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); 10350276Speter return true; 104184989Srafan } 105174993Srafan } 106176187Srafan return false; 107174993Srafan} 108174993Srafan 109174993SrafanSDNode *XCoreDAGToDAGISel::Select(SDNode *N) { 110174993Srafan SDLoc dl(N); 111176187Srafan switch (N->getOpcode()) { 112166124Srafan default: break; 113174993Srafan case ISD::Constant: { 114174993Srafan uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue(); 115174993Srafan if (immMskBitp(N)) { 116166124Srafan // Transformation function: get the size of a mask 117174993Srafan // Look for the first non-zero bit 118166124Srafan SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val)); 119174993Srafan return CurDAG->getMachineNode(XCore::MKMSK_rus, dl, 120174993Srafan MVT::i32, MskSize); 121174993Srafan } 122174993Srafan else if (!isUInt<16>(Val)) { 123174993Srafan SDValue CPIdx = 124174993Srafan CurDAG->getTargetConstantPool(ConstantInt::get( 125174993Srafan Type::getInt32Ty(*CurDAG->getContext()), Val), 126174993Srafan getTargetLowering()->getPointerTy()); 127176187Srafan SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, 128174993Srafan MVT::Other, CPIdx, 129174993Srafan CurDAG->getEntryNode()); 130174993Srafan MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 131174993Srafan MemOp[0] = MF->getMachineMemOperand( 132174993Srafan MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad, 4, 4); 133174993Srafan cast<MachineSDNode>(node)->setMemRefs(MemOp, MemOp + 1); 134174993Srafan return node; 135174993Srafan } 136174993Srafan break; 137166124Srafan } 138166124Srafan case XCoreISD::LADD: { 139184989Srafan SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 140176187Srafan N->getOperand(2) }; 141166124Srafan return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, 142166124Srafan Ops); 143174993Srafan } 144174993Srafan case XCoreISD::LSUB: { 145174993Srafan SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 146174993Srafan N->getOperand(2) }; 147174993Srafan return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32, 148174993Srafan Ops); 149174993Srafan } 150176187Srafan case XCoreISD::MACCU: { 151176187Srafan SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 152176187Srafan N->getOperand(2), N->getOperand(3) }; 153176187Srafan return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32, 154176187Srafan Ops); 155184989Srafan } 156184989Srafan case XCoreISD::MACCS: { 157176187Srafan SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 158176187Srafan N->getOperand(2), N->getOperand(3) }; 159174993Srafan return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32, 160176187Srafan Ops); 161176187Srafan } 162176187Srafan case XCoreISD::LMUL: { 163176187Srafan SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 164184989Srafan N->getOperand(2), N->getOperand(3) }; 165184989Srafan return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32, 166184989Srafan Ops); 167176187Srafan } 168176187Srafan case XCoreISD::CRC8: { 169176187Srafan SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; 170176187Srafan return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32, 171176187Srafan Ops); 172176187Srafan } 173184989Srafan case ISD::BRIND: 174184989Srafan if (SDNode *ResNode = SelectBRIND(N)) 175184989Srafan return ResNode; 176176187Srafan break; 177176187Srafan // Other cases are autogenerated. 178176187Srafan } 179176187Srafan return SelectCode(N); 180176187Srafan} 181174993Srafan 182176187Srafan/// Given a chain return a new chain where any appearance of Old is replaced 183176187Srafan/// by New. There must be at most one instruction between Old and Chain and 184176187Srafan/// this instruction must be a TokenFactor. Returns an empty SDValue if 185176187Srafan/// these conditions don't hold. 186176187Srafanstatic SDValue 187184989SrafanreplaceInChain(SelectionDAG *CurDAG, SDValue Chain, SDValue Old, SDValue New) 188184989Srafan{ 189184989Srafan if (Chain == Old) 190184989Srafan return New; 191184989Srafan if (Chain->getOpcode() != ISD::TokenFactor) 19250276Speter return SDValue(); 193 SmallVector<SDValue, 8> Ops; 194 bool found = false; 195 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) { 196 if (Chain->getOperand(i) == Old) { 197 Ops.push_back(New); 198 found = true; 199 } else { 200 Ops.push_back(Chain->getOperand(i)); 201 } 202 } 203 if (!found) 204 return SDValue(); 205 return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, 206 &Ops[0], Ops.size()); 207} 208 209SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N) { 210 SDLoc dl(N); 211 // (brind (int_xcore_checkevent (addr))) 212 SDValue Chain = N->getOperand(0); 213 SDValue Addr = N->getOperand(1); 214 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN) 215 return 0; 216 unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue(); 217 if (IntNo != Intrinsic::xcore_checkevent) 218 return 0; 219 SDValue nextAddr = Addr->getOperand(2); 220 SDValue CheckEventChainOut(Addr.getNode(), 1); 221 if (!CheckEventChainOut.use_empty()) { 222 // If the chain out of the checkevent intrinsic is an operand of the 223 // indirect branch or used in a TokenFactor which is the operand of the 224 // indirect branch then build a new chain which uses the chain coming into 225 // the checkevent intrinsic instead. 226 SDValue CheckEventChainIn = Addr->getOperand(0); 227 SDValue NewChain = replaceInChain(CurDAG, Chain, CheckEventChainOut, 228 CheckEventChainIn); 229 if (!NewChain.getNode()) 230 return 0; 231 Chain = NewChain; 232 } 233 // Enable events on the thread using setsr 1 and then disable them immediately 234 // after with clrsr 1. If any resources owned by the thread are ready an event 235 // will be taken. If no resource is ready we branch to the address which was 236 // the operand to the checkevent intrinsic. 237 SDValue constOne = getI32Imm(1); 238 SDValue Glue = 239 SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue, 240 constOne, Chain), 0); 241 Glue = 242 SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue, 243 constOne, Glue), 0); 244 if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper && 245 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) { 246 return CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other, 247 nextAddr->getOperand(0), Glue); 248 } 249 return CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue); 250} 251