X86TargetMachine.cpp revision 263508 
1//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the X86 specific subclass of TargetMachine.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86TargetMachine.h"
15#include "X86.h"
16#include "llvm/CodeGen/MachineFunction.h"
17#include "llvm/CodeGen/Passes.h"
18#include "llvm/PassManager.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Support/FormattedStream.h"
21#include "llvm/Support/TargetRegistry.h"
22#include "llvm/Target/TargetOptions.h"
23using namespace llvm;
24
25extern "C" void LLVMInitializeX86Target() {
26  // Register the target.
27  RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
28  RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
29}
30
31void X86_32TargetMachine::anchor() { }
32
33X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
34                                         StringRef CPU, StringRef FS,
35                                         const TargetOptions &Options,
36                                         Reloc::Model RM, CodeModel::Model CM,
37                                         CodeGenOpt::Level OL)
38  : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
39    DL(getSubtargetImpl()->isTargetDarwin() ?
40               "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
41               "n8:16:32-S128" :
42               (getSubtargetImpl()->isTargetCygMing() ||
43                getSubtargetImpl()->isTargetWindows()) ?
44               "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-"
45               "n8:16:32-S32" :
46               "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-"
47               "n8:16:32-S128"),
48    InstrInfo(*this),
49    TLInfo(*this),
50    TSInfo(*this),
51    JITInfo(*this) {
52  initAsmInfo();
53}
54
55void X86_64TargetMachine::anchor() { }
56
57X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
58                                         StringRef CPU, StringRef FS,
59                                         const TargetOptions &Options,
60                                         Reloc::Model RM, CodeModel::Model CM,
61                                         CodeGenOpt::Level OL)
62  : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
63    // The x32 ABI dictates the ILP32 programming model for x64.
64    DL(getSubtargetImpl()->isTarget64BitILP32() ?
65        "e-p:32:32-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
66        "n8:16:32:64-S128" :
67        "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
68        "n8:16:32:64-S128"),
69    InstrInfo(*this),
70    TLInfo(*this),
71    TSInfo(*this),
72    JITInfo(*this) {
73  initAsmInfo();
74}
75
76/// X86TargetMachine ctor - Create an X86 target.
77///
78X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
79                                   StringRef CPU, StringRef FS,
80                                   const TargetOptions &Options,
81                                   Reloc::Model RM, CodeModel::Model CM,
82                                   CodeGenOpt::Level OL,
83                                   bool is64Bit)
84  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
85    Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
86    FrameLowering(*this, Subtarget),
87    InstrItins(Subtarget.getInstrItineraryData()){
88  // Determine the PICStyle based on the target selected.
89  if (getRelocationModel() == Reloc::Static) {
90    // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
91    Subtarget.setPICStyle(PICStyles::None);
92  } else if (Subtarget.is64Bit()) {
93    // PIC in 64 bit mode is always rip-rel.
94    Subtarget.setPICStyle(PICStyles::RIPRel);
95  } else if (Subtarget.isTargetCOFF()) {
96    Subtarget.setPICStyle(PICStyles::None);
97  } else if (Subtarget.isTargetDarwin()) {
98    if (getRelocationModel() == Reloc::PIC_)
99      Subtarget.setPICStyle(PICStyles::StubPIC);
100    else {
101      assert(getRelocationModel() == Reloc::DynamicNoPIC);
102      Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
103    }
104  } else if (Subtarget.isTargetELF()) {
105    Subtarget.setPICStyle(PICStyles::GOT);
106  }
107
108  // default to hard float ABI
109  if (Options.FloatABIType == FloatABI::Default)
110    this->Options.FloatABIType = FloatABI::Hard;
111}
112
113//===----------------------------------------------------------------------===//
114// Command line options for x86
115//===----------------------------------------------------------------------===//
116static cl::opt<bool>
117UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
118  cl::desc("Minimize AVX to SSE transition penalty"),
119  cl::init(true));
120
121// Temporary option to control early if-conversion for x86 while adding machine
122// models.
123static cl::opt<bool>
124X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
125	       cl::desc("Enable early if-conversion on X86"));
126
127//===----------------------------------------------------------------------===//
128// X86 Analysis Pass Setup
129//===----------------------------------------------------------------------===//
130
131void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
132  // Add first the target-independent BasicTTI pass, then our X86 pass. This
133  // allows the X86 pass to delegate to the target independent layer when
134  // appropriate.
135  PM.add(createBasicTargetTransformInfoPass(this));
136  PM.add(createX86TargetTransformInfoPass(this));
137}
138
139
140//===----------------------------------------------------------------------===//
141// Pass Pipeline Configuration
142//===----------------------------------------------------------------------===//
143
144namespace {
145/// X86 Code Generator Pass Configuration Options.
146class X86PassConfig : public TargetPassConfig {
147public:
148  X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
149    : TargetPassConfig(TM, PM) {}
150
151  X86TargetMachine &getX86TargetMachine() const {
152    return getTM<X86TargetMachine>();
153  }
154
155  const X86Subtarget &getX86Subtarget() const {
156    return *getX86TargetMachine().getSubtargetImpl();
157  }
158
159  virtual bool addInstSelector();
160  virtual bool addILPOpts();
161  virtual bool addPreRegAlloc();
162  virtual bool addPostRegAlloc();
163  virtual bool addPreEmitPass();
164};
165} // namespace
166
167TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
168  return new X86PassConfig(this, PM);
169}
170
171bool X86PassConfig::addInstSelector() {
172  // Install an instruction selector.
173  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
174
175  // For ELF, cleanup any local-dynamic TLS accesses.
176  if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
177    addPass(createCleanupLocalDynamicTLSPass());
178
179  // For 32-bit, prepend instructions to set the "global base reg" for PIC.
180  if (!getX86Subtarget().is64Bit())
181    addPass(createGlobalBaseRegPass());
182
183  return false;
184}
185
186bool X86PassConfig::addILPOpts() {
187  if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
188    addPass(&EarlyIfConverterID);
189    return true;
190  }
191  return false;
192}
193
194bool X86PassConfig::addPreRegAlloc() {
195  return false;  // -print-machineinstr shouldn't print after this.
196}
197
198bool X86PassConfig::addPostRegAlloc() {
199  addPass(createX86FloatingPointStackifierPass());
200  return true;  // -print-machineinstr should print after this.
201}
202
203bool X86PassConfig::addPreEmitPass() {
204  bool ShouldPrint = false;
205  if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
206    addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
207    ShouldPrint = true;
208  }
209
210  if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
211    addPass(createX86IssueVZeroUpperPass());
212    ShouldPrint = true;
213  }
214
215  if (getOptLevel() != CodeGenOpt::None &&
216      getX86Subtarget().padShortFunctions()) {
217    addPass(createX86PadShortFunctions());
218    ShouldPrint = true;
219  }
220  if (getOptLevel() != CodeGenOpt::None &&
221      getX86Subtarget().LEAusesAG()){
222    addPass(createX86FixupLEAs());
223    ShouldPrint = true;
224  }
225
226  return ShouldPrint;
227}
228
229bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
230                                      JITCodeEmitter &JCE) {
231  PM.add(createX86JITCodeEmitterPass(*this, JCE));
232
233  return false;
234}
235