X86Subtarget.h revision 263508 
1//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef X86SUBTARGET_H
15#define X86SUBTARGET_H
16
17#include "llvm/ADT/Triple.h"
18#include "llvm/IR/CallingConv.h"
19#include "llvm/Target/TargetSubtargetInfo.h"
20#include <string>
21
22#define GET_SUBTARGETINFO_HEADER
23#include "X86GenSubtargetInfo.inc"
24
25namespace llvm {
26class GlobalValue;
27class StringRef;
28class TargetMachine;
29
30/// PICStyles - The X86 backend supports a number of different styles of PIC.
31///
32namespace PICStyles {
33enum Style {
34  StubPIC,          // Used on i386-darwin in -fPIC mode.
35  StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36  GOT,              // Used on many 32-bit unices in -fPIC mode.
37  RIPRel,           // Used on X86-64 when not in -static mode.
38  None              // Set when in -static mode (not PIC or DynamicNoPIC mode).
39};
40}
41
42class X86Subtarget : public X86GenSubtargetInfo {
43protected:
44  enum X86SSEEnum {
45    NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
46  };
47
48  enum X863DNowEnum {
49    NoThreeDNow, ThreeDNow, ThreeDNowA
50  };
51
52  enum X86ProcFamilyEnum {
53    Others, IntelAtom, IntelSLM
54  };
55
56  /// X86ProcFamily - X86 processor family: Intel Atom, and others
57  X86ProcFamilyEnum X86ProcFamily;
58
59  /// PICStyle - Which PIC style to use
60  ///
61  PICStyles::Style PICStyle;
62
63  /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
64  /// none supported.
65  X86SSEEnum X86SSELevel;
66
67  /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
68  ///
69  X863DNowEnum X863DNowLevel;
70
71  /// HasCMov - True if this processor has conditional move instructions
72  /// (generally pentium pro+).
73  bool HasCMov;
74
75  /// HasX86_64 - True if the processor supports X86-64 instructions.
76  ///
77  bool HasX86_64;
78
79  /// HasPOPCNT - True if the processor supports POPCNT.
80  bool HasPOPCNT;
81
82  /// HasSSE4A - True if the processor supports SSE4A instructions.
83  bool HasSSE4A;
84
85  /// HasAES - Target has AES instructions
86  bool HasAES;
87
88  /// HasPCLMUL - Target has carry-less multiplication
89  bool HasPCLMUL;
90
91  /// HasFMA - Target has 3-operand fused multiply-add
92  bool HasFMA;
93
94  /// HasFMA4 - Target has 4-operand fused multiply-add
95  bool HasFMA4;
96
97  /// HasXOP - Target has XOP instructions
98  bool HasXOP;
99
100  /// HasTBM - Target has TBM instructions.
101  bool HasTBM;
102
103  /// HasMOVBE - True if the processor has the MOVBE instruction.
104  bool HasMOVBE;
105
106  /// HasRDRAND - True if the processor has the RDRAND instruction.
107  bool HasRDRAND;
108
109  /// HasF16C - Processor has 16-bit floating point conversion instructions.
110  bool HasF16C;
111
112  /// HasFSGSBase - Processor has FS/GS base insturctions.
113  bool HasFSGSBase;
114
115  /// HasLZCNT - Processor has LZCNT instruction.
116  bool HasLZCNT;
117
118  /// HasBMI - Processor has BMI1 instructions.
119  bool HasBMI;
120
121  /// HasBMI2 - Processor has BMI2 instructions.
122  bool HasBMI2;
123
124  /// HasRTM - Processor has RTM instructions.
125  bool HasRTM;
126
127  /// HasHLE - Processor has HLE.
128  bool HasHLE;
129
130  /// HasADX - Processor has ADX instructions.
131  bool HasADX;
132
133  /// HasSHA - Processor has SHA instructions.
134  bool HasSHA;
135
136  /// HasPRFCHW - Processor has PRFCHW instructions.
137  bool HasPRFCHW;
138
139  /// HasRDSEED - Processor has RDSEED instructions.
140  bool HasRDSEED;
141
142  /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
143  bool IsBTMemSlow;
144
145  /// IsUAMemFast - True if unaligned memory access is fast.
146  bool IsUAMemFast;
147
148  /// HasVectorUAMem - True if SIMD operations can have unaligned memory
149  /// operands. This may require setting a feature bit in the processor.
150  bool HasVectorUAMem;
151
152  /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
153  /// this is true for most x86-64 chips, but not the first AMD chips.
154  bool HasCmpxchg16b;
155
156  /// UseLeaForSP - True if the LEA instruction should be used for adjusting
157  /// the stack pointer. This is an optimization for Intel Atom processors.
158  bool UseLeaForSP;
159
160  /// HasSlowDivide - True if smaller divides are significantly faster than
161  /// full divides and should be used when possible.
162  bool HasSlowDivide;
163
164  /// PostRAScheduler - True if using post-register-allocation scheduler.
165  bool PostRAScheduler;
166
167  /// PadShortFunctions - True if the short functions should be padded to prevent
168  /// a stall when returning too early.
169  bool PadShortFunctions;
170
171  /// CallRegIndirect - True if the Calls with memory reference should be converted
172  /// to a register-based indirect call.
173  bool CallRegIndirect;
174  /// LEAUsesAG - True if the LEA instruction inputs have to be ready at
175  ///             address generation (AG) time.
176  bool LEAUsesAG;
177
178  /// Processor has AVX-512 PreFetch Instructions
179  bool HasPFI;
180
181  /// Processor has AVX-512 Exponential and Reciprocal Instructions
182  bool HasERI;
183
184  /// Processor has AVX-512 Conflict Detection Instructions
185  bool HasCDI;
186
187  /// stackAlignment - The minimum alignment known to hold of the stack frame on
188  /// entry to the function and which must be maintained by every function.
189  unsigned stackAlignment;
190
191  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
192  ///
193  unsigned MaxInlineSizeThreshold;
194
195  /// TargetTriple - What processor and OS we're targeting.
196  Triple TargetTriple;
197
198  /// Instruction itineraries for scheduling
199  InstrItineraryData InstrItins;
200
201private:
202  /// StackAlignOverride - Override the stack alignment.
203  unsigned StackAlignOverride;
204
205  /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
206  bool In64BitMode;
207
208public:
209  /// This constructor initializes the data members to match that
210  /// of the specified triple.
211  ///
212  X86Subtarget(const std::string &TT, const std::string &CPU,
213               const std::string &FS,
214               unsigned StackAlignOverride, bool is64Bit);
215
216  /// getStackAlignment - Returns the minimum alignment known to hold of the
217  /// stack frame on entry to the function and which must be maintained by every
218  /// function for this subtarget.
219  unsigned getStackAlignment() const { return stackAlignment; }
220
221  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
222  /// that still makes it profitable to inline the call.
223  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
224
225  /// ParseSubtargetFeatures - Parses features string setting specified
226  /// subtarget options.  Definition of function is auto generated by tblgen.
227  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
228
229  /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
230  /// instruction.
231  void AutoDetectSubtargetFeatures();
232
233  /// \brief Reset the features for the X86 target.
234  virtual void resetSubtargetFeatures(const MachineFunction *MF);
235private:
236  void initializeEnvironment();
237  void resetSubtargetFeatures(StringRef CPU, StringRef FS);
238public:
239  /// Is this x86_64? (disregarding specific ABI / programming model)
240  bool is64Bit() const {
241    return In64BitMode;
242  }
243
244  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
245  bool isTarget64BitILP32() const {
246    return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32);
247  }
248
249  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
250  bool isTarget64BitLP64() const {
251    return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32);
252  }
253
254  PICStyles::Style getPICStyle() const { return PICStyle; }
255  void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
256
257  bool hasCMov() const { return HasCMov; }
258  bool hasMMX() const { return X86SSELevel >= MMX; }
259  bool hasSSE1() const { return X86SSELevel >= SSE1; }
260  bool hasSSE2() const { return X86SSELevel >= SSE2; }
261  bool hasSSE3() const { return X86SSELevel >= SSE3; }
262  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
263  bool hasSSE41() const { return X86SSELevel >= SSE41; }
264  bool hasSSE42() const { return X86SSELevel >= SSE42; }
265  bool hasAVX() const { return X86SSELevel >= AVX; }
266  bool hasAVX2() const { return X86SSELevel >= AVX2; }
267  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
268  bool hasFp256() const { return hasAVX(); }
269  bool hasInt256() const { return hasAVX2(); }
270  bool hasSSE4A() const { return HasSSE4A; }
271  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
272  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
273  bool hasPOPCNT() const { return HasPOPCNT; }
274  bool hasAES() const { return HasAES; }
275  bool hasPCLMUL() const { return HasPCLMUL; }
276  bool hasFMA() const { return HasFMA; }
277  // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
278  bool hasFMA4() const { return HasFMA4 && !HasFMA; }
279  bool hasXOP() const { return HasXOP; }
280  bool hasTBM() const { return HasTBM; }
281  bool hasMOVBE() const { return HasMOVBE; }
282  bool hasRDRAND() const { return HasRDRAND; }
283  bool hasF16C() const { return HasF16C; }
284  bool hasFSGSBase() const { return HasFSGSBase; }
285  bool hasLZCNT() const { return HasLZCNT; }
286  bool hasBMI() const { return HasBMI; }
287  bool hasBMI2() const { return HasBMI2; }
288  bool hasRTM() const { return HasRTM; }
289  bool hasHLE() const { return HasHLE; }
290  bool hasADX() const { return HasADX; }
291  bool hasSHA() const { return HasSHA; }
292  bool hasPRFCHW() const { return HasPRFCHW; }
293  bool hasRDSEED() const { return HasRDSEED; }
294  bool isBTMemSlow() const { return IsBTMemSlow; }
295  bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
296  bool hasVectorUAMem() const { return HasVectorUAMem; }
297  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
298  bool useLeaForSP() const { return UseLeaForSP; }
299  bool hasSlowDivide() const { return HasSlowDivide; }
300  bool padShortFunctions() const { return PadShortFunctions; }
301  bool callRegIndirect() const { return CallRegIndirect; }
302  bool LEAusesAG() const { return LEAUsesAG; }
303  bool hasCDI() const { return HasCDI; }
304  bool hasPFI() const { return HasPFI; }
305  bool hasERI() const { return HasERI; }
306
307  bool isAtom() const { return X86ProcFamily == IntelAtom; }
308
309  const Triple &getTargetTriple() const { return TargetTriple; }
310
311  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
312  bool isTargetFreeBSD() const {
313    return TargetTriple.getOS() == Triple::FreeBSD;
314  }
315  bool isTargetSolaris() const {
316    return TargetTriple.getOS() == Triple::Solaris;
317  }
318  bool isTargetELF() const {
319    return (TargetTriple.getEnvironment() == Triple::ELF ||
320            TargetTriple.isOSBinFormatELF());
321  }
322  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
323  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
324  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
325  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
326  bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
327  bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
328  bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
329  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
330  bool isTargetCOFF() const {
331    return (TargetTriple.getEnvironment() != Triple::ELF &&
332            TargetTriple.isOSBinFormatCOFF());
333  }
334  bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
335
336  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
337
338  bool isTargetWin64() const {
339    return In64BitMode && TargetTriple.isOSWindows();
340  }
341
342  bool isTargetWin32() const {
343    return !In64BitMode && (isTargetCygMing() || isTargetWindows());
344  }
345
346  bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
347  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
348  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
349
350  bool isPICStyleStubPIC() const {
351    return PICStyle == PICStyles::StubPIC;
352  }
353
354  bool isPICStyleStubNoDynamic() const {
355    return PICStyle == PICStyles::StubDynamicNoPIC;
356  }
357  bool isPICStyleStubAny() const {
358    return PICStyle == PICStyles::StubDynamicNoPIC ||
359           PICStyle == PICStyles::StubPIC;
360  }
361
362  bool isCallingConvWin64(CallingConv::ID CC) const {
363    return (isTargetWin64() && CC != CallingConv::X86_64_SysV) ||
364           CC == CallingConv::X86_64_Win64;
365  }
366
367  /// ClassifyGlobalReference - Classify a global variable reference for the
368  /// current subtarget according to how we should reference it in a non-pcrel
369  /// context.
370  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
371                                        const TargetMachine &TM)const;
372
373  /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
374  /// current subtarget according to how we should reference it in a non-pcrel
375  /// context.
376  unsigned char ClassifyBlockAddressReference() const;
377
378  /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
379  /// to immediate address.
380  bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
381
382  /// This function returns the name of a function which has an interface
383  /// like the non-standard bzero function, if such a function exists on
384  /// the current subtarget and it is considered prefereable over
385  /// memset with zero passed as the second argument. Otherwise it
386  /// returns null.
387  const char *getBZeroEntry() const;
388
389  /// This function returns true if the target has sincos() routine in its
390  /// compiler runtime or math libraries.
391  bool hasSinCos() const;
392
393  /// Enable the MachineScheduler pass for all X86 subtargets.
394  bool enableMachineScheduler() const LLVM_OVERRIDE { return true; }
395
396  /// enablePostRAScheduler - run for Atom optimization.
397  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
398                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
399                             RegClassVector& CriticalPathRCs) const;
400
401  bool postRAScheduler() const { return PostRAScheduler; }
402
403  /// getInstrItins = Return the instruction itineraries based on the
404  /// subtarget selection.
405  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
406};
407
408} // End llvm namespace
409
410#endif
411