X86SchedHaswell.td revision 263508
1//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the machine model for Haswell to support instruction 11// scheduling and other instruction cost heuristics. 12// 13//===----------------------------------------------------------------------===// 14 15def HaswellModel : SchedMachineModel { 16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4 17 // instructions per cycle. 18 let IssueWidth = 4; 19 let MicroOpBufferSize = 192; // Based on the reorder buffer. 20 let LoadLatency = 4; 21 let MispredictPenalty = 16; 22 23 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow 24 // the scheduler to assign a default model to unrecognized opcodes. 25 let CompleteModel = 0; 26} 27 28let SchedModel = HaswellModel in { 29 30// Haswell can issue micro-ops to 8 different ports in one cycle. 31 32// Ports 0, 1, 5, 6 and 7 handle all computation. 33// Port 4 gets the data half of stores. Store data can be available later than 34// the store address, but since we don't model the latency of stores, we can 35// ignore that. 36// Ports 2 and 3 are identical. They handle loads and the address half of 37// stores. Port 7 can handle address calculations. 38def HWPort0 : ProcResource<1>; 39def HWPort1 : ProcResource<1>; 40def HWPort2 : ProcResource<1>; 41def HWPort3 : ProcResource<1>; 42def HWPort4 : ProcResource<1>; 43def HWPort5 : ProcResource<1>; 44def HWPort6 : ProcResource<1>; 45def HWPort7 : ProcResource<1>; 46 47// Many micro-ops are capable of issuing on multiple ports. 48def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>; 49def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>; 50def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>; 51def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>; 52def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; 53def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; 54def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; 55 56// 60 Entry Unified Scheduler 57def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4, 58 HWPort5, HWPort6, HWPort7]> { 59 let BufferSize=60; 60} 61 62// Integer division issued on port 0. 63def HWDivider : ProcResource<1>; 64 65// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4 66// cycles after the memory operand. 67def : ReadAdvance<ReadAfterLd, 4>; 68 69// Many SchedWrites are defined in pairs with and without a folded load. 70// Instructions with folded loads are usually micro-fused, so they only appear 71// as two micro-ops when queued in the reservation station. 72// This multiclass defines the resource usage for variants with and without 73// folded loads. 74multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW, 75 ProcResourceKind ExePort, 76 int Lat> { 77 // Register variant is using a single cycle on ExePort. 78 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 79 80 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the 81 // latency. 82 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> { 83 let Latency = !add(Lat, 4); 84 } 85} 86 87// A folded store needs a cycle on port 4 for the store data, but it does not 88// need an extra port 2/3 cycle to recompute the address. 89def : WriteRes<WriteRMW, [HWPort4]>; 90 91def : WriteRes<WriteStore, [HWPort237, HWPort4]>; 92def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; } 93def : WriteRes<WriteMove, [HWPort0156]>; 94def : WriteRes<WriteZero, []>; 95 96defm : HWWriteResPair<WriteALU, HWPort0156, 1>; 97defm : HWWriteResPair<WriteIMul, HWPort1, 3>; 98def : WriteRes<WriteIMulH, []> { let Latency = 3; } 99defm : HWWriteResPair<WriteShift, HWPort056, 1>; 100defm : HWWriteResPair<WriteJump, HWPort5, 1>; 101 102// This is for simple LEAs with one or two input operands. 103// The complex ones can only execute on port 1, and they require two cycles on 104// the port to read all inputs. We don't model that. 105def : WriteRes<WriteLEA, [HWPort15]>; 106 107// This is quite rough, latency depends on the dividend. 108def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> { 109 let Latency = 25; 110 let ResourceCycles = [1, 10]; 111} 112def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> { 113 let Latency = 29; 114 let ResourceCycles = [1, 1, 10]; 115} 116 117// Scalar and vector floating point. 118defm : HWWriteResPair<WriteFAdd, HWPort1, 3>; 119defm : HWWriteResPair<WriteFMul, HWPort0, 5>; 120defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles. 121defm : HWWriteResPair<WriteFRcp, HWPort0, 5>; 122defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>; 123defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>; 124defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>; 125defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>; 126 127// Vector integer operations. 128defm : HWWriteResPair<WriteVecShift, HWPort05, 1>; 129defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>; 130defm : HWWriteResPair<WriteVecALU, HWPort15, 1>; 131defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>; 132defm : HWWriteResPair<WriteShuffle, HWPort15, 1>; 133 134def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; } 135def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; } 136} // SchedModel 137