X86InstrSystem.td revision 263508 
1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let SchedRW = [WriteSystem] in {
17let Defs = [RAX, RDX] in
18  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
19              TB;
20
21let Defs = [RAX, RCX, RDX] in
22  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
23
24// CPU flow control instructions
25
26let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
27  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29}
30
31def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
33
34// Interrupt and SysCall Instructions.
35let Uses = [EFLAGS] in
36  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
38              [(int_x86_int (i8 3))], IIC_INT3>;
39} // SchedRW
40
41def : Pat<(debugtrap),
42          (INT3)>;
43
44// The long form of "int $3" turns into int3 as a size optimization.
45// FIXME: This doesn't work because InstAlias can't match immediate constants.
46//def : InstAlias<"int\t$3", (INT3)>;
47
48let SchedRW = [WriteSystem] in {
49
50def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
51              [(int_x86_int imm:$trap)], IIC_INT>;
52
53
54def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
55def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
56def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
57               Requires<[In64BitMode]>;
58
59def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
60                 IIC_SYS_ENTER_EXIT>, TB;
61
62def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
63                 IIC_SYS_ENTER_EXIT>, TB;
64def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", []>, TB,
65                Requires<[In64BitMode]>;
66
67def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
68def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>;
69def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
70             Requires<[In64BitMode]>;
71} // SchedRW
72
73
74//===----------------------------------------------------------------------===//
75//  Input/Output Instructions.
76//
77let SchedRW = [WriteSystem] in {
78let Defs = [AL], Uses = [DX] in
79def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
80               "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
81let Defs = [AX], Uses = [DX] in
82def IN16rr : I<0xED, RawFrm, (outs), (ins),
83               "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize;
84let Defs = [EAX], Uses = [DX] in
85def IN32rr : I<0xED, RawFrm, (outs), (ins),
86               "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>;
87
88let Defs = [AL] in
89def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
90                  "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
91let Defs = [AX] in
92def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
93                  "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;
94let Defs = [EAX] in
95def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
96                  "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>;
97
98let Uses = [DX, AL] in
99def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
100                "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
101let Uses = [DX, AX] in
102def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
103                "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;
104let Uses = [DX, EAX] in
105def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
106                "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>;
107
108let Uses = [AL] in
109def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
110                   "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
111let Uses = [AX] in
112def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
113                   "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize;
114let Uses = [EAX] in
115def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
116                   "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>;
117
118def IN8  : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
119def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>,  OpSize;
120def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>;
121} // SchedRW
122
123//===----------------------------------------------------------------------===//
124// Moves to and from debug registers
125
126let SchedRW = [WriteSystem] in {
127def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
128                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB;
129def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
130                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB;
131                
132def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
133                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB;
134def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
135                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB;
136} // SchedRW
137
138//===----------------------------------------------------------------------===//
139// Moves to and from control registers
140
141let SchedRW = [WriteSystem] in {
142def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
143                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB;
144def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
145                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB;
146                
147def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
148                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB;
149def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
150                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB;
151} // SchedRW
152
153//===----------------------------------------------------------------------===//
154// Segment override instruction prefixes
155
156def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
157def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
158def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
159def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
160def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
161def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
162
163
164//===----------------------------------------------------------------------===//
165// Moves to and from segment registers.
166//
167
168let SchedRW = [WriteMove] in {
169def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
170                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
171def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
172                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
173def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
174                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
175
176def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
177                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
178def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
179                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
180def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
181                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
182
183def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
184                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
185def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
186                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
187def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
188                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
189
190def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
191                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
192def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
193                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
194def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
195                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
196} // SchedRW
197
198//===----------------------------------------------------------------------===//
199// Segmentation support instructions.
200
201let SchedRW = [WriteSystem] in {
202def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
203
204def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 
205                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, OpSize;
206def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
207                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, OpSize;
208
209// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
210def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 
211                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
212def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
213                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
214// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
215def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 
216                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
217def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
218                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
219
220def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
221                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, OpSize; 
222def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
223                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, OpSize;
224def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
225                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB; 
226def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
227                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
228def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
229                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB; 
230def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
231                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
232
233def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
234               [], IIC_INVLPG>, TB;
235
236def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
237               "str{w}\t$dst", [], IIC_STR>, TB, OpSize;
238def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
239               "str{l}\t$dst", [], IIC_STR>, TB;
240def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
241                "str{q}\t$dst", [], IIC_STR>, TB;
242def STRm   : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
243               "str{w}\t$dst", [], IIC_STR>, TB;
244
245def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
246             "ltr{w}\t$src", [], IIC_LTR>, TB;
247def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
248             "ltr{w}\t$src", [], IIC_LTR>, TB;
249             
250def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
251                 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
252               OpSize;
253def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
254                 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>, Requires<[In32BitMode]>;
255def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
256                 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
257               OpSize;
258def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
259                 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
260def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
261                 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
262               OpSize;
263def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
264                 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
265def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
266                 "push{w}\t{%es|es}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
267               OpSize;
268def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
269                 "push{l}\t{%es|es}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
270                 
271def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
272                 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize, TB;
273def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
274                 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
275def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
276                 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize, TB;
277def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
278                 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
279
280def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
281                 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB;
282def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
283                 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB;
284
285// No "pop cs" instruction.
286def POPSS16 : I<0x17, RawFrm, (outs), (ins),
287                "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
288              OpSize, Requires<[In32BitMode]>;
289def POPSS32 : I<0x17, RawFrm, (outs), (ins),
290                "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
291                      Requires<[In32BitMode]>;
292                
293def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
294                "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
295              OpSize, Requires<[In32BitMode]>;
296def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
297                "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
298                      Requires<[In32BitMode]>;
299                
300def POPES16 : I<0x07, RawFrm, (outs), (ins),
301                "pop{w}\t{%es|es}", [], IIC_POP_SR>,
302              OpSize, Requires<[In32BitMode]>;
303def POPES32 : I<0x07, RawFrm, (outs), (ins),
304                "pop{l}\t{%es|es}", [], IIC_POP_SR>,
305                      Requires<[In32BitMode]>;
306                
307def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
308                "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize, TB;
309def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
310                "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
311def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
312                "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB;
313                
314def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
315                "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize, TB;
316def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
317                "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
318def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
319                "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB;
320                 
321
322def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
323                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
324def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
325                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;
326                
327def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
328                "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
329def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
330                "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
331def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
332                 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
333                
334def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
335                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
336def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
337                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;
338                
339def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
340                "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
341def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
342                "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
343def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
344                 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
345                
346def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
347                "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
348def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
349                "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
350                
351def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
352                 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
353
354
355def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
356              "verr\t$seg", [], IIC_VERR>, TB;
357def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
358              "verr\t$seg", [], IIC_VERR>, TB;
359def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
360              "verw\t$seg", [], IIC_VERW_MEM>, TB;
361def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
362              "verw\t$seg", [], IIC_VERW_REG>, TB;
363} // SchedRW
364
365//===----------------------------------------------------------------------===//
366// Descriptor-table support instructions
367
368let SchedRW = [WriteSystem] in {
369def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
370              "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[In32BitMode]>;
371def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
372              "sgdt\t$dst", [], IIC_SGDT>, TB;
373def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
374              "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[In32BitMode]>;
375def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
376              "sidt\t$dst", []>, TB;
377def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
378                "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize;
379def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
380                "sldt{w}\t$dst", [], IIC_SLDT>, TB;
381def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
382                "sldt{l}\t$dst", [], IIC_SLDT>, TB;
383                
384// LLDT is not interpreted specially in 64-bit mode because there is no sign
385//   extension.
386def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
387                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
388def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
389                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
390
391def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
392              "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[In32BitMode]>;
393def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
394              "lgdt\t$src", [], IIC_LGDT>, TB;
395def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
396              "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[In32BitMode]>;
397def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
398              "lidt\t$src", [], IIC_LIDT>, TB;
399def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
400                "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
401def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
402                "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
403} // SchedRW
404
405//===----------------------------------------------------------------------===//
406// Specialized register support
407let SchedRW = [WriteSystem] in {
408def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
409def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
410def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB;
411
412def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins), 
413                "smsw{w}\t$dst", [], IIC_SMSW>, OpSize, TB;
414def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins), 
415                "smsw{l}\t$dst", [], IIC_SMSW>, TB;
416// no m form encodable; use SMSW16m
417def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins), 
418                 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
419
420// For memory operands, there is only a 16-bit form
421def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
422                "smsw{w}\t$dst", [], IIC_SMSW>, TB;
423
424def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
425                "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
426def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
427                "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
428                
429def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
430} // SchedRW
431
432//===----------------------------------------------------------------------===//
433// Cache instructions
434let SchedRW = [WriteSystem] in {
435def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
436def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
437} // SchedRW
438
439//===----------------------------------------------------------------------===//
440// XSAVE instructions
441let SchedRW = [WriteSystem] in {
442let Defs = [RDX, RAX], Uses = [RCX] in
443  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
444
445let Uses = [RDX, RAX, RCX] in
446  def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
447
448let Uses = [RDX, RAX] in {
449  def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
450               "xsave\t$dst", []>, TB;
451  def XSAVE64 : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
452                 "xsave{q|64}\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
453  def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
454               "xrstor\t$dst", []>, TB;
455  def XRSTOR64 : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
456                 "xrstor{q|64}\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
457  def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
458                  "xsaveopt\t$dst", []>, TB;
459  def XSAVEOPT64 : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
460                    "xsaveopt{q|64}\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
461}
462} // SchedRW
463
464//===----------------------------------------------------------------------===//
465// VIA PadLock crypto instructions
466let Defs = [RAX, RDI], Uses = [RDX, RDI] in
467  def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7;
468
469def : InstAlias<"xstorerng", (XSTORE)>;
470
471let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
472  def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7;
473  def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7;
474  def XCRYPTCTR : I<0xd8, RawFrm, (outs), (ins), "xcryptctr", []>, A7;
475  def XCRYPTCFB : I<0xe0, RawFrm, (outs), (ins), "xcryptcfb", []>, A7;
476  def XCRYPTOFB : I<0xe8, RawFrm, (outs), (ins), "xcryptofb", []>, A7;
477}
478
479let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
480  def XSHA1 : I<0xc8, RawFrm, (outs), (ins), "xsha1", []>, A6;
481  def XSHA256 : I<0xd0, RawFrm, (outs), (ins), "xsha256", []>, A6;
482}
483let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
484  def MONTMUL : I<0xc0, RawFrm, (outs), (ins), "montmul", []>, A6;
485
486//===----------------------------------------------------------------------===//
487// FS/GS Base Instructions
488let Predicates = [HasFSGSBase, In64BitMode] in {
489  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
490                   "rdfsbase{l}\t$dst",
491                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS;
492  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
493                     "rdfsbase{q}\t$dst",
494                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS;
495  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
496                   "rdgsbase{l}\t$dst",
497                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS;
498  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
499                     "rdgsbase{q}\t$dst",
500                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS;
501  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
502                   "wrfsbase{l}\t$src",
503                   [(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS;
504  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
505                      "wrfsbase{q}\t$src",
506                      [(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS;
507  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
508                   "wrgsbase{l}\t$src",
509                   [(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS;
510  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
511                      "wrgsbase{q}\t$src",
512                      [(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS;
513}
514
515//===----------------------------------------------------------------------===//
516// INVPCID Instruction
517def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
518                "invpcid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
519                Requires<[In32BitMode]>;
520def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
521                "invpcid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
522                Requires<[In64BitMode]>;
523
524//===----------------------------------------------------------------------===//
525// SMAP Instruction
526let Defs = [EFLAGS], Uses = [EFLAGS] in {
527  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
528  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
529}
530