X86InstrFragmentsSIMD.td revision 263508 
1//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides pattern fragments useful for SIMD instructions.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// MMX Pattern Fragments
16//===----------------------------------------------------------------------===//
17
18def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
19def bc_mmx  : PatFrag<(ops node:$in), (x86mmx  (bitconvert node:$in))>;
20
21//===----------------------------------------------------------------------===//
22// SSE specific DAG Nodes.
23//===----------------------------------------------------------------------===//
24
25def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
26                                            SDTCisFP<0>, SDTCisInt<2> ]>;
27def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
28                                       SDTCisFP<1>, SDTCisVT<3, i8>]>;
29
30def X86umin    : SDNode<"X86ISD::UMIN",      SDTIntBinOp>;
31def X86umax    : SDNode<"X86ISD::UMAX",      SDTIntBinOp>;
32def X86smin    : SDNode<"X86ISD::SMIN",      SDTIntBinOp>;
33def X86smax    : SDNode<"X86ISD::SMAX",      SDTIntBinOp>;
34
35def X86fmin    : SDNode<"X86ISD::FMIN",      SDTFPBinOp>;
36def X86fmax    : SDNode<"X86ISD::FMAX",      SDTFPBinOp>;
37
38// Commutative and Associative FMIN and FMAX.
39def X86fminc    : SDNode<"X86ISD::FMINC", SDTFPBinOp,
40    [SDNPCommutative, SDNPAssociative]>;
41def X86fmaxc    : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
42    [SDNPCommutative, SDNPAssociative]>;
43
44def X86fand    : SDNode<"X86ISD::FAND",      SDTFPBinOp,
45                        [SDNPCommutative, SDNPAssociative]>;
46def X86for     : SDNode<"X86ISD::FOR",       SDTFPBinOp,
47                        [SDNPCommutative, SDNPAssociative]>;
48def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
49                        [SDNPCommutative, SDNPAssociative]>;
50def X86fandn   : SDNode<"X86ISD::FANDN",     SDTFPBinOp,
51                        [SDNPCommutative, SDNPAssociative]>;
52def X86frsqrt  : SDNode<"X86ISD::FRSQRT",    SDTFPUnaryOp>;
53def X86frcp    : SDNode<"X86ISD::FRCP",      SDTFPUnaryOp>;
54def X86fsrl    : SDNode<"X86ISD::FSRL",      SDTX86FPShiftOp>;
55def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
56def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
57def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
58def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
59def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
60def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
61def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
62def X86cmpss   : SDNode<"X86ISD::FSETCCss",    SDTX86Cmpss>;
63def X86cmpsd   : SDNode<"X86ISD::FSETCCsd",    SDTX86Cmpsd>;
64def X86pshufb  : SDNode<"X86ISD::PSHUFB",
65                 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
66                                      SDTCisSameAs<0,2>]>>;
67def X86andnp   : SDNode<"X86ISD::ANDNP",
68                 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
69                                      SDTCisSameAs<0,2>]>>;
70def X86psign   : SDNode<"X86ISD::PSIGN",
71                 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
72                                      SDTCisSameAs<0,2>]>>;
73def X86pextrb  : SDNode<"X86ISD::PEXTRB",
74                 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
75def X86pextrw  : SDNode<"X86ISD::PEXTRW",
76                 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
77def X86pinsrb  : SDNode<"X86ISD::PINSRB",
78                 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
79                                      SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
80def X86pinsrw  : SDNode<"X86ISD::PINSRW",
81                 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
82                                      SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
83def X86insrtps : SDNode<"X86ISD::INSERTPS",
84                 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
85                                      SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
86def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
87                 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
88
89def X86vzmovly  : SDNode<"X86ISD::VZEXT_MOVL",
90                 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
91                                      SDTCisOpSmallerThanOp<1, 0> ]>>;
92
93def X86vsmovl  : SDNode<"X86ISD::VSEXT_MOVL",
94                 SDTypeProfile<1, 1,
95                 [SDTCisVec<0>, SDTCisInt<1>, SDTCisInt<0>]>>;
96
97def X86vzload  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
98                        [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
99
100def X86vzext   : SDNode<"X86ISD::VZEXT",
101                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
102                                              SDTCisInt<0>, SDTCisInt<1>]>>;
103
104def X86vsext   : SDNode<"X86ISD::VSEXT",
105                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
106                                              SDTCisInt<0>, SDTCisInt<1>]>>;
107
108def X86vtrunc   : SDNode<"X86ISD::VTRUNC",
109                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
110                                              SDTCisInt<0>, SDTCisInt<1>]>>;
111def X86vtruncm   : SDNode<"X86ISD::VTRUNCM",
112                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
113                                              SDTCisInt<0>, SDTCisInt<1>,
114                                              SDTCisVec<2>, SDTCisInt<2>]>>;
115def X86vfpext  : SDNode<"X86ISD::VFPEXT",
116                        SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
117                                             SDTCisFP<0>, SDTCisFP<1>]>>;
118def X86vfpround: SDNode<"X86ISD::VFPROUND",
119                        SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
120                                             SDTCisFP<0>, SDTCisFP<1>]>>;
121
122def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    SDTIntShiftOp>;
123def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    SDTIntShiftOp>;
124def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;
125def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
126def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
127
128def X86IntCmpMask : SDTypeProfile<1, 2,
129    [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
130def X86pcmpeqm  : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
131def X86pcmpgtm  : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
132
133def X86CmpMaskCC : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
134def X86cmpm   : SDNode<"X86ISD::CMPM",    X86CmpMaskCC>;
135def X86cmpmu  : SDNode<"X86ISD::CMPMU",   X86CmpMaskCC>;
136
137def X86vshl    : SDNode<"X86ISD::VSHL",
138                        SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
139                                      SDTCisVec<2>]>>;
140def X86vsrl    : SDNode<"X86ISD::VSRL",
141                        SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
142                                      SDTCisVec<2>]>>;
143def X86vsra    : SDNode<"X86ISD::VSRA",
144                        SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
145                                      SDTCisVec<2>]>>;
146
147def X86vshli   : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
148def X86vsrli   : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
149def X86vsrai   : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
150
151def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
152                                          SDTCisVec<1>,
153                                          SDTCisSameAs<2, 1>]>;
154def X86subus   : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
155def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
156def X86testp   : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
157def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
158def X86ktest   : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
159def X86testm  : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
160                                          SDTCisVec<1>,
161                                          SDTCisSameAs<2, 1>]>>;
162
163def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
164                        SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
165                                      SDTCisSameAs<1,2>]>>;
166
167// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
168// translated into one of the target nodes below during lowering.
169// Note: this is a work in progress...
170def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
171def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
172                                SDTCisSameAs<0,2>]>;
173def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
174                                SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
175
176def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
177                                 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
178def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
179                                 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
180
181def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
182def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
183
184def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
185                             SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>;
186
187def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
188                           SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
189
190def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
191
192def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
193def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
194def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
195
196def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
197
198def X86Movddup  : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
199def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
200def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
201
202def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
203def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
204
205def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
206def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
207def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
208
209def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
210def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
211
212def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
213def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
214
215def X86VPermilp  : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
216def X86VPermv    : SDNode<"X86ISD::VPERMV",   SDTShuff2Op>;
217def X86VPermi    : SDNode<"X86ISD::VPERMI",   SDTShuff2OpI>;
218def X86VPermv3   : SDNode<"X86ISD::VPERMV3",  SDTShuff3Op>;
219
220def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
221
222def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
223def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
224def X86Vinsert   : SDNode<"X86ISD::VINSERT",  SDTypeProfile<1, 3,
225                              [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
226
227def X86Blendi    : SDNode<"X86ISD::BLENDI",   SDTBlend>;
228def X86Fmadd     : SDNode<"X86ISD::FMADD",     SDTFma>;
229def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFma>;
230def X86Fmsub     : SDNode<"X86ISD::FMSUB",     SDTFma>;
231def X86Fnmsub    : SDNode<"X86ISD::FNMSUB",    SDTFma>;
232def X86Fmaddsub  : SDNode<"X86ISD::FMADDSUB",  SDTFma>;
233def X86Fmsubadd  : SDNode<"X86ISD::FMSUBADD",  SDTFma>;
234
235def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
236                                         SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
237                                         SDTCisVT<4, i8>]>;
238def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
239                                         SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
240                                         SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
241                                         SDTCisVT<6, i8>]>;
242
243def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
244def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
245
246//===----------------------------------------------------------------------===//
247// SSE Complex Patterns
248//===----------------------------------------------------------------------===//
249
250// These are 'extloads' from a scalar to the low element of a vector, zeroing
251// the top elements.  These are used for the SSE 'ss' and 'sd' instruction
252// forms.
253def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
254                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
255                                   SDNPWantRoot]>;
256def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
257                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
258                                   SDNPWantRoot]>;
259
260def ssmem : Operand<v4f32> {
261  let PrintMethod = "printf32mem";
262  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
263  let ParserMatchClass = X86Mem32AsmOperand;
264  let OperandType = "OPERAND_MEMORY";
265}
266def sdmem : Operand<v2f64> {
267  let PrintMethod = "printf64mem";
268  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
269  let ParserMatchClass = X86Mem64AsmOperand;
270  let OperandType = "OPERAND_MEMORY";
271}
272
273//===----------------------------------------------------------------------===//
274// SSE pattern fragments
275//===----------------------------------------------------------------------===//
276
277// 128-bit load pattern fragments
278// NOTE: all 128-bit integer vector loads are promoted to v2i64
279def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
280def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
281def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
282
283// 256-bit load pattern fragments
284// NOTE: all 256-bit integer vector loads are promoted to v4i64
285def loadv8f32    : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
286def loadv4f64    : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
287def loadv4i64    : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
288
289// 512-bit load pattern fragments
290def loadv16f32   : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
291def loadv8f64    : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
292def loadv16i32   : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
293def loadv8i64    : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
294
295// 128-/256-/512-bit extload pattern fragments
296def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
297def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
298def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
299
300// Like 'store', but always requires 128-bit vector alignment.
301def alignedstore : PatFrag<(ops node:$val, node:$ptr),
302                           (store node:$val, node:$ptr), [{
303  return cast<StoreSDNode>(N)->getAlignment() >= 16;
304}]>;
305
306// Like 'store', but always requires 256-bit vector alignment.
307def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
308                              (store node:$val, node:$ptr), [{
309  return cast<StoreSDNode>(N)->getAlignment() >= 32;
310}]>;
311
312// Like 'store', but always requires 512-bit vector alignment.
313def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
314                              (store node:$val, node:$ptr), [{
315  return cast<StoreSDNode>(N)->getAlignment() >= 64;
316}]>;
317
318// Like 'load', but always requires 128-bit vector alignment.
319def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
320  return cast<LoadSDNode>(N)->getAlignment() >= 16;
321}]>;
322
323// Like 'X86vzload', but always requires 128-bit vector alignment.
324def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
325  return cast<MemSDNode>(N)->getAlignment() >= 16;
326}]>;
327
328// Like 'load', but always requires 256-bit vector alignment.
329def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
330  return cast<LoadSDNode>(N)->getAlignment() >= 32;
331}]>;
332
333// Like 'load', but always requires 512-bit vector alignment.
334def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
335  return cast<LoadSDNode>(N)->getAlignment() >= 64;
336}]>;
337
338def alignedloadfsf32 : PatFrag<(ops node:$ptr),
339                               (f32 (alignedload node:$ptr))>;
340def alignedloadfsf64 : PatFrag<(ops node:$ptr),
341                               (f64 (alignedload node:$ptr))>;
342
343// 128-bit aligned load pattern fragments
344// NOTE: all 128-bit integer vector loads are promoted to v2i64
345def alignedloadv4f32 : PatFrag<(ops node:$ptr),
346                               (v4f32 (alignedload node:$ptr))>;
347def alignedloadv2f64 : PatFrag<(ops node:$ptr),
348                               (v2f64 (alignedload node:$ptr))>;
349def alignedloadv2i64 : PatFrag<(ops node:$ptr),
350                               (v2i64 (alignedload node:$ptr))>;
351
352// 256-bit aligned load pattern fragments
353// NOTE: all 256-bit integer vector loads are promoted to v4i64
354def alignedloadv8f32 : PatFrag<(ops node:$ptr),
355                               (v8f32 (alignedload256 node:$ptr))>;
356def alignedloadv4f64 : PatFrag<(ops node:$ptr),
357                               (v4f64 (alignedload256 node:$ptr))>;
358def alignedloadv4i64 : PatFrag<(ops node:$ptr),
359                               (v4i64 (alignedload256 node:$ptr))>;
360
361// 512-bit aligned load pattern fragments
362def alignedloadv16f32 : PatFrag<(ops node:$ptr),
363                                (v16f32 (alignedload512 node:$ptr))>;
364def alignedloadv16i32 : PatFrag<(ops node:$ptr),
365                                (v16i32 (alignedload512 node:$ptr))>;
366def alignedloadv8f64  : PatFrag<(ops node:$ptr),
367                                (v8f64  (alignedload512 node:$ptr))>;
368def alignedloadv8i64  : PatFrag<(ops node:$ptr),
369                                (v8i64  (alignedload512 node:$ptr))>;
370
371// Like 'load', but uses special alignment checks suitable for use in
372// memory operands in most SSE instructions, which are required to
373// be naturally aligned on some targets but not on others.  If the subtarget
374// allows unaligned accesses, match any load, though this may require
375// setting a feature bit in the processor (on startup, for example).
376// Opteron 10h and later implement such a feature.
377def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
378  return    Subtarget->hasVectorUAMem()
379         || cast<LoadSDNode>(N)->getAlignment() >= 16;
380}]>;
381
382def memop4 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
383  return    Subtarget->hasVectorUAMem()
384         || cast<LoadSDNode>(N)->getAlignment() >= 4;
385}]>;
386
387def memop8 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
388  return    Subtarget->hasVectorUAMem()
389         || cast<LoadSDNode>(N)->getAlignment() >= 8;
390}]>;
391
392def memopfsf32 : PatFrag<(ops node:$ptr), (f32   (memop node:$ptr))>;
393def memopfsf64 : PatFrag<(ops node:$ptr), (f64   (memop node:$ptr))>;
394
395// 128-bit memop pattern fragments
396// NOTE: all 128-bit integer vector loads are promoted to v2i64
397def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
398def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
399def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
400
401// 256-bit memop pattern fragments
402// NOTE: all 256-bit integer vector loads are promoted to v4i64
403def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
404def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
405def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
406
407// 512-bit memop pattern fragments
408def memopv16f32 : PatFrag<(ops node:$ptr), (v16f32 (memop4 node:$ptr))>;
409def memopv8f64  : PatFrag<(ops node:$ptr), (v8f64  (memop8 node:$ptr))>;
410def memopv16i32 : PatFrag<(ops node:$ptr), (v16i32 (memop4 node:$ptr))>;
411def memopv8i64  : PatFrag<(ops node:$ptr), (v8i64  (memop8 node:$ptr))>;
412
413// SSSE3 uses MMX registers for some instructions. They aren't aligned on a
414// 16-byte boundary.
415// FIXME: 8 byte alignment for mmx reads is not required
416def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
417  return cast<LoadSDNode>(N)->getAlignment() >= 8;
418}]>;
419
420def memopmmx  : PatFrag<(ops node:$ptr), (x86mmx  (memop64 node:$ptr))>;
421
422// MOVNT Support
423// Like 'store', but requires the non-temporal bit to be set
424def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
425                           (st node:$val, node:$ptr), [{
426  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
427    return ST->isNonTemporal();
428  return false;
429}]>;
430
431def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
432                                    (st node:$val, node:$ptr), [{
433  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
434    return ST->isNonTemporal() && !ST->isTruncatingStore() &&
435           ST->getAddressingMode() == ISD::UNINDEXED &&
436           ST->getAlignment() >= 16;
437  return false;
438}]>;
439
440def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
441                                      (st node:$val, node:$ptr), [{
442  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
443    return ST->isNonTemporal() &&
444           ST->getAlignment() < 16;
445  return false;
446}]>;
447
448// 128-bit bitconvert pattern fragments
449def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
450def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
451def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
452def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
453def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
454def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
455
456// 256-bit bitconvert pattern fragments
457def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
458def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
459def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
460def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
461
462// 512-bit bitconvert pattern fragments
463def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
464def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
465
466def vzmovl_v2i64 : PatFrag<(ops node:$src),
467                           (bitconvert (v2i64 (X86vzmovl
468                             (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
469def vzmovl_v4i32 : PatFrag<(ops node:$src),
470                           (bitconvert (v4i32 (X86vzmovl
471                             (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
472
473def vzload_v2i64 : PatFrag<(ops node:$src),
474                           (bitconvert (v2i64 (X86vzload node:$src)))>;
475
476
477def fp32imm0 : PatLeaf<(f32 fpimm), [{
478  return N->isExactlyValue(+0.0);
479}]>;
480
481// BYTE_imm - Transform bit immediates into byte immediates.
482def BYTE_imm  : SDNodeXForm<imm, [{
483  // Transformation function: imm >> 3
484  return getI32Imm(N->getZExtValue() >> 3);
485}]>;
486
487// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
488// to VEXTRACTF128/VEXTRACTI128 imm.
489def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
490  return getI8Imm(X86::getExtractVEXTRACT128Immediate(N));
491}]>;
492
493// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
494// VINSERTF128/VINSERTI128 imm.
495def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
496  return getI8Imm(X86::getInsertVINSERT128Immediate(N));
497}]>;
498
499// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
500// to VEXTRACTF64x4 imm.
501def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
502  return getI8Imm(X86::getExtractVEXTRACT256Immediate(N));
503}]>;
504
505// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
506// VINSERTF64x4 imm.
507def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
508  return getI8Imm(X86::getInsertVINSERT256Immediate(N));
509}]>;
510
511def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
512                                   (extract_subvector node:$bigvec,
513                                                      node:$index), [{
514  return X86::isVEXTRACT128Index(N);
515}], EXTRACT_get_vextract128_imm>;
516
517def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
518                                      node:$index),
519                                 (insert_subvector node:$bigvec, node:$smallvec,
520                                                   node:$index), [{
521  return X86::isVINSERT128Index(N);
522}], INSERT_get_vinsert128_imm>;
523
524
525def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
526                                   (extract_subvector node:$bigvec,
527                                                      node:$index), [{
528  return X86::isVEXTRACT256Index(N);
529}], EXTRACT_get_vextract256_imm>;
530
531def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
532                                      node:$index),
533                                 (insert_subvector node:$bigvec, node:$smallvec,
534                                                   node:$index), [{
535  return X86::isVINSERT256Index(N);
536}], INSERT_get_vinsert256_imm>;
537
538