X86InstrControl.td revision 263508
1//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 jump, return, call, and related instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Control Flow Instructions. 16// 17 18// Return instructions. 19// 20// The X86retflag return instructions are variadic because we may add ST0 and 21// ST1 arguments when returning values on the x87 stack. 22let isTerminator = 1, isReturn = 1, isBarrier = 1, 23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { 24 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops), 25 "ret", 26 [(X86retflag 0)], IIC_RET>; 27 def RETW : I <0xC3, RawFrm, (outs), (ins), 28 "ret{w}", 29 [], IIC_RET>, OpSize; 30 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 31 "ret\t$amt", 32 [(X86retflag timm:$amt)], IIC_RET_IMM>; 33 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), 34 "ret{w}\t$amt", 35 [], IIC_RET_IMM>, OpSize; 36 def LRETL : I <0xCB, RawFrm, (outs), (ins), 37 "{l}ret{l|f}", [], IIC_RET>; 38 def LRETW : I <0xCB, RawFrm, (outs), (ins), 39 "{l}ret{w|f}", [], IIC_RET>, OpSize; 40 def LRETQ : RI <0xCB, RawFrm, (outs), (ins), 41 "{l}ret{q|f}", [], IIC_RET>; 42 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 43 "{l}ret{l|f}\t$amt", [], IIC_RET>; 44 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 45 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize; 46} 47 48// Unconditional branches. 49let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { 50 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst), 51 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>; 52 let hasSideEffects = 0 in 53 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), 54 "jmp\t$dst", [], IIC_JMP_REL>; 55 // FIXME : Intel syntax for JMP64pcrel32 such that it is not ambiguious 56 // with JMP_1. 57 let hasSideEffects = 0 in 58 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst), 59 "jmpq\t$dst", [], IIC_JMP_REL>; 60} 61 62// Conditional Branches. 63let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in { 64 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> { 65 let hasSideEffects = 0 in 66 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [], 67 IIC_Jcc>; 68 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm, 69 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB; 70 } 71} 72 73defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>; 74defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>; 75defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>; 76defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>; 77defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>; 78defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>; 79defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>; 80defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>; 81defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>; 82defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>; 83defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>; 84defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>; 85defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>; 86defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>; 87defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>; 88defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>; 89 90// jcx/jecx/jrcx instructions. 91let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in { 92 // These are the 32-bit versions of this instruction for the asmparser. In 93 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is 94 // jecxz. 95 let Uses = [CX] in 96 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 97 "jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In32BitMode]>; 98 let Uses = [ECX] in 99 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 100 "jecxz\t$dst", [], IIC_JCXZ>, Requires<[In32BitMode]>; 101 102 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser. 103 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version 104 // is jrcxz. 105 let Uses = [ECX] in 106 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 107 "jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>; 108 let Uses = [RCX] in 109 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 110 "jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>; 111} 112 113// Indirect branches 114let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 115 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", 116 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>, 117 Sched<[WriteJump]>; 118 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", 119 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, 120 Requires<[In32BitMode]>, Sched<[WriteJumpLd]>; 121 122 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", 123 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>, 124 Sched<[WriteJump]>; 125 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", 126 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, 127 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>; 128 129 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), 130 (ins i16imm:$off, i16imm:$seg), 131 "ljmp{w}\t{$seg, $off|$off, $seg}", [], 132 IIC_JMP_FAR_PTR>, OpSize, Sched<[WriteJump]>; 133 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), 134 (ins i32imm:$off, i16imm:$seg), 135 "ljmp{l}\t{$seg, $off|$off, $seg}", [], 136 IIC_JMP_FAR_PTR>, Sched<[WriteJump]>; 137 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst), 138 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>, 139 Sched<[WriteJump]>; 140 141 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), 142 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize, 143 Sched<[WriteJumpLd]>; 144 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst), 145 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, 146 Sched<[WriteJumpLd]>; 147} 148 149 150// Loop instructions 151let SchedRW = [WriteJump] in { 152def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>; 153def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>; 154def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>; 155} 156 157//===----------------------------------------------------------------------===// 158// Call Instructions... 159// 160let isCall = 1 in 161 // All calls clobber the non-callee saved registers. ESP is marked as 162 // a use to prevent stack-pointer assignments that appear immediately 163 // before calls from potentially appearing dead. Uses for argument 164 // registers are added manually. 165 let Uses = [ESP] in { 166 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, 167 (outs), (ins i32imm_pcrel:$dst), 168 "call{l}\t$dst", [], IIC_CALL_RI>, 169 Requires<[In32BitMode]>, Sched<[WriteJump]>; 170 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), 171 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>, 172 Requires<[In32BitMode]>, Sched<[WriteJump]>; 173 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst), 174 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], 175 IIC_CALL_MEM>, 176 Requires<[In32BitMode,FavorMemIndirectCall]>, 177 Sched<[WriteJumpLd]>; 178 179 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), 180 (ins i16imm:$off, i16imm:$seg), 181 "lcall{w}\t{$seg, $off|$off, $seg}", [], 182 IIC_CALL_FAR_PTR>, OpSize, Sched<[WriteJump]>; 183 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), 184 (ins i32imm:$off, i16imm:$seg), 185 "lcall{l}\t{$seg, $off|$off, $seg}", [], 186 IIC_CALL_FAR_PTR>, Sched<[WriteJump]>; 187 188 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst), 189 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize, 190 Sched<[WriteJumpLd]>; 191 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst), 192 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, 193 Sched<[WriteJumpLd]>; 194 195 // callw for 16 bit code for the assembler. 196 let isAsmParserOnly = 1 in 197 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, 198 (outs), (ins i16imm_pcrel:$dst), 199 "callw\t$dst", []>, OpSize; 200 } 201 202 203// Tail call stuff. 204 205let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 206 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in 207 let Uses = [ESP] in { 208 def TCRETURNdi : PseudoI<(outs), 209 (ins i32imm_pcrel:$dst, i32imm:$offset), []>; 210 def TCRETURNri : PseudoI<(outs), 211 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>; 212 let mayLoad = 1 in 213 def TCRETURNmi : PseudoI<(outs), 214 (ins i32mem_TC:$dst, i32imm:$offset), []>; 215 216 // FIXME: The should be pseudo instructions that are lowered when going to 217 // mcinst. 218 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), 219 (ins i32imm_pcrel:$dst), 220 "jmp\t$dst # TAILCALL", 221 [], IIC_JMP_REL>; 222 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 223 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead. 224 let mayLoad = 1 in 225 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst), 226 "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>; 227} 228 229 230//===----------------------------------------------------------------------===// 231// Call Instructions... 232// 233 234// RSP is marked as a use to prevent stack-pointer assignments that appear 235// immediately before calls from potentially appearing dead. Uses for argument 236// registers are added manually. 237let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in { 238 // NOTE: this pattern doesn't match "X86call imm", because we do not know 239 // that the offset between an arbitrary immediate and the call will fit in 240 // the 32-bit pcrel field that we have. 241 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, 242 (outs), (ins i64i32imm_pcrel:$dst), 243 "call{q}\t$dst", [], IIC_CALL_RI>, 244 Requires<[In64BitMode]>; 245 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), 246 "call{q}\t{*}$dst", [(X86call GR64:$dst)], 247 IIC_CALL_RI>, 248 Requires<[In64BitMode]>; 249 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), 250 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))], 251 IIC_CALL_MEM>, 252 Requires<[In64BitMode,FavorMemIndirectCall]>; 253 254 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst), 255 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>; 256} 257 258let isCall = 1, isCodeGenOnly = 1 in 259 // __chkstk(MSVC): clobber R10, R11 and EFLAGS. 260 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP. 261 let Defs = [RAX, R10, R11, RSP, EFLAGS], 262 Uses = [RSP] in { 263 def W64ALLOCA : Ii32PCRel<0xE8, RawFrm, 264 (outs), (ins i64i32imm_pcrel:$dst), 265 "call{q}\t$dst", [], IIC_CALL_RI>, 266 Requires<[IsWin64]>, Sched<[WriteJump]>; 267 } 268 269let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 270 isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1, 271 SchedRW = [WriteJump] in { 272 def TCRETURNdi64 : PseudoI<(outs), 273 (ins i64i32imm_pcrel:$dst, i32imm:$offset), 274 []>; 275 def TCRETURNri64 : PseudoI<(outs), 276 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>; 277 let mayLoad = 1 in 278 def TCRETURNmi64 : PseudoI<(outs), 279 (ins i64mem_TC:$dst, i32imm:$offset), []>; 280 281 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), 282 (ins i64i32imm_pcrel:$dst), 283 "jmp\t$dst # TAILCALL", [], IIC_JMP_REL>; 284 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 285 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>; 286 287 let mayLoad = 1 in 288 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), 289 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>; 290} 291