X86IntelInstPrinter.cpp revision 263508 
151237Speter//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
251237Speter//
33023Srgrimes//                     The LLVM Compiler Infrastructure
43023Srgrimes//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file includes code for rendering MCInst instances as Intel-style
11// assembly.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "asm-printer"
16#include "X86IntelInstPrinter.h"
17#include "MCTargetDesc/X86BaseInfo.h"
18#include "MCTargetDesc/X86MCTargetDesc.h"
19#include "X86InstComments.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrInfo.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/FormattedStream.h"
25#include <cctype>
26using namespace llvm;
27
28#include "X86GenAsmWriter1.inc"
29
30void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
31  OS << getRegisterName(RegNo);
32}
33
34void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
35                                    StringRef Annot) {
36  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
37  uint64_t TSFlags = Desc.TSFlags;
38
39  if (TSFlags & X86II::LOCK)
40    OS << "\tlock\n";
41
42  printInstruction(MI, OS);
43
44  // Next always print the annotation.
45  printAnnotation(OS, Annot);
46
47  // If verbose assembly is enabled, we can print some informative comments.
48  if (CommentStream)
49    EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
50}
51
52void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
53                                     raw_ostream &O) {
54  int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
55  switch (Imm) {
56  default: llvm_unreachable("Invalid ssecc argument!");
57  case    0: O << "eq"; break;
58  case    1: O << "lt"; break;
59  case    2: O << "le"; break;
60  case    3: O << "unord"; break;
61  case    4: O << "neq"; break;
62  case    5: O << "nlt"; break;
63  case    6: O << "nle"; break;
64  case    7: O << "ord"; break;
65  case    8: O << "eq_uq"; break;
66  case    9: O << "nge"; break;
67  case  0xa: O << "ngt"; break;
68  case  0xb: O << "false"; break;
69  case  0xc: O << "neq_oq"; break;
70  case  0xd: O << "ge"; break;
71  case  0xe: O << "gt"; break;
72  case  0xf: O << "true"; break;
73  }
74}
75
76void X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
77                                     raw_ostream &O) {
78  int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
79  switch (Imm) {
80  default: llvm_unreachable("Invalid avxcc argument!");
81  case    0: O << "eq"; break;
82  case    1: O << "lt"; break;
83  case    2: O << "le"; break;
84  case    3: O << "unord"; break;
85  case    4: O << "neq"; break;
86  case    5: O << "nlt"; break;
87  case    6: O << "nle"; break;
88  case    7: O << "ord"; break;
89  case    8: O << "eq_uq"; break;
90  case    9: O << "nge"; break;
91  case  0xa: O << "ngt"; break;
92  case  0xb: O << "false"; break;
93  case  0xc: O << "neq_oq"; break;
94  case  0xd: O << "ge"; break;
95  case  0xe: O << "gt"; break;
96  case  0xf: O << "true"; break;
97  case 0x10: O << "eq_os"; break;
98  case 0x11: O << "lt_oq"; break;
99  case 0x12: O << "le_oq"; break;
100  case 0x13: O << "unord_s"; break;
101  case 0x14: O << "neq_us"; break;
102  case 0x15: O << "nlt_uq"; break;
103  case 0x16: O << "nle_uq"; break;
104  case 0x17: O << "ord_s"; break;
105  case 0x18: O << "eq_us"; break;
106  case 0x19: O << "nge_uq"; break;
107  case 0x1a: O << "ngt_uq"; break;
108  case 0x1b: O << "false_os"; break;
109  case 0x1c: O << "neq_os"; break;
110  case 0x1d: O << "ge_oq"; break;
111  case 0x1e: O << "gt_oq"; break;
112  case 0x1f: O << "true_us"; break;
113  }
114}
115
116/// printPCRelImm - This is used to print an immediate value that ends up
117/// being encoded as a pc-relative value.
118void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
119                                        raw_ostream &O) {
120  const MCOperand &Op = MI->getOperand(OpNo);
121  if (Op.isImm())
122    O << formatImm(Op.getImm());
123  else {
124    assert(Op.isExpr() && "unknown pcrel immediate operand");
125    // If a symbolic branch target was added as a constant expression then print
126    // that address in hex.
127    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
128    int64_t Address;
129    if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
130      O << formatHex((uint64_t)Address);
131    }
132    else {
133      // Otherwise, just print the expression.
134      O << *Op.getExpr();
135    }
136  }
137}
138
139void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
140                                       raw_ostream &O) {
141  const MCOperand &Op = MI->getOperand(OpNo);
142  if (Op.isReg()) {
143    printRegName(O, Op.getReg());
144  } else if (Op.isImm()) {
145    O << formatImm((int64_t)Op.getImm());
146  } else {
147    assert(Op.isExpr() && "unknown operand kind in printOperand");
148    O << *Op.getExpr();
149  }
150}
151
152void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
153                                            raw_ostream &O) {
154  const MCOperand &BaseReg  = MI->getOperand(Op);
155  unsigned ScaleVal         = MI->getOperand(Op+1).getImm();
156  const MCOperand &IndexReg = MI->getOperand(Op+2);
157  const MCOperand &DispSpec = MI->getOperand(Op+3);
158  const MCOperand &SegReg   = MI->getOperand(Op+4);
159
160  // If this has a segment register, print it.
161  if (SegReg.getReg()) {
162    printOperand(MI, Op+4, O);
163    O << ':';
164  }
165
166  O << '[';
167
168  bool NeedPlus = false;
169  if (BaseReg.getReg()) {
170    printOperand(MI, Op, O);
171    NeedPlus = true;
172  }
173
174  if (IndexReg.getReg()) {
175    if (NeedPlus) O << " + ";
176    if (ScaleVal != 1)
177      O << ScaleVal << '*';
178    printOperand(MI, Op+2, O);
179    NeedPlus = true;
180  }
181
182  if (!DispSpec.isImm()) {
183    if (NeedPlus) O << " + ";
184    assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
185    O << *DispSpec.getExpr();
186  } else {
187    int64_t DispVal = DispSpec.getImm();
188    if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
189      if (NeedPlus) {
190        if (DispVal > 0)
191          O << " + ";
192        else {
193          O << " - ";
194          DispVal = -DispVal;
195        }
196      }
197      O << formatImm(DispVal);
198    }
199  }
200
201  O << ']';
202}
203
204void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
205                                         raw_ostream &O) {
206  const MCOperand &DispSpec = MI->getOperand(Op);
207
208  O << '[';
209
210  if (DispSpec.isImm()) {
211    O << formatImm(DispSpec.getImm());
212  } else {
213    assert(DispSpec.isExpr() && "non-immediate displacement?");
214    O << *DispSpec.getExpr();
215  }
216
217  O << ']';
218}
219