SystemZOperands.td revision 263508
1//===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Class definitions 12//===----------------------------------------------------------------------===// 13 14class ImmediateAsmOperand<string name> 15 : AsmOperandClass { 16 let Name = name; 17 let RenderMethod = "addImmOperands"; 18} 19 20// Constructs both a DAG pattern and instruction operand for an immediate 21// of type VT. PRED returns true if a node is acceptable and XFORM returns 22// the operand value associated with the node. ASMOP is the name of the 23// associated asm operand, and also forms the basis of the asm print method. 24class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop> 25 : PatLeaf<(vt imm), pred, xform>, Operand<vt> { 26 let PrintMethod = "print"##asmop##"Operand"; 27 let DecoderMethod = "decode"##asmop##"Operand"; 28 let ParserMatchClass = !cast<AsmOperandClass>(asmop); 29} 30 31// Constructs an asm operand for a PC-relative address. SIZE says how 32// many bits there are. 33class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> { 34 let PredicateMethod = "isImm"; 35 let ParserMethod = "parsePCRel"##size; 36} 37 38// Constructs an operand for a PC-relative address with address type VT. 39// ASMOP is the associated asm operand. 40class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> { 41 let PrintMethod = "printPCRelOperand"; 42 let ParserMatchClass = asmop; 43} 44 45// Constructs both a DAG pattern and instruction operand for a PC-relative 46// address with address size VT. SELF is the name of the operand and 47// ASMOP is the associated asm operand. 48class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop> 49 : ComplexPattern<vt, 1, "selectPCRelAddress", 50 [z_pcrel_wrapper, z_pcrel_offset]>, 51 PCRelOperand<vt, asmop> { 52 let MIOperandInfo = (ops !cast<Operand>(self)); 53} 54 55// Constructs an AsmOperandClass for addressing mode FORMAT, treating the 56// registers as having BITSIZE bits and displacements as having DISPSIZE bits. 57// LENGTH is "LenN" for addresses with an N-bit length field, otherwise it 58// is "". 59class AddressAsmOperand<string format, string bitsize, string dispsize, 60 string length = ""> 61 : AsmOperandClass { 62 let Name = format##bitsize##"Disp"##dispsize##length; 63 let ParserMethod = "parse"##format##bitsize; 64 let RenderMethod = "add"##format##"Operands"; 65} 66 67// Constructs both a DAG pattern and instruction operand for an addressing mode. 68// FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated 69// AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands 70// (base register, displacement, etc.). SELTYPE is the type of the memory 71// operand for selection purposes; sometimes we want different selection 72// choices for the same underlying addressing mode. SUFFIX is similarly 73// a suffix appended to the displacement for selection purposes; 74// e.g. we want to reject small 20-bit displacements if a 12-bit form 75// also exists, but we want to accept them otherwise. 76class AddressingMode<string seltype, string bitsize, string dispsize, 77 string suffix, string length, int numops, string format, 78 dag operands> 79 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops, 80 "select"##seltype##dispsize##suffix##length, 81 [add, sub, or, frameindex, z_adjdynalloc]>, 82 Operand<!cast<ValueType>("i"##bitsize)> { 83 let PrintMethod = "print"##format##"Operand"; 84 let EncoderMethod = "get"##format##dispsize##length##"Encoding"; 85 let DecoderMethod = 86 "decode"##format##bitsize##"Disp"##dispsize##length##"Operand"; 87 let MIOperandInfo = operands; 88 let ParserMatchClass = 89 !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length); 90} 91 92// An addressing mode with a base and displacement but no index. 93class BDMode<string type, string bitsize, string dispsize, string suffix> 94 : AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr", 95 (ops !cast<RegisterOperand>("ADDR"##bitsize), 96 !cast<Immediate>("disp"##dispsize##"imm"##bitsize))>; 97 98// An addressing mode with a base, displacement and index. 99class BDXMode<string type, string bitsize, string dispsize, string suffix> 100 : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr", 101 (ops !cast<RegisterOperand>("ADDR"##bitsize), 102 !cast<Immediate>("disp"##dispsize##"imm"##bitsize), 103 !cast<RegisterOperand>("ADDR"##bitsize))>; 104 105// A BDMode paired with an immediate length operand of LENSIZE bits. 106class BDLMode<string type, string bitsize, string dispsize, string suffix, 107 string lensize> 108 : AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3, 109 "BDLAddr", 110 (ops !cast<RegisterOperand>("ADDR"##bitsize), 111 !cast<Immediate>("disp"##dispsize##"imm"##bitsize), 112 !cast<Immediate>("imm"##bitsize))>; 113 114//===----------------------------------------------------------------------===// 115// Extracting immediate operands from nodes 116// These all create MVT::i64 nodes to ensure the value is not sign-extended 117// when converted from an SDNode to a MachineOperand later on. 118//===----------------------------------------------------------------------===// 119 120// Bits 0-15 (counting from the lsb). 121def LL16 : SDNodeXForm<imm, [{ 122 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL; 123 return CurDAG->getTargetConstant(Value, MVT::i64); 124}]>; 125 126// Bits 16-31 (counting from the lsb). 127def LH16 : SDNodeXForm<imm, [{ 128 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16; 129 return CurDAG->getTargetConstant(Value, MVT::i64); 130}]>; 131 132// Bits 32-47 (counting from the lsb). 133def HL16 : SDNodeXForm<imm, [{ 134 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32; 135 return CurDAG->getTargetConstant(Value, MVT::i64); 136}]>; 137 138// Bits 48-63 (counting from the lsb). 139def HH16 : SDNodeXForm<imm, [{ 140 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48; 141 return CurDAG->getTargetConstant(Value, MVT::i64); 142}]>; 143 144// Low 32 bits. 145def LF32 : SDNodeXForm<imm, [{ 146 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL; 147 return CurDAG->getTargetConstant(Value, MVT::i64); 148}]>; 149 150// High 32 bits. 151def HF32 : SDNodeXForm<imm, [{ 152 uint64_t Value = N->getZExtValue() >> 32; 153 return CurDAG->getTargetConstant(Value, MVT::i64); 154}]>; 155 156// Truncate an immediate to a 8-bit signed quantity. 157def SIMM8 : SDNodeXForm<imm, [{ 158 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64); 159}]>; 160 161// Truncate an immediate to a 8-bit unsigned quantity. 162def UIMM8 : SDNodeXForm<imm, [{ 163 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64); 164}]>; 165 166// Truncate an immediate to a 16-bit signed quantity. 167def SIMM16 : SDNodeXForm<imm, [{ 168 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64); 169}]>; 170 171// Truncate an immediate to a 16-bit unsigned quantity. 172def UIMM16 : SDNodeXForm<imm, [{ 173 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), MVT::i64); 174}]>; 175 176// Truncate an immediate to a 32-bit signed quantity. 177def SIMM32 : SDNodeXForm<imm, [{ 178 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), MVT::i64); 179}]>; 180 181// Truncate an immediate to a 32-bit unsigned quantity. 182def UIMM32 : SDNodeXForm<imm, [{ 183 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), MVT::i64); 184}]>; 185 186// Negate and then truncate an immediate to a 32-bit unsigned quantity. 187def NEGIMM32 : SDNodeXForm<imm, [{ 188 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), MVT::i64); 189}]>; 190 191//===----------------------------------------------------------------------===// 192// Immediate asm operands. 193//===----------------------------------------------------------------------===// 194 195def U4Imm : ImmediateAsmOperand<"U4Imm">; 196def U6Imm : ImmediateAsmOperand<"U6Imm">; 197def S8Imm : ImmediateAsmOperand<"S8Imm">; 198def U8Imm : ImmediateAsmOperand<"U8Imm">; 199def S16Imm : ImmediateAsmOperand<"S16Imm">; 200def U16Imm : ImmediateAsmOperand<"U16Imm">; 201def S32Imm : ImmediateAsmOperand<"S32Imm">; 202def U32Imm : ImmediateAsmOperand<"U32Imm">; 203 204//===----------------------------------------------------------------------===// 205// 8-bit immediates 206//===----------------------------------------------------------------------===// 207 208def uimm8zx4 : Immediate<i8, [{ 209 return isUInt<4>(N->getZExtValue()); 210}], NOOP_SDNodeXForm, "U4Imm">; 211 212def uimm8zx6 : Immediate<i8, [{ 213 return isUInt<6>(N->getZExtValue()); 214}], NOOP_SDNodeXForm, "U6Imm">; 215 216def simm8 : Immediate<i8, [{}], SIMM8, "S8Imm">; 217def uimm8 : Immediate<i8, [{}], UIMM8, "U8Imm">; 218 219//===----------------------------------------------------------------------===// 220// i32 immediates 221//===----------------------------------------------------------------------===// 222 223// Immediates for the lower and upper 16 bits of an i32, with the other 224// bits of the i32 being zero. 225def imm32ll16 : Immediate<i32, [{ 226 return SystemZ::isImmLL(N->getZExtValue()); 227}], LL16, "U16Imm">; 228 229def imm32lh16 : Immediate<i32, [{ 230 return SystemZ::isImmLH(N->getZExtValue()); 231}], LH16, "U16Imm">; 232 233// Immediates for the lower and upper 16 bits of an i32, with the other 234// bits of the i32 being one. 235def imm32ll16c : Immediate<i32, [{ 236 return SystemZ::isImmLL(uint32_t(~N->getZExtValue())); 237}], LL16, "U16Imm">; 238 239def imm32lh16c : Immediate<i32, [{ 240 return SystemZ::isImmLH(uint32_t(~N->getZExtValue())); 241}], LH16, "U16Imm">; 242 243// Short immediates 244def imm32sx8 : Immediate<i32, [{ 245 return isInt<8>(N->getSExtValue()); 246}], SIMM8, "S8Imm">; 247 248def imm32zx8 : Immediate<i32, [{ 249 return isUInt<8>(N->getZExtValue()); 250}], UIMM8, "U8Imm">; 251 252def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">; 253 254def imm32sx16 : Immediate<i32, [{ 255 return isInt<16>(N->getSExtValue()); 256}], SIMM16, "S16Imm">; 257 258def imm32zx16 : Immediate<i32, [{ 259 return isUInt<16>(N->getZExtValue()); 260}], UIMM16, "U16Imm">; 261 262def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">; 263 264// Full 32-bit immediates. we need both signed and unsigned versions 265// because the assembler is picky. E.g. AFI requires signed operands 266// while NILF requires unsigned ones. 267def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">; 268def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">; 269 270def imm32 : ImmLeaf<i32, [{}]>; 271 272//===----------------------------------------------------------------------===// 273// 64-bit immediates 274//===----------------------------------------------------------------------===// 275 276// Immediates for 16-bit chunks of an i64, with the other bits of the 277// i32 being zero. 278def imm64ll16 : Immediate<i64, [{ 279 return SystemZ::isImmLL(N->getZExtValue()); 280}], LL16, "U16Imm">; 281 282def imm64lh16 : Immediate<i64, [{ 283 return SystemZ::isImmLH(N->getZExtValue()); 284}], LH16, "U16Imm">; 285 286def imm64hl16 : Immediate<i64, [{ 287 return SystemZ::isImmHL(N->getZExtValue()); 288}], HL16, "U16Imm">; 289 290def imm64hh16 : Immediate<i64, [{ 291 return SystemZ::isImmHH(N->getZExtValue()); 292}], HH16, "U16Imm">; 293 294// Immediates for 16-bit chunks of an i64, with the other bits of the 295// i32 being one. 296def imm64ll16c : Immediate<i64, [{ 297 return SystemZ::isImmLL(uint64_t(~N->getZExtValue())); 298}], LL16, "U16Imm">; 299 300def imm64lh16c : Immediate<i64, [{ 301 return SystemZ::isImmLH(uint64_t(~N->getZExtValue())); 302}], LH16, "U16Imm">; 303 304def imm64hl16c : Immediate<i64, [{ 305 return SystemZ::isImmHL(uint64_t(~N->getZExtValue())); 306}], HL16, "U16Imm">; 307 308def imm64hh16c : Immediate<i64, [{ 309 return SystemZ::isImmHH(uint64_t(~N->getZExtValue())); 310}], HH16, "U16Imm">; 311 312// Immediates for the lower and upper 32 bits of an i64, with the other 313// bits of the i32 being zero. 314def imm64lf32 : Immediate<i64, [{ 315 return SystemZ::isImmLF(N->getZExtValue()); 316}], LF32, "U32Imm">; 317 318def imm64hf32 : Immediate<i64, [{ 319 return SystemZ::isImmHF(N->getZExtValue()); 320}], HF32, "U32Imm">; 321 322// Immediates for the lower and upper 32 bits of an i64, with the other 323// bits of the i32 being one. 324def imm64lf32c : Immediate<i64, [{ 325 return SystemZ::isImmLF(uint64_t(~N->getZExtValue())); 326}], LF32, "U32Imm">; 327 328def imm64hf32c : Immediate<i64, [{ 329 return SystemZ::isImmHF(uint64_t(~N->getZExtValue())); 330}], HF32, "U32Imm">; 331 332// Short immediates. 333def imm64sx8 : Immediate<i64, [{ 334 return isInt<8>(N->getSExtValue()); 335}], SIMM8, "S8Imm">; 336 337def imm64zx8 : Immediate<i64, [{ 338 return isUInt<8>(N->getSExtValue()); 339}], UIMM8, "U8Imm">; 340 341def imm64sx16 : Immediate<i64, [{ 342 return isInt<16>(N->getSExtValue()); 343}], SIMM16, "S16Imm">; 344 345def imm64zx16 : Immediate<i64, [{ 346 return isUInt<16>(N->getZExtValue()); 347}], UIMM16, "U16Imm">; 348 349def imm64sx32 : Immediate<i64, [{ 350 return isInt<32>(N->getSExtValue()); 351}], SIMM32, "S32Imm">; 352 353def imm64zx32 : Immediate<i64, [{ 354 return isUInt<32>(N->getZExtValue()); 355}], UIMM32, "U32Imm">; 356 357def imm64zx32n : Immediate<i64, [{ 358 return isUInt<32>(-N->getSExtValue()); 359}], NEGIMM32, "U32Imm">; 360 361def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>; 362 363//===----------------------------------------------------------------------===// 364// Floating-point immediates 365//===----------------------------------------------------------------------===// 366 367// Floating-point zero. 368def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 369 370// Floating point negative zero. 371def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>; 372 373//===----------------------------------------------------------------------===// 374// Symbolic address operands 375//===----------------------------------------------------------------------===// 376 377// PC-relative asm operands. 378def PCRel16 : PCRelAsmOperand<"16">; 379def PCRel32 : PCRelAsmOperand<"32">; 380 381// PC-relative offsets of a basic block. The offset is sign-extended 382// and multiplied by 2. 383def brtarget16 : PCRelOperand<OtherVT, PCRel16> { 384 let EncoderMethod = "getPC16DBLEncoding"; 385 let DecoderMethod = "decodePC16DBLOperand"; 386} 387def brtarget32 : PCRelOperand<OtherVT, PCRel32> { 388 let EncoderMethod = "getPC32DBLEncoding"; 389 let DecoderMethod = "decodePC32DBLOperand"; 390} 391 392// A PC-relative offset of a global value. The offset is sign-extended 393// and multiplied by 2. 394def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> { 395 let EncoderMethod = "getPC32DBLEncoding"; 396 let DecoderMethod = "decodePC32DBLOperand"; 397} 398 399//===----------------------------------------------------------------------===// 400// Addressing modes 401//===----------------------------------------------------------------------===// 402 403// 12-bit displacement operands. 404def disp12imm32 : Operand<i32>; 405def disp12imm64 : Operand<i64>; 406 407// 20-bit displacement operands. 408def disp20imm32 : Operand<i32>; 409def disp20imm64 : Operand<i64>; 410 411def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">; 412def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">; 413def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">; 414def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">; 415def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">; 416def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">; 417def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">; 418 419// DAG patterns and operands for addressing modes. Each mode has 420// the form <type><range><group>[<len>] where: 421// 422// <type> is one of: 423// shift : base + displacement (32-bit) 424// bdaddr : base + displacement 425// mviaddr : like bdaddr, but reject cases with a natural index 426// bdxaddr : base + displacement + index 427// laaddr : like bdxaddr, but used for Load Address operations 428// dynalloc : base + displacement + index + ADJDYNALLOC 429// bdladdr : base + displacement with a length field 430// 431// <range> is one of: 432// 12 : the displacement is an unsigned 12-bit value 433// 20 : the displacement is a signed 20-bit value 434// 435// <group> is one of: 436// pair : used when there is an equivalent instruction with the opposite 437// range value (12 or 20) 438// only : used when there is no equivalent instruction with the opposite 439// range value 440// 441// <len> is one of: 442// 443// <empty> : there is no length field 444// len8 : the length field is 8 bits, with a range of [1, 0x100]. 445def shift12only : BDMode <"BDAddr", "32", "12", "Only">; 446def shift20only : BDMode <"BDAddr", "32", "20", "Only">; 447def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">; 448def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">; 449def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">; 450def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">; 451def mviaddr12pair : BDMode <"MVIAddr", "64", "12", "Pair">; 452def mviaddr20pair : BDMode <"MVIAddr", "64", "20", "Pair">; 453def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">; 454def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">; 455def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">; 456def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">; 457def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">; 458def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">; 459def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">; 460def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">; 461def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">; 462 463//===----------------------------------------------------------------------===// 464// Miscellaneous 465//===----------------------------------------------------------------------===// 466 467// Access registers. At present we just use them for accessing the thread 468// pointer, so we don't expose them as register to LLVM. 469def AccessReg : AsmOperandClass { 470 let Name = "AccessReg"; 471 let ParserMethod = "parseAccessReg"; 472} 473def access_reg : Immediate<i8, [{ return N->getZExtValue() < 16; }], 474 NOOP_SDNodeXForm, "AccessReg"> { 475 let ParserMatchClass = AccessReg; 476} 477 478// A 4-bit condition-code mask. 479def cond4 : PatLeaf<(i8 imm), [{ return (N->getZExtValue() < 16); }]>, 480 Operand<i8> { 481 let PrintMethod = "printCond4Operand"; 482} 483