SystemZMCTargetDesc.h revision 263508 
1//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#ifndef SYSTEMZMCTARGETDESC_H
11#define SYSTEMZMCTARGETDESC_H
12
13#include "llvm/Support/DataTypes.h"
14
15namespace llvm {
16
17class MCAsmBackend;
18class MCCodeEmitter;
19class MCContext;
20class MCInstrInfo;
21class MCObjectWriter;
22class MCRegisterInfo;
23class MCSubtargetInfo;
24class StringRef;
25class Target;
26class raw_ostream;
27
28extern Target TheSystemZTarget;
29
30namespace SystemZMC {
31  // How many bytes are in the ABI-defined, caller-allocated part of
32  // a stack frame.
33  const int64_t CallFrameSize = 160;
34
35  // The offset of the DWARF CFA from the incoming stack pointer.
36  const int64_t CFAOffsetFromInitialSP = CallFrameSize;
37
38  // Maps of asm register numbers to LLVM register numbers, with 0 indicating
39  // an invalid register.  In principle we could use 32-bit and 64-bit register
40  // classes directly, provided that we relegated the GPR allocation order
41  // in SystemZRegisterInfo.td to an AltOrder and left the default order
42  // as %r0-%r15.  It seems better to provide the same interface for
43  // all classes though.
44  extern const unsigned GR32Regs[16];
45  extern const unsigned GRH32Regs[16];
46  extern const unsigned GR64Regs[16];
47  extern const unsigned GR128Regs[16];
48  extern const unsigned FP32Regs[16];
49  extern const unsigned FP64Regs[16];
50  extern const unsigned FP128Regs[16];
51
52  // Return the 0-based number of the first architectural register that
53  // contains the given LLVM register.   E.g. R1D -> 1.
54  unsigned getFirstReg(unsigned Reg);
55
56  // Return the given register as a GR64.
57  inline unsigned getRegAsGR64(unsigned Reg) {
58    return GR64Regs[getFirstReg(Reg)];
59  }
60
61  // Return the given register as a low GR32.
62  inline unsigned getRegAsGR32(unsigned Reg) {
63    return GR32Regs[getFirstReg(Reg)];
64  }
65
66  // Return the given register as a high GR32.
67  inline unsigned getRegAsGRH32(unsigned Reg) {
68    return GRH32Regs[getFirstReg(Reg)];
69  }
70}
71
72MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
73                                          const MCRegisterInfo &MRI,
74                                          const MCSubtargetInfo &STI,
75                                          MCContext &Ctx);
76
77MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
78                                        const MCRegisterInfo &MRI,
79                                        StringRef TT, StringRef CPU);
80
81MCObjectWriter *createSystemZObjectWriter(raw_ostream &OS, uint8_t OSABI);
82} // end namespace llvm
83
84// Defines symbolic names for SystemZ registers.
85// This defines a mapping from register name to register number.
86#define GET_REGINFO_ENUM
87#include "SystemZGenRegisterInfo.inc"
88
89// Defines symbolic names for the SystemZ instructions.
90#define GET_INSTRINFO_ENUM
91#include "SystemZGenInstrInfo.inc"
92
93#define GET_SUBTARGETINFO_ENUM
94#include "SystemZGenSubtargetInfo.inc"
95
96#endif
97