SIRegisterInfo.td revision 263508 
1//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Declarations that describe the SI registers
12//===----------------------------------------------------------------------===//
13
14class SIReg <string n, bits<16> encoding = 0> : Register<n> {
15  let Namespace = "AMDGPU";
16  let HWEncoding = encoding;
17}
18
19// Special Registers
20def VCC : SIReg<"VCC", 106>;
21def EXEC : SIReg<"EXEC", 126>;
22def SCC : SIReg<"SCC", 253>;
23def M0 : SIReg <"M0", 124>;
24
25// SGPR registers
26foreach Index = 0-101 in {
27  def SGPR#Index : SIReg <"SGPR"#Index, Index>;
28}
29
30// VGPR registers
31foreach Index = 0-255 in {
32  def VGPR#Index : SIReg <"VGPR"#Index, Index> {
33    let HWEncoding{8} = 1;
34  }
35}
36
37//===----------------------------------------------------------------------===//
38//  Groupings using register classes and tuples
39//===----------------------------------------------------------------------===//
40
41// SGPR 32-bit registers
42def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
43                            (add (sequence "SGPR%u", 0, 101))>;
44
45// SGPR 64-bit registers
46def SGPR_64Regs : RegisterTuples<[sub0, sub1],
47                             [(add (decimate (trunc SGPR_32, 101), 2)),
48                              (add (decimate (shl SGPR_32, 1), 2))]>;
49
50// SGPR 128-bit registers
51def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
52                              [(add (decimate (trunc SGPR_32, 99), 4)),
53                               (add (decimate (shl SGPR_32, 1), 4)),
54                               (add (decimate (shl SGPR_32, 2), 4)),
55                               (add (decimate (shl SGPR_32, 3), 4))]>;
56
57// SGPR 256-bit registers
58def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
59                              [(add (decimate (trunc SGPR_32, 95), 4)),
60                               (add (decimate (shl SGPR_32, 1), 4)),
61                               (add (decimate (shl SGPR_32, 2), 4)),
62                               (add (decimate (shl SGPR_32, 3), 4)),
63                               (add (decimate (shl SGPR_32, 4), 4)),
64                               (add (decimate (shl SGPR_32, 5), 4)),
65                               (add (decimate (shl SGPR_32, 6), 4)),
66                               (add (decimate (shl SGPR_32, 7), 4))]>;
67
68// SGPR 512-bit registers
69def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
70                               sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
71                              [(add (decimate (trunc SGPR_32, 87), 4)),
72                               (add (decimate (shl SGPR_32, 1), 4)),
73                               (add (decimate (shl SGPR_32, 2), 4)),
74                               (add (decimate (shl SGPR_32, 3), 4)),
75                               (add (decimate (shl SGPR_32, 4), 4)),
76                               (add (decimate (shl SGPR_32, 5), 4)),
77                               (add (decimate (shl SGPR_32, 6), 4)),
78                               (add (decimate (shl SGPR_32, 7), 4)),
79                               (add (decimate (shl SGPR_32, 8), 4)),
80                               (add (decimate (shl SGPR_32, 9), 4)),
81                               (add (decimate (shl SGPR_32, 10), 4)),
82                               (add (decimate (shl SGPR_32, 11), 4)),
83                               (add (decimate (shl SGPR_32, 12), 4)),
84                               (add (decimate (shl SGPR_32, 13), 4)),
85                               (add (decimate (shl SGPR_32, 14), 4)),
86                               (add (decimate (shl SGPR_32, 15), 4))]>;
87
88// VGPR 32-bit registers
89def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
90                            (add (sequence "VGPR%u", 0, 255))>;
91
92// VGPR 64-bit registers
93def VGPR_64 : RegisterTuples<[sub0, sub1],
94                             [(add (trunc VGPR_32, 255)),
95                              (add (shl VGPR_32, 1))]>;
96
97// VGPR 96-bit registers
98def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
99                             [(add (trunc VGPR_32, 254)),
100                              (add (shl VGPR_32, 1)),
101                              (add (shl VGPR_32, 2))]>;
102
103// VGPR 128-bit registers
104def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
105                              [(add (trunc VGPR_32, 253)),
106                               (add (shl VGPR_32, 1)),
107                               (add (shl VGPR_32, 2)),
108                               (add (shl VGPR_32, 3))]>;
109
110// VGPR 256-bit registers
111def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
112                              [(add (trunc VGPR_32, 249)),
113                               (add (shl VGPR_32, 1)),
114                               (add (shl VGPR_32, 2)),
115                               (add (shl VGPR_32, 3)),
116                               (add (shl VGPR_32, 4)),
117                               (add (shl VGPR_32, 5)),
118                               (add (shl VGPR_32, 6)),
119                               (add (shl VGPR_32, 7))]>;
120
121// VGPR 512-bit registers
122def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
123                               sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
124                              [(add (trunc VGPR_32, 241)),
125                               (add (shl VGPR_32, 1)),
126                               (add (shl VGPR_32, 2)),
127                               (add (shl VGPR_32, 3)),
128                               (add (shl VGPR_32, 4)),
129                               (add (shl VGPR_32, 5)),
130                               (add (shl VGPR_32, 6)),
131                               (add (shl VGPR_32, 7)),
132                               (add (shl VGPR_32, 8)),
133                               (add (shl VGPR_32, 9)),
134                               (add (shl VGPR_32, 10)),
135                               (add (shl VGPR_32, 11)),
136                               (add (shl VGPR_32, 12)),
137                               (add (shl VGPR_32, 13)),
138                               (add (shl VGPR_32, 14)),
139                               (add (shl VGPR_32, 15))]>;
140
141//===----------------------------------------------------------------------===//
142//  Register classes used as source and destination
143//===----------------------------------------------------------------------===//
144
145// Special register classes for predicates and the M0 register
146def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
147def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
148def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
149def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
150
151// Register class for all scalar registers (SGPRs + Special Registers)
152def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
153  (add SGPR_32, M0Reg)
154>;
155
156def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>;
157
158def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64,
159  (add SGPR_64Regs, VCCReg, EXECReg)
160>;
161
162def SReg_128 : RegisterClass<"AMDGPU", [i128, v4i32], 128, (add SGPR_128)>;
163
164def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
165
166def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)>;
167
168// Register class for all vector registers (VGPRs + Interploation Registers)
169def VReg_32 : RegisterClass<"AMDGPU", [i32, f32, v1i32], 32, (add VGPR_32)>;
170
171def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)>;
172
173def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> {
174  let Size = 96;
175}
176
177def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, i128], 128, (add VGPR_128)>;
178
179def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
180
181def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
182
183//===----------------------------------------------------------------------===//
184//  [SV]Src_* register classes, can have either an immediate or an register
185//===----------------------------------------------------------------------===//
186
187def SSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32)>;
188
189def SSrc_64 : RegisterClass<"AMDGPU", [i64, f64, i1], 64, (add SReg_64)>;
190
191def VSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VReg_32, SReg_32)>;
192
193def VSrc_64 : RegisterClass<"AMDGPU", [i64, f64], 64, (add VReg_64, SReg_64)>;
194
195