AMDILInstrInfo.td revision 263508 
1//===------------ AMDILInstrInfo.td - AMDIL Target ------*-tablegen-*------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9//
10// This file describes the AMDIL instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13//===--------------------------------------------------------------------===//
14// Custom Operands
15//===--------------------------------------------------------------------===//
16def brtarget   : Operand<OtherVT>;
17
18//===--------------------------------------------------------------------===//
19// Custom Selection DAG Type Profiles
20//===--------------------------------------------------------------------===//
21//===----------------------------------------------------------------------===//
22// Generic Profile Types
23//===----------------------------------------------------------------------===//
24
25def SDTIL_GenBinaryOp : SDTypeProfile<1, 2, [
26    SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
27    ]>;
28def SDTIL_GenTernaryOp : SDTypeProfile<1, 3, [
29    SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<2, 3>
30    ]>;
31def SDTIL_GenVecBuild : SDTypeProfile<1, 1, [
32    SDTCisEltOfVec<1, 0>
33    ]>;
34
35//===----------------------------------------------------------------------===//
36// Flow Control Profile Types
37//===----------------------------------------------------------------------===//
38// Branch instruction where second and third are basic blocks
39def SDTIL_BRCond : SDTypeProfile<0, 2, [
40    SDTCisVT<0, OtherVT>
41    ]>;
42
43//===--------------------------------------------------------------------===//
44// Custom Selection DAG Nodes
45//===--------------------------------------------------------------------===//
46//===----------------------------------------------------------------------===//
47// Flow Control DAG Nodes
48//===----------------------------------------------------------------------===//
49def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
50
51//===----------------------------------------------------------------------===//
52// Call/Return DAG Nodes
53//===----------------------------------------------------------------------===//
54def IL_retflag       : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
55    [SDNPHasChain, SDNPOptInGlue]>;
56
57//===--------------------------------------------------------------------===//
58// Instructions
59//===--------------------------------------------------------------------===//
60// Floating point math functions
61def IL_div_inf      : SDNode<"AMDGPUISD::DIV_INF", SDTIL_GenBinaryOp>;
62
63//===----------------------------------------------------------------------===//
64// Integer functions
65//===----------------------------------------------------------------------===//
66def IL_umul        : SDNode<"AMDGPUISD::UMUL"    , SDTIntBinOp,
67    [SDNPCommutative, SDNPAssociative]>;
68
69//===--------------------------------------------------------------------===//
70// Custom Pattern DAG Nodes
71//===--------------------------------------------------------------------===//
72def global_store : PatFrag<(ops node:$val, node:$ptr),
73    (store node:$val, node:$ptr), [{
74        return isGlobalStore(dyn_cast<StoreSDNode>(N));
75}]>;
76
77//===----------------------------------------------------------------------===//
78// Load pattern fragments
79//===----------------------------------------------------------------------===//
80// Global address space loads
81def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
82    return isGlobalLoad(dyn_cast<LoadSDNode>(N));
83}]>;
84// Constant address space loads
85def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
86    return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
87}]>;
88
89//===----------------------------------------------------------------------===//
90// Complex addressing mode patterns
91//===----------------------------------------------------------------------===//
92def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>;
93def ADDRF : ComplexPattern<i32, 2, "SelectADDR", [frameindex], []>;
94def ADDR64 : ComplexPattern<i64, 2, "SelectADDR64", [], []>;
95def ADDR64F : ComplexPattern<i64, 2, "SelectADDR64", [frameindex], []>;
96
97//===----------------------------------------------------------------------===//
98// Instruction format classes
99//===----------------------------------------------------------------------===//
100class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
101: Instruction {
102
103     let Namespace = "AMDGPU";
104     dag OutOperandList = outs;
105     dag InOperandList = ins;
106     let Pattern = pattern;
107     let AsmString = !strconcat(asmstr, "\n");
108     let isPseudo = 1;
109     let Itinerary = NullALU;
110     bit hasIEEEFlag = 0;
111     bit hasZeroOpFlag = 0;
112     let mayLoad = 0;
113     let mayStore = 0;
114     let hasSideEffects = 0;
115}
116
117//===--------------------------------------------------------------------===//
118// Multiclass Instruction formats
119//===--------------------------------------------------------------------===//
120// Multiclass that handles branch instructions
121multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> {
122    def _i32 : ILFormat<(outs),
123  (ins brtarget:$target, rci:$src0),
124        "; i32 Pseudo branch instruction",
125  [(Op bb:$target, (i32 rci:$src0))]>;
126    def _f32 : ILFormat<(outs),
127  (ins brtarget:$target, rcf:$src0),
128        "; f32 Pseudo branch instruction",
129  [(Op bb:$target, (f32 rcf:$src0))]>;
130}
131
132// Only scalar types should generate flow control
133multiclass BranchInstr<string name> {
134  def _i32 : ILFormat<(outs), (ins GPRI32:$src),
135      !strconcat(name, " $src"), []>;
136  def _f32 : ILFormat<(outs), (ins GPRF32:$src),
137      !strconcat(name, " $src"), []>;
138}
139// Only scalar types should generate flow control
140multiclass BranchInstr2<string name> {
141  def _i32 : ILFormat<(outs), (ins GPRI32:$src0, GPRI32:$src1),
142      !strconcat(name, " $src0, $src1"), []>;
143  def _f32 : ILFormat<(outs), (ins GPRF32:$src0, GPRF32:$src1),
144      !strconcat(name, " $src0, $src1"), []>;
145}
146
147//===--------------------------------------------------------------------===//
148// Intrinsics support
149//===--------------------------------------------------------------------===//
150include "AMDILIntrinsics.td"
151