AMDGPURegisterInfo.h revision 263508 
1//===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief TargetRegisterInfo interface that is implemented by all hw codegen
12/// targets.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef AMDGPUREGISTERINFO_H
17#define AMDGPUREGISTERINFO_H
18
19#include "llvm/ADT/BitVector.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21
22#define GET_REGINFO_HEADER
23#define GET_REGINFO_ENUM
24#include "AMDGPUGenRegisterInfo.inc"
25
26namespace llvm {
27
28class AMDGPUTargetMachine;
29class TargetInstrInfo;
30
31struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
32  TargetMachine &TM;
33  static const uint16_t CalleeSavedReg;
34
35  AMDGPURegisterInfo(TargetMachine &tm);
36
37  virtual BitVector getReservedRegs(const MachineFunction &MF) const {
38    assert(!"Unimplemented");  return BitVector();
39  }
40
41  /// \param RC is an AMDIL reg class.
42  ///
43  /// \returns The ISA reg class that is equivalent to \p RC.
44  virtual const TargetRegisterClass * getISARegClass(
45                                         const TargetRegisterClass * RC) const {
46    assert(!"Unimplemented"); return NULL;
47  }
48
49  virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
50    assert(!"Unimplemented"); return NULL;
51  }
52
53  virtual unsigned getHWRegIndex(unsigned Reg) const {
54    assert(!"Unimplemented"); return 0;
55  }
56
57  /// \returns the sub reg enum value for the given \p Channel
58  /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
59  unsigned getSubRegFromChannel(unsigned Channel) const;
60
61  const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const;
62  void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
63                           unsigned FIOperandNum,
64                           RegScavenger *RS) const;
65  unsigned getFrameRegister(const MachineFunction &MF) const;
66
67  unsigned getIndirectSubReg(unsigned IndirectIndex) const;
68
69};
70
71} // End namespace llvm
72
73#endif // AMDIDSAREGISTERINFO_H
74