AMDGPU.td revision 263508 
1275970Scy//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
2275970Scy//
3275970Scy//                     The LLVM Compiler Infrastructure
4275970Scy//
5275970Scy// This file is distributed under the University of Illinois Open Source
6275970Scy// License. See LICENSE.TXT for details.
7275970Scy//
8275970Scy//==-----------------------------------------------------------------------===//
9275970Scy
10275970Scy// Include AMDIL TD files
11275970Scyinclude "AMDILBase.td"
12275970Scy
13275970Scy//===----------------------------------------------------------------------===//
14275970Scy// Subtarget Features
15275970Scy//===----------------------------------------------------------------------===//
16275970Scy
17275970Scy// Debugging Features
18275970Scy
19275970Scydef FeatureDumpCode : SubtargetFeature <"DumpCode",
20275970Scy        "DumpCode",
21275970Scy        "true",
22275970Scy        "Dump MachineInstrs in the CodeEmitter">;
23275970Scy
24275970Scydef FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
25275970Scy        "EnableIRStructurizer",
26275970Scy        "false",
27275970Scy        "Disable IR Structurizer">;
28275970Scy
29275970Scy// Target features
30275970Scy
31275970Scydef FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
32275970Scy        "EnableIfCvt",
33275970Scy        "false",
34275970Scy        "Disable the if conversion pass">;
35275970Scy
36275970Scydef FeatureFP64     : SubtargetFeature<"fp64",
37275970Scy        "FP64",
38275970Scy        "true",
39275970Scy        "Enable 64bit double precision operations">;
40275970Scy
41275970Scydef Feature64BitPtr : SubtargetFeature<"64BitPtr",
42275970Scy        "Is64bit",
43275970Scy        "true",
44275970Scy        "Specify if 64bit addressing should be used.">;
45275970Scy
46275970Scydef Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
47275970Scy        "Is32on64bit",
48275970Scy        "false",
49275970Scy        "Specify if 64bit sized pointers with 32bit addressing should be used.">;
50275970Scy
51275970Scydef FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
52275970Scy        "R600ALUInst",
53275970Scy        "false",
54275970Scy        "Older version of ALU instructions encoding.">;
55275970Scy
56275970Scydef FeatureVertexCache : SubtargetFeature<"HasVertexCache",
57275970Scy        "HasVertexCache",
58275970Scy        "true",
59275970Scy        "Specify use of dedicated vertex cache.">;
60275970Scy
61275970Scydef FeatureCaymanISA : SubtargetFeature<"caymanISA",
62275970Scy        "CaymanISA",
63275970Scy        "true",
64275970Scy        "Use Cayman ISA">;
65275970Scy
66275970Scyclass SubtargetFeatureFetchLimit <string Value> :
67275970Scy                          SubtargetFeature <"fetch"#Value,
68275970Scy        "TexVTXClauseSize",
69275970Scy        Value,
70275970Scy        "Limit the maximum number of fetches in a clause to "#Value>;
71275970Scy
72275970Scydef FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
73275970Scydef FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
74275970Scy
75275970Scyclass SubtargetFeatureGeneration <string Value,
76275970Scy                                  list<SubtargetFeature> Implies> :
77275970Scy        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
78275970Scy                          Value#" GPU generation", Implies>;
79275970Scy
80275970Scydef FeatureR600 : SubtargetFeatureGeneration<"R600",
81275970Scy        [FeatureR600ALUInst, FeatureFetchLimit8]>;
82275970Scy
83275970Scydef FeatureR700 : SubtargetFeatureGeneration<"R700",
84275970Scy        [FeatureFetchLimit16]>;
85275970Scy
86275970Scydef FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
87275970Scy        [FeatureFetchLimit16]>;
88275970Scy
89275970Scydef FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
90275970Scy        [FeatureFetchLimit16]>;
91275970Scy
92275970Scydef FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
93275970Scy        [Feature64BitPtr, FeatureFP64]>;
94275970Scy
95275970Scydef FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
96275970Scy        [Feature64BitPtr, FeatureFP64]>;
97275970Scy//===----------------------------------------------------------------------===//
98275970Scy
99275970Scydef AMDGPUInstrInfo : InstrInfo {
100275970Scy  let guessInstructionProperties = 1;
101275970Scy}
102275970Scy
103275970Scy//===----------------------------------------------------------------------===//
104275970Scy// Declare the target which we are implementing
105275970Scy//===----------------------------------------------------------------------===//
106275970Scydef AMDGPUAsmWriter : AsmWriter {
107275970Scy    string AsmWriterClassName = "InstPrinter";
108275970Scy    int Variant = 0;
109275970Scy    bit isMCAsmWriter = 1;
110275970Scy}
111275970Scy
112275970Scydef AMDGPU : Target {
113275970Scy  // Pull in Instruction Info:
114275970Scy  let InstructionSet = AMDGPUInstrInfo;
115275970Scy  let AssemblyWriters = [AMDGPUAsmWriter];
116275970Scy}
117275970Scy
118275970Scy// Include AMDGPU TD files
119275970Scyinclude "R600Schedule.td"
120275970Scyinclude "SISchedule.td"
121275970Scyinclude "Processors.td"
122275970Scyinclude "AMDGPUInstrInfo.td"
123275970Scyinclude "AMDGPUIntrinsics.td"
124275970Scyinclude "AMDGPURegisterInfo.td"
125275970Scyinclude "AMDGPUInstructions.td"
126275970Scyinclude "AMDGPUCallingConv.td"
127275970Scy