PPCScheduleA2.td revision 263508 
1//===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9
10// Primary reference:
11// A2 Processor User's Manual.
12// IBM (as updated in) 2010.
13
14//===----------------------------------------------------------------------===//
15// Functional units on the PowerPC A2 chip sets
16//
17def XU     : FuncUnit; // XU pipeline
18def FU     : FuncUnit; // FI pipeline
19
20//
21// This file defines the itinerary class data for the PPC A2 processor.
22//
23//===----------------------------------------------------------------------===//
24
25
26def PPCA2Itineraries : ProcessorItineraries<
27  [XU, FU], [], [
28  InstrItinData<IntSimple   , [InstrStage<1, [XU]>],
29                              [1, 1, 1]>,
30  InstrItinData<IntGeneral  , [InstrStage<1, [XU]>],
31                              [2, 1, 1]>,
32  InstrItinData<IntCompare  , [InstrStage<1, [XU]>],
33                              [2, 1, 1]>,
34  InstrItinData<IntDivW     , [InstrStage<1, [XU]>],
35                              [39, 1, 1]>,
36  InstrItinData<IntDivD     , [InstrStage<1, [XU]>],
37                              [71, 1, 1]>,
38  InstrItinData<IntMulHW    , [InstrStage<1, [XU]>],
39                              [5, 1, 1]>,
40  InstrItinData<IntMulHWU   , [InstrStage<1, [XU]>],
41                              [5, 1, 1]>,
42  InstrItinData<IntMulLI    , [InstrStage<1, [XU]>],
43                              [6, 1, 1]>,
44  InstrItinData<IntRotate   , [InstrStage<1, [XU]>],
45                              [2, 1, 1]>,
46  InstrItinData<IntRotateD  , [InstrStage<1, [XU]>],
47                              [2, 1, 1]>,
48  InstrItinData<IntRotateDI , [InstrStage<1, [XU]>],
49                              [2, 1, 1]>,
50  InstrItinData<IntShift    , [InstrStage<1, [XU]>],
51                              [2, 1, 1]>,
52  InstrItinData<IntTrapW    , [InstrStage<1, [XU]>],
53                              [2, 1]>,
54  InstrItinData<IntTrapD    , [InstrStage<1, [XU]>],
55                              [2, 1]>,
56  InstrItinData<BrB         , [InstrStage<1, [XU]>],
57                              [6, 1, 1]>,
58  InstrItinData<BrCR        , [InstrStage<1, [XU]>],
59                              [1, 1, 1]>,
60  InstrItinData<BrMCR       , [InstrStage<1, [XU]>],
61                              [5, 1, 1]>,
62  InstrItinData<BrMCRX      , [InstrStage<1, [XU]>],
63                              [1, 1, 1]>,
64  InstrItinData<LdStDCBA    , [InstrStage<1, [XU]>],
65                              [1, 1, 1]>,
66  InstrItinData<LdStDCBF    , [InstrStage<1, [XU]>],
67                              [1, 1, 1]>,
68  InstrItinData<LdStDCBI    , [InstrStage<1, [XU]>],
69                              [1, 1, 1]>,
70  InstrItinData<LdStLoad    , [InstrStage<1, [XU]>],
71                              [6, 1, 1]>,
72  InstrItinData<LdStLoadUpd , [InstrStage<1, [XU]>],
73                              [6, 8, 1, 1]>,
74  InstrItinData<LdStLDU     , [InstrStage<1, [XU]>],
75                              [6, 1, 1]>,
76  InstrItinData<LdStStore   , [InstrStage<1, [XU]>],
77                              [1, 1, 1]>,
78  InstrItinData<LdStStoreUpd, [InstrStage<1, [XU]>],
79                              [2, 1, 1, 1]>,
80  InstrItinData<LdStICBI,     [InstrStage<1, [XU]>],
81                              [16, 1, 1]>,
82  InstrItinData<LdStSTFD    , [InstrStage<1, [XU]>],
83                              [1, 1, 1]>,
84  InstrItinData<LdStSTFDU   , [InstrStage<1, [XU]>],
85                              [2, 1, 1, 1]>,
86  InstrItinData<LdStLFD     , [InstrStage<1, [XU]>],
87                              [7, 1, 1]>,
88  InstrItinData<LdStLFDU    , [InstrStage<1, [XU]>],
89                              [7, 9, 1, 1]>,
90  InstrItinData<LdStLHA     , [InstrStage<1, [XU]>],
91                              [6, 1, 1]>,
92  InstrItinData<LdStLHAU    , [InstrStage<1, [XU]>],
93                              [6, 8, 1, 1]>,
94  InstrItinData<LdStLWARX   , [InstrStage<1, [XU]>],
95                              [82, 1, 1]>, // L2 latency
96  InstrItinData<LdStSTD     , [InstrStage<1, [XU]>],
97                              [1, 1, 1]>,
98  InstrItinData<LdStSTDU    , [InstrStage<1, [XU]>],
99                              [2, 1, 1, 1]>,
100  InstrItinData<LdStSTDCX   , [InstrStage<1, [XU]>],
101                              [82, 1, 1]>, // L2 latency
102  InstrItinData<LdStSTWCX   , [InstrStage<1, [XU]>],
103                              [82, 1, 1]>, // L2 latency
104  InstrItinData<LdStSync    , [InstrStage<1, [XU]>],
105                              [6]>,
106  InstrItinData<SprISYNC    , [InstrStage<1, [XU]>],
107                              [16]>,
108  InstrItinData<SprMTMSR    , [InstrStage<1, [XU]>],
109                              [16, 1]>,
110  InstrItinData<SprMFCR     , [InstrStage<1, [XU]>],
111                              [6, 1]>,
112  InstrItinData<SprMFMSR    , [InstrStage<1, [XU]>],
113                              [4, 1]>,
114  InstrItinData<SprMFSPR    , [InstrStage<1, [XU]>],
115                              [6, 1]>,
116  InstrItinData<SprMFTB     , [InstrStage<1, [XU]>],
117                              [4, 1]>,
118  InstrItinData<SprMTSPR    , [InstrStage<1, [XU]>],
119                              [6, 1]>,
120  InstrItinData<SprRFI      , [InstrStage<1, [XU]>],
121                              [16]>,
122  InstrItinData<SprSC       , [InstrStage<1, [XU]>],
123                              [16]>,
124  InstrItinData<FPGeneral   , [InstrStage<1, [FU]>],
125                              [6, 1, 1]>,
126  InstrItinData<FPAddSub    , [InstrStage<1, [FU]>],
127                              [6, 1, 1]>,
128  InstrItinData<FPCompare   , [InstrStage<1, [FU]>],
129                              [5, 1, 1]>,
130  InstrItinData<FPDivD      , [InstrStage<1, [FU]>],
131                              [72, 1, 1]>,
132  InstrItinData<FPDivS      , [InstrStage<1, [FU]>],
133                              [59, 1, 1]>,
134  InstrItinData<FPSqrt      , [InstrStage<1, [FU]>],
135                              [69, 1, 1]>,
136  InstrItinData<FPFused     , [InstrStage<1, [FU]>],
137                              [6, 1, 1, 1]>,
138  InstrItinData<FPRes       , [InstrStage<1, [FU]>],
139                              [6, 1]>
140]>;
141
142// ===---------------------------------------------------------------------===//
143// A2 machine model for scheduling and other instruction cost heuristics.
144
145def PPCA2Model : SchedMachineModel {
146  let IssueWidth = 1;  // 2 micro-ops are dispatched per cycle.
147  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
148  let LoadLatency = 6; // Optimistic load latency assuming bypass.
149                       // This is overriden by OperandCycles if the
150                       // Itineraries are queried instead.
151  let MispredictPenalty = 13;
152
153  let Itineraries = PPCA2Itineraries;
154}
155
156