PPCRegisterInfo.td revision 266715
11539Srgrimes//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===// 21539Srgrimes// 31539Srgrimes// The LLVM Compiler Infrastructure 41539Srgrimes// 51539Srgrimes// This file is distributed under the University of Illinois Open Source 61539Srgrimes// License. See LICENSE.TXT for details. 71539Srgrimes// 81539Srgrimes//===----------------------------------------------------------------------===// 91539Srgrimes// 101539Srgrimes// 111539Srgrimes//===----------------------------------------------------------------------===// 121539Srgrimes 131539Srgrimeslet Namespace = "PPC" in { 141539Srgrimesdef sub_lt : SubRegIndex<1>; 151539Srgrimesdef sub_gt : SubRegIndex<1, 1>; 161539Srgrimesdef sub_eq : SubRegIndex<1, 2>; 171539Srgrimesdef sub_un : SubRegIndex<1, 3>; 181539Srgrimesdef sub_32 : SubRegIndex<32>; 191539Srgrimes} 201539Srgrimes 211539Srgrimes 221539Srgrimesclass PPCReg<string n> : Register<n> { 231539Srgrimes let Namespace = "PPC"; 241539Srgrimes} 251539Srgrimes 261539Srgrimes// We identify all our registers with a 5-bit ID, for consistency's sake. 271539Srgrimes 281539Srgrimes// GPR - One of the 32 32-bit general-purpose registers 291539Srgrimesclass GPR<bits<5> num, string n> : PPCReg<n> { 301539Srgrimes let HWEncoding{4-0} = num; 311539Srgrimes} 321539Srgrimes 331539Srgrimes// GP8 - One of the 32 64-bit general-purpose registers 341539Srgrimesclass GP8<GPR SubReg, string n> : PPCReg<n> { 351539Srgrimes let HWEncoding = SubReg.HWEncoding; 3623655Speter let SubRegs = [SubReg]; 3750473Speter let SubRegIndices = [sub_32]; 381539Srgrimes} 391539Srgrimes 401539Srgrimes// SPR - One of the 32-bit special-purpose registers 411539Srgrimesclass SPR<bits<10> num, string n> : PPCReg<n> { 421539Srgrimes let HWEncoding{9-0} = num; 431539Srgrimes} 44102227Smike 451539Srgrimes// FPR - One of the 32 64-bit floating-point registers 46104585Smikeclass FPR<bits<5> num, string n> : PPCReg<n> { 47104585Smike let HWEncoding{4-0} = num; 48102227Smike} 49102227Smike 50102227Smike// VR - One of the 32 128-bit vector registers 511539Srgrimesclass VR<bits<5> num, string n> : PPCReg<n> { 521539Srgrimes let HWEncoding{4-0} = num; 53104585Smike} 54104585Smike 55104585Smike// CR - One of the 8 4-bit condition registers 56104585Smikeclass CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> { 57104585Smike let HWEncoding{2-0} = num; 58104585Smike let SubRegs = subregs; 59104585Smike} 601539Srgrimes 611539Srgrimes// CRBIT - One of the 32 1-bit condition register fields 621539Srgrimesclass CRBIT<bits<5> num, string n> : PPCReg<n> { 631539Srgrimes let HWEncoding{4-0} = num; 641539Srgrimes} 651539Srgrimes 661539Srgrimes// General-purpose registers 671539Srgrimesforeach Index = 0-31 in { 681539Srgrimes def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>; 691539Srgrimes} 701539Srgrimes 711539Srgrimes// 64-bit General-purpose registers 721539Srgrimesforeach Index = 0-31 in { 731539Srgrimes def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>, 741539Srgrimes DwarfRegNum<[Index, -2]>; 751539Srgrimes} 761539Srgrimes 771539Srgrimes// Floating-point registers 7872529Simpforeach Index = 0-31 in { 7973254Sdeischen def F#Index : FPR<Index, "f"#Index>, 8072529Simp DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>; 811539Srgrimes} 821539Srgrimes 831539Srgrimes// Vector registers 841539Srgrimesforeach Index = 0-31 in { 851539Srgrimes def V#Index : VR<Index, "v"#Index>, 861539Srgrimes DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>; 871539Srgrimes} 881539Srgrimes 891539Srgrimes// The reprsentation of r0 when treated as the constant 0. 901539Srgrimesdef ZERO : GPR<0, "0">; 911539Srgrimesdef ZERO8 : GP8<ZERO, "0">; 921539Srgrimes 931539Srgrimes// Representations of the frame pointer used by ISD::FRAMEADDR. 941539Srgrimesdef FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">; 951539Srgrimesdef FP8 : GP8<FP, "**FRAME POINTER**">; 961539Srgrimes 971539Srgrimes// Representations of the base pointer used by setjmp. 981539Srgrimesdef BP : GPR<0 /* arbitrary */, "**BASE POINTER**">; 991539Srgrimesdef BP8 : GP8<BP, "**BASE POINTER**">; 1001539Srgrimes 1011539Srgrimes// Condition register bits 1021539Srgrimesdef CR0LT : CRBIT< 0, "0">; 1031539Srgrimesdef CR0GT : CRBIT< 1, "1">; 1041539Srgrimesdef CR0EQ : CRBIT< 2, "2">; 1051539Srgrimesdef CR0UN : CRBIT< 3, "3">; 1061539Srgrimesdef CR1LT : CRBIT< 4, "4">; 1071539Srgrimesdef CR1GT : CRBIT< 5, "5">; 1081539Srgrimesdef CR1EQ : CRBIT< 6, "6">; 1091539Srgrimesdef CR1UN : CRBIT< 7, "7">; 1101539Srgrimesdef CR2LT : CRBIT< 8, "8">; 1111539Srgrimesdef CR2GT : CRBIT< 9, "9">; 1121539Srgrimesdef CR2EQ : CRBIT<10, "10">; 1131539Srgrimesdef CR2UN : CRBIT<11, "11">; 1141539Srgrimesdef CR3LT : CRBIT<12, "12">; 1151539Srgrimesdef CR3GT : CRBIT<13, "13">; 1161539Srgrimesdef CR3EQ : CRBIT<14, "14">; 1171539Srgrimesdef CR3UN : CRBIT<15, "15">; 11893032Simpdef CR4LT : CRBIT<16, "16">; 11993032Simpdef CR4GT : CRBIT<17, "17">; 12093032Simpdef CR4EQ : CRBIT<18, "18">; 12193032Simpdef CR4UN : CRBIT<19, "19">; 1221539Srgrimesdef CR5LT : CRBIT<20, "20">; 1231539Srgrimesdef CR5GT : CRBIT<21, "21">; 1241539Srgrimesdef CR5EQ : CRBIT<22, "22">; 12572529Simpdef CR5UN : CRBIT<23, "23">; 1261539Srgrimesdef CR6LT : CRBIT<24, "24">; 1271539Srgrimesdef CR6GT : CRBIT<25, "25">; 1281539Srgrimesdef CR6EQ : CRBIT<26, "26">; 1291539Srgrimesdef CR6UN : CRBIT<27, "27">; 1301539Srgrimesdef CR7LT : CRBIT<28, "28">; 1311539Srgrimesdef CR7GT : CRBIT<29, "29">; 1321539Srgrimesdef CR7EQ : CRBIT<30, "30">; 1331539Srgrimesdef CR7UN : CRBIT<31, "31">; 1341539Srgrimes 1351539Srgrimes// Condition registers 1361539Srgrimeslet SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in { 1371539Srgrimesdef CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>; 1381539Srgrimesdef CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>; 1391539Srgrimesdef CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>; 1401539Srgrimesdef CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>; 14181600Speterdef CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>; 14281600Speterdef CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>; 14381600Speterdef CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; 1441539Srgrimesdef CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; 1451539Srgrimes} 1461539Srgrimes 1471539Srgrimes// The full condition-code register. This is not modeled fully, but defined 1481539Srgrimes// here primarily, for compatibility with gcc, to allow the inline asm "cc" 1491539Srgrimes// clobber specification to work. 1501539Srgrimesdef CC : PPCReg<"cc">, DwarfRegAlias<CR0> { 1511539Srgrimes let Aliases = [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]; 1521539Srgrimes} 1531539Srgrimes 1541539Srgrimes// Link register 1551539Srgrimesdef LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 1561539Srgrimes//let Aliases = [LR] in 15713771Smppdef LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 15813771Smpp 1591539Srgrimes// Count register 1601539Srgrimesdef CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 16137489Speterdef CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 16272372Sdeischen 1631539Srgrimes// VRsave register 1641539Srgrimesdef VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 1651539Srgrimes 1661539Srgrimes// Carry bit. In the architecture this is really bit 0 of the XER register 1671539Srgrimes// (which really is SPR register 1); this is the only bit interesting to a 1681539Srgrimes// compiler. 1691539Srgrimesdef CARRY: SPR<1, "ca">; 1701539Srgrimes 1711539Srgrimes// FP rounding mode: bits 30 and 31 of the FP status and control register 1721539Srgrimes// This is not allocated as a normal register; it appears only in 1731539Srgrimes// Uses and Defs. The ABI says it needs to be preserved by a function, 1741539Srgrimes// but this is not achieved by saving and restoring it as with 1751539Srgrimes// most registers, it has to be done in code; to make this work all the 1761539Srgrimes// return and call instructions are described as Uses of RM, so instructions 1771539Srgrimes// that do nothing but change RM will not get deleted. 1781539Srgrimes// Also, in the architecture it is not really a SPR; 512 is arbitrary. 1791539Srgrimesdef RM: SPR<512, "**ROUNDING MODE**">; 1801539Srgrimes 1811539Srgrimes/// Register classes 1821539Srgrimes// Allocate volatiles first 1831539Srgrimes// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 1841539Srgrimesdef GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12), 1851539Srgrimes (sequence "R%u", 30, 13), 1861539Srgrimes R31, R0, R1, FP, BP)>; 1871539Srgrimes 1881539Srgrimesdef G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12), 1891539Srgrimes (sequence "X%u", 30, 14), 190100133Swollman X31, X13, X0, X1, FP8, BP8)>; 1911539Srgrimes 1921539Srgrimes// For some instructions r0 is special (representing the value 0 instead of 1931539Srgrimes// the value in the r0 register), and we use these register subclasses to 1941539Srgrimes// prevent r0 from being allocated for use by those instructions. 1951539Srgrimesdef GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>; 1961539Srgrimesdef G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>; 1971539Srgrimes 1981539Srgrimes// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 1991539Srgrimes// ABI the size of the Floating-point register save area is determined by the 2001539Srgrimes// allocated non-volatile register with the lowest register number, as FP 2011539Srgrimes// register N is spilled to offset 8 * (32 - N) below the back chain word of the 2021539Srgrimes// previous stack frame. By allocating non-volatiles in reverse order we make 2031539Srgrimes// sure that the Floating-point register save area is always as small as 2041539Srgrimes// possible because there aren't any unused spill slots. 2051539Srgrimesdef F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13), 20681600Speter (sequence "F%u", 31, 14))>; 20781600Speterdef F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>; 20881600Speter 2091539Srgrimesdef VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128, 210100133Swollman (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11, 2111539Srgrimes V12, V13, V14, V15, V16, V17, V18, V19, V31, V30, 2121539Srgrimes V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>; 2131539Srgrimes 21493032Simpdef CRBITRC : RegisterClass<"PPC", [i32], 32, 21593032Simp (add CR0LT, CR0GT, CR0EQ, CR0UN, 21693032Simp CR1LT, CR1GT, CR1EQ, CR1UN, 21793032Simp CR2LT, CR2GT, CR2EQ, CR2UN, 21893032Simp CR3LT, CR3GT, CR3EQ, CR3UN, 21993032Simp CR4LT, CR4GT, CR4EQ, CR4UN, 220104989Smike CR5LT, CR5GT, CR5EQ, CR5UN, 221104989Smike CR6LT, CR6GT, CR6EQ, CR6UN, 222104989Smike CR7LT, CR7GT, CR7EQ, CR7UN)> 223103012Stjr{ 22493032Simp let CopyCost = -1; 225104989Smike} 226104989Smike 227104989Smikedef CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6, 228104989Smike CR7, CR2, CR3, CR4)>; 22993032Simp 23093032Simp// The CTR registers are not allocatable because they're used by the 23193032Simp// decrement-and-branch instructions, and thus need to stay live across 232104989Smike// multiple basic blocks. 23393032Simpdef CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> { 23493032Simp let isAllocatable = 0; 23593032Simp} 23693032Simpdef CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> { 237103012Stjr let isAllocatable = 0; 23893032Simp} 23993032Simp 24093032Simpdef VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>; 24193032Simpdef CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> { 24293032Simp let CopyCost = -1; 24393032Simp} 244104989Smike 245103012Stjrdef CCRC : RegisterClass<"PPC", [i32], 32, (add CC)> { 246103012Stjr let isAllocatable = 0; 247103012Stjr} 248104989Smike 24993032Simp