PPCInstrAltivec.td revision 263508
1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Altivec extension to the PowerPC instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Altivec transformation functions and pattern fragments. 16// 17 18// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 19// of that type. 20def vnot_ppc : PatFrag<(ops node:$in), 21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 22 23def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24 (vector_shuffle node:$lhs, node:$rhs), [{ 25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 26}]>; 27def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 28 (vector_shuffle node:$lhs, node:$rhs), [{ 29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 30}]>; 31def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 32 (vector_shuffle node:$lhs, node:$rhs), [{ 33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 34}]>; 35def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 36 (vector_shuffle node:$lhs, node:$rhs), [{ 37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 38}]>; 39 40 41def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 42 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 43 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 44}]>; 45def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 48}]>; 49def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 51 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 52}]>; 53def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 55 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 56}]>; 57def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 59 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 60}]>; 61def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 63 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 64}]>; 65 66 67def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 69 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 70}]>; 71def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 72 (vector_shuffle node:$lhs, node:$rhs), [{ 73 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 74}]>; 75def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 76 (vector_shuffle node:$lhs, node:$rhs), [{ 77 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 78}]>; 79def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 80 (vector_shuffle node:$lhs, node:$rhs), [{ 81 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 82}]>; 83def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 84 (vector_shuffle node:$lhs, node:$rhs), [{ 85 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 86}]>; 87def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 88 (vector_shuffle node:$lhs, node:$rhs), [{ 89 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 90}]>; 91 92 93def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 94 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false)); 95}]>; 96def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 97 (vector_shuffle node:$lhs, node:$rhs), [{ 98 return PPC::isVSLDOIShuffleMask(N, false) != -1; 99}], VSLDOI_get_imm>; 100 101 102/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 103/// vector_shuffle(X,undef,mask) by the dag combiner. 104def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 105 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true)); 106}]>; 107def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 108 (vector_shuffle node:$lhs, node:$rhs), [{ 109 return PPC::isVSLDOIShuffleMask(N, true) != -1; 110}], VSLDOI_unary_get_imm>; 111 112 113// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 114def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 115 return getI32Imm(PPC::getVSPLTImmediate(N, 1)); 116}]>; 117def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 118 (vector_shuffle node:$lhs, node:$rhs), [{ 119 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 120}], VSPLTB_get_imm>; 121def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 122 return getI32Imm(PPC::getVSPLTImmediate(N, 2)); 123}]>; 124def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125 (vector_shuffle node:$lhs, node:$rhs), [{ 126 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 127}], VSPLTH_get_imm>; 128def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 129 return getI32Imm(PPC::getVSPLTImmediate(N, 4)); 130}]>; 131def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 132 (vector_shuffle node:$lhs, node:$rhs), [{ 133 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 134}], VSPLTW_get_imm>; 135 136 137// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 138def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 139 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 140}]>; 141def vecspltisb : PatLeaf<(build_vector), [{ 142 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 143}], VSPLTISB_get_imm>; 144 145// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 146def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 147 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 148}]>; 149def vecspltish : PatLeaf<(build_vector), [{ 150 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 151}], VSPLTISH_get_imm>; 152 153// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 154def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 155 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 156}]>; 157def vecspltisw : PatLeaf<(build_vector), [{ 158 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 159}], VSPLTISW_get_imm>; 160 161//===----------------------------------------------------------------------===// 162// Helpers for defining instructions that directly correspond to intrinsics. 163 164// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 165class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 166 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 167 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 168 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 169 170// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 171// inputs doesn't match the type of the output. 172class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 173 ValueType InTy> 174 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 175 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 176 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 177 178// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 179// input types and an output type. 180class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 181 ValueType In1Ty, ValueType In2Ty> 182 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 183 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 184 [(set OutTy:$vD, 185 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 186 187// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 188class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 189 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 190 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 191 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 192 193// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 194// inputs doesn't match the type of the output. 195class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 196 ValueType InTy> 197 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 198 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 199 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 200 201// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 202// input types and an output type. 203class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 204 ValueType In1Ty, ValueType In2Ty> 205 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 206 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 207 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 208 209// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 210class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 211 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 212 !strconcat(opc, " $vD, $vB"), VecFP, 213 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 214 215// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 216// inputs doesn't match the type of the output. 217class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 218 ValueType InTy> 219 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 220 !strconcat(opc, " $vD, $vB"), VecFP, 221 [(set OutTy:$vD, (IntID InTy:$vB))]>; 222 223//===----------------------------------------------------------------------===// 224// Instruction Definitions. 225 226def HasAltivec : Predicate<"PPCSubTarget.hasAltivec()">; 227let Predicates = [HasAltivec] in { 228 229let isCodeGenOnly = 1 in { 230def DSS : DSS_Form<822, (outs), 231 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), 232 "dss $STRM", LdStLoad /*FIXME*/, []>, 233 Deprecated<DeprecatedDST>; 234def DSSALL : DSS_Form<822, (outs), 235 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), 236 "dssall", LdStLoad /*FIXME*/, []>, 237 Deprecated<DeprecatedDST>; 238def DST : DSS_Form<342, (outs), 239 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), 240 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, 241 Deprecated<DeprecatedDST>; 242def DSTT : DSS_Form<342, (outs), 243 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), 244 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, 245 Deprecated<DeprecatedDST>; 246def DSTST : DSS_Form<374, (outs), 247 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), 248 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, 249 Deprecated<DeprecatedDST>; 250def DSTSTT : DSS_Form<374, (outs), 251 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), 252 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, 253 Deprecated<DeprecatedDST>; 254 255def DST64 : DSS_Form<342, (outs), 256 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), 257 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, 258 Deprecated<DeprecatedDST>; 259def DSTT64 : DSS_Form<342, (outs), 260 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), 261 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, 262 Deprecated<DeprecatedDST>; 263def DSTST64 : DSS_Form<374, (outs), 264 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), 265 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, 266 Deprecated<DeprecatedDST>; 267def DSTSTT64 : DSS_Form<374, (outs), 268 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), 269 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, 270 Deprecated<DeprecatedDST>; 271} 272 273def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 274 "mfvscr $vD", LdStStore, 275 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 276def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 277 "mtvscr $vB", LdStLoad, 278 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 279 280let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 281def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src), 282 "lvebx $vD, $src", LdStLoad, 283 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 284def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src), 285 "lvehx $vD, $src", LdStLoad, 286 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 287def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src), 288 "lvewx $vD, $src", LdStLoad, 289 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 290def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src), 291 "lvx $vD, $src", LdStLoad, 292 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 293def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src), 294 "lvxl $vD, $src", LdStLoad, 295 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 296} 297 298def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src), 299 "lvsl $vD, $src", LdStLoad, 300 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 301 PPC970_Unit_LSU; 302def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src), 303 "lvsr $vD, $src", LdStLoad, 304 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 305 PPC970_Unit_LSU; 306 307let PPC970_Unit = 2 in { // Stores. 308def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 309 "stvebx $rS, $dst", LdStStore, 310 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 311def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 312 "stvehx $rS, $dst", LdStStore, 313 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 314def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 315 "stvewx $rS, $dst", LdStStore, 316 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 317def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 318 "stvx $rS, $dst", LdStStore, 319 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 320def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 321 "stvxl $rS, $dst", LdStStore, 322 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 323} 324 325let PPC970_Unit = 5 in { // VALU Operations. 326// VA-Form instructions. 3-input AltiVec ops. 327def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 328 "vmaddfp $vD, $vA, $vC, $vB", VecFP, 329 [(set v4f32:$vD, 330 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 331 332// FIXME: The fma+fneg pattern won't match because fneg is not legal. 333def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 334 "vnmsubfp $vD, $vA, $vC, $vB", VecFP, 335 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 336 (fneg v4f32:$vB))))]>; 337 338def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 339def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 340 v8i16>; 341def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 342 343def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 344 v4i32, v4i32, v16i8>; 345def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 346 347// Shuffles. 348def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH), 349 "vsldoi $vD, $vA, $vB, $SH", VecFP, 350 [(set v16i8:$vD, 351 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>; 352 353// VX-Form instructions. AltiVec arithmetic ops. 354def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 355 "vaddfp $vD, $vA, $vB", VecFP, 356 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 357 358def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 359 "vaddubm $vD, $vA, $vB", VecGeneral, 360 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 361def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 362 "vadduhm $vD, $vA, $vB", VecGeneral, 363 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 364def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 365 "vadduwm $vD, $vA, $vB", VecGeneral, 366 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 367 368def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 369def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 370def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 371def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 372def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 373def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 374def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 375 376 377def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 378 "vand $vD, $vA, $vB", VecFP, 379 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 380def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 381 "vandc $vD, $vA, $vB", VecFP, 382 [(set v4i32:$vD, (and v4i32:$vA, 383 (vnot_ppc v4i32:$vB)))]>; 384 385def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 386 "vcfsx $vD, $vB, $UIMM", VecFP, 387 [(set v4f32:$vD, 388 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; 389def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 390 "vcfux $vD, $vB, $UIMM", VecFP, 391 [(set v4f32:$vD, 392 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; 393def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 394 "vctsxs $vD, $vB, $UIMM", VecFP, 395 [(set v4i32:$vD, 396 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; 397def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 398 "vctuxs $vD, $vB, $UIMM", VecFP, 399 [(set v4i32:$vD, 400 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; 401 402// Defines with the UIM field set to 0 for floating-point 403// to integer (fp_to_sint/fp_to_uint) conversions and integer 404// to floating-point (sint_to_fp/uint_to_fp) conversions. 405let isCodeGenOnly = 1, VA = 0 in { 406def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 407 "vcfsx $vD, $vB, 0", VecFP, 408 [(set v4f32:$vD, 409 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 410def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 411 "vctuxs $vD, $vB, 0", VecFP, 412 [(set v4i32:$vD, 413 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 414def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 415 "vcfux $vD, $vB, 0", VecFP, 416 [(set v4f32:$vD, 417 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 418def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 419 "vctsxs $vD, $vB, 0", VecFP, 420 [(set v4i32:$vD, 421 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 422} 423def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 424def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 425 426def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 427def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 428def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 429def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 430def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 431def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 432 433def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 434def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 435def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 436def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 437def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 438def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 439def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 440def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 441def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 442def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 443def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 444def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 445def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 446def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 447 448def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 449 "vmrghb $vD, $vA, $vB", VecFP, 450 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 451def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 452 "vmrghh $vD, $vA, $vB", VecFP, 453 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 454def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 455 "vmrghw $vD, $vA, $vB", VecFP, 456 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 457def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 458 "vmrglb $vD, $vA, $vB", VecFP, 459 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 460def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 461 "vmrglh $vD, $vA, $vB", VecFP, 462 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 463def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 464 "vmrglw $vD, $vA, $vB", VecFP, 465 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 466 467def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 468 v4i32, v16i8, v4i32>; 469def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 470 v4i32, v8i16, v4i32>; 471def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 472 v4i32, v8i16, v4i32>; 473def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 474 v4i32, v16i8, v4i32>; 475def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 476 v4i32, v8i16, v4i32>; 477def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 478 v4i32, v8i16, v4i32>; 479 480def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 481 v8i16, v16i8>; 482def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 483 v4i32, v8i16>; 484def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 485 v8i16, v16i8>; 486def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 487 v4i32, v8i16>; 488def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 489 v8i16, v16i8>; 490def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 491 v4i32, v8i16>; 492def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 493 v8i16, v16i8>; 494def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 495 v4i32, v8i16>; 496 497def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 498def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 499def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 500def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 501def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 502def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 503 504def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 505 506def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 507 "vsubfp $vD, $vA, $vB", VecGeneral, 508 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 509def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 510 "vsububm $vD, $vA, $vB", VecGeneral, 511 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 512def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 513 "vsubuhm $vD, $vA, $vB", VecGeneral, 514 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 515def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 516 "vsubuwm $vD, $vA, $vB", VecGeneral, 517 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 518 519def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 520def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 521def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 522def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 523def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 524def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 525 526def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 527def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 528 529def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 530 v4i32, v16i8, v4i32>; 531def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 532 v4i32, v8i16, v4i32>; 533def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 534 v4i32, v16i8, v4i32>; 535 536def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 537 "vnor $vD, $vA, $vB", VecFP, 538 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 539 v4i32:$vB)))]>; 540def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 541 "vor $vD, $vA, $vB", VecFP, 542 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 543def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 544 "vxor $vD, $vA, $vB", VecFP, 545 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 546 547def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 548def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 549def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 550 551def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 552def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 553 554def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 555def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 556def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 557 558def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 559 "vspltb $vD, $vB, $UIMM", VecPerm, 560 [(set v16i8:$vD, 561 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 562def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 563 "vsplth $vD, $vB, $UIMM", VecPerm, 564 [(set v16i8:$vD, 565 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 566def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 567 "vspltw $vD, $vB, $UIMM", VecPerm, 568 [(set v16i8:$vD, 569 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 570 571def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 572def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 573 574def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 575def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 576def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 577def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 578def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 579def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 580 581 582def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 583 "vspltisb $vD, $SIMM", VecPerm, 584 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 585def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 586 "vspltish $vD, $SIMM", VecPerm, 587 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 588def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 589 "vspltisw $vD, $SIMM", VecPerm, 590 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 591 592// Vector Pack. 593def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 594 v8i16, v4i32>; 595def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 596 v16i8, v8i16>; 597def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 598 v16i8, v8i16>; 599def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 600 v16i8, v4i32>; 601def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 602 v8i16, v4i32>; 603def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 604 "vpkuhum $vD, $vA, $vB", VecFP, 605 [(set v16i8:$vD, 606 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 607def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 608 v16i8, v8i16>; 609def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 610 "vpkuwum $vD, $vA, $vB", VecFP, 611 [(set v16i8:$vD, 612 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 613def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 614 v8i16, v4i32>; 615 616// Vector Unpack. 617def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 618 v4i32, v8i16>; 619def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 620 v8i16, v16i8>; 621def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 622 v4i32, v8i16>; 623def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 624 v4i32, v8i16>; 625def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 626 v8i16, v16i8>; 627def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 628 v4i32, v8i16>; 629 630 631// Altivec Comparisons. 632 633class VCMP<bits<10> xo, string asmstr, ValueType Ty> 634 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),asmstr,VecFPCompare, 635 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 636class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 637 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),asmstr,VecFPCompare, 638 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 639 let Defs = [CR6]; 640 let RC = 1; 641} 642 643// f32 element comparisons.0 644def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 645def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 646def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 647def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 648def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 649def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 650def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 651def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 652 653// i8 element comparisons. 654def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 655def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 656def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 657def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 658def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 659def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 660 661// i16 element comparisons. 662def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 663def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 664def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 665def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 666def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 667def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 668 669// i32 element comparisons. 670def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 671def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 672def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 673def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 674def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 675def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 676 677let isCodeGenOnly = 1 in { 678def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 679 "vxor $vD, $vD, $vD", VecFP, 680 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 681def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 682 "vxor $vD, $vD, $vD", VecFP, 683 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 684def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 685 "vxor $vD, $vD, $vD", VecFP, 686 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 687 688let IMM=-1 in { 689def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 690 "vspltisw $vD, -1", VecFP, 691 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 692def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 693 "vspltisw $vD, -1", VecFP, 694 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 695def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 696 "vspltisw $vD, -1", VecFP, 697 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 698} 699} 700} // VALU Operations. 701 702//===----------------------------------------------------------------------===// 703// Additional Altivec Patterns 704// 705 706// DS* intrinsics 707def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; 708def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; 709 710// * 32-bit 711def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM), 712 (DST 0, imm:$STRM, $rA, $rB)>; 713def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM), 714 (DSTT 1, imm:$STRM, $rA, $rB)>; 715def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM), 716 (DSTST 0, imm:$STRM, $rA, $rB)>; 717def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM), 718 (DSTSTT 1, imm:$STRM, $rA, $rB)>; 719 720// * 64-bit 721def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM), 722 (DST64 0, imm:$STRM, $rA, $rB)>; 723def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM), 724 (DSTT64 1, imm:$STRM, $rA, $rB)>; 725def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM), 726 (DSTST64 0, imm:$STRM, $rA, $rB)>; 727def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM), 728 (DSTSTT64 1, imm:$STRM, $rA, $rB)>; 729 730// Loads. 731def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 732 733// Stores. 734def : Pat<(store v4i32:$rS, xoaddr:$dst), 735 (STVX $rS, xoaddr:$dst)>; 736 737// Bit conversions. 738def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 739def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 740def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 741 742def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 743def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 744def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 745 746def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 747def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 748def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 749 750def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 751def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 752def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 753 754// Shuffles. 755 756// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 757def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 758 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 759def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 760 (VPKUWUM $vA, $vA)>; 761def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 762 (VPKUHUM $vA, $vA)>; 763 764// Match vmrg*(x,x) 765def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 766 (VMRGLB $vA, $vA)>; 767def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 768 (VMRGLH $vA, $vA)>; 769def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 770 (VMRGLW $vA, $vA)>; 771def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 772 (VMRGHB $vA, $vA)>; 773def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 774 (VMRGHH $vA, $vA)>; 775def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 776 (VMRGHW $vA, $vA)>; 777 778// Logical Operations 779def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 780 781def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 782 (VNOR $A, $B)>; 783def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 784 (VANDC $A, $B)>; 785 786def : Pat<(fmul v4f32:$vA, v4f32:$vB), 787 (VMADDFP $vA, $vB, 788 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>; 789 790// Fused multiply add and multiply sub for packed float. These are represented 791// separately from the real instructions above, for operations that must have 792// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 793def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 794 (VMADDFP $A, $B, $C)>; 795def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 796 (VNMSUBFP $A, $B, $C)>; 797 798def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 799 (VMADDFP $A, $B, $C)>; 800def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 801 (VNMSUBFP $A, $B, $C)>; 802 803def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 804 (VPERM $vA, $vB, $vC)>; 805 806def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 807def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 808 809// Vector shifts 810def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 811 (v16i8 (VSLB $vA, $vB))>; 812def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 813 (v8i16 (VSLH $vA, $vB))>; 814def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 815 (v4i32 (VSLW $vA, $vB))>; 816 817def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 818 (v16i8 (VSRB $vA, $vB))>; 819def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 820 (v8i16 (VSRH $vA, $vB))>; 821def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 822 (v4i32 (VSRW $vA, $vB))>; 823 824def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 825 (v16i8 (VSRAB $vA, $vB))>; 826def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 827 (v8i16 (VSRAH $vA, $vB))>; 828def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 829 (v4i32 (VSRAW $vA, $vB))>; 830 831// Float to integer and integer to float conversions 832def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 833 (VCTSXS_0 $vA)>; 834def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 835 (VCTUXS_0 $vA)>; 836def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 837 (VCFSX_0 $vA)>; 838def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 839 (VCFUX_0 $vA)>; 840 841// Floating-point rounding 842def : Pat<(v4f32 (ffloor v4f32:$vA)), 843 (VRFIM $vA)>; 844def : Pat<(v4f32 (fceil v4f32:$vA)), 845 (VRFIP $vA)>; 846def : Pat<(v4f32 (ftrunc v4f32:$vA)), 847 (VRFIZ $vA)>; 848def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 849 (VRFIN $vA)>; 850 851} // end HasAltivec 852 853