PPCCallingConv.td revision 263508 
1//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This describes the calling conventions for the PowerPC 32- and 64-bit
11// architectures.
12//
13//===----------------------------------------------------------------------===//
14
15/// CCIfSubtarget - Match if the current subtarget has a feature F.
16class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
18
19//===----------------------------------------------------------------------===//
20// Return Value Calling Convention
21//===----------------------------------------------------------------------===//
22
23// Return-value convention for PowerPC
24def RetCC_PPC : CallingConv<[
25  // On PPC64, integer return values are always promoted to i64
26  CCIfType<[i32], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
27
28  CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
29  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
30  CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
31  
32  CCIfType<[f32], CCAssignToReg<[F1, F2]>>,
33  CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>,
34  
35  // Vector types are always returned in V2.
36  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
37]>;
38
39
40// Note that we don't currently have calling conventions for 64-bit
41// PowerPC, but handle all the complexities of the ABI in the lowering
42// logic.  FIXME: See if the logic can be simplified with use of CCs.
43// This may require some extensions to current table generation.
44
45// Simple calling convention for 64-bit ELF PowerPC fast isel.
46// Only handle ints and floats.  All ints are promoted to i64.
47// Vector types and quadword ints are not handled.
48def CC_PPC64_ELF_FIS : CallingConv<[
49  CCIfType<[i8],  CCPromoteToType<i64>>,
50  CCIfType<[i16], CCPromoteToType<i64>>,
51  CCIfType<[i32], CCPromoteToType<i64>>,
52  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
53  CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
54]>;
55
56// Simple return-value convention for 64-bit ELF PowerPC fast isel.
57// All small ints are promoted to i64.  Vector types, quadword ints,
58// and multiple register returns are "supported" to avoid compile
59// errors, but none are handled by the fast selector.
60def RetCC_PPC64_ELF_FIS : CallingConv<[
61  CCIfType<[i8],   CCPromoteToType<i64>>,
62  CCIfType<[i16],  CCPromoteToType<i64>>,
63  CCIfType<[i32],  CCPromoteToType<i64>>,
64  CCIfType<[i64],  CCAssignToReg<[X3, X4]>>,
65  CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
66  CCIfType<[f32],  CCAssignToReg<[F1, F2]>>,
67  CCIfType<[f64],  CCAssignToReg<[F1, F2, F3, F4]>>,
68  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
69]>;
70
71//===----------------------------------------------------------------------===//
72// PowerPC System V Release 4 32-bit ABI
73//===----------------------------------------------------------------------===//
74
75def CC_PPC32_SVR4_Common : CallingConv<[
76  // The ABI requires i64 to be passed in two adjacent registers with the first
77  // register having an odd register number.
78  CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
79
80  // The first 8 integer arguments are passed in integer registers.
81  CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
82
83  // Make sure the i64 words from a long double are either both passed in
84  // registers or both passed on the stack.
85  CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
86  
87  // FP values are passed in F1 - F8.
88  CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
89
90  // Split arguments have an alignment of 8 bytes on the stack.
91  CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
92  
93  CCIfType<[i32], CCAssignToStack<4, 4>>,
94  
95  // Floats are stored in double precision format, thus they have the same
96  // alignment and size as doubles.
97  CCIfType<[f32,f64], CCAssignToStack<8, 8>>,  
98
99  // Vectors get 16-byte stack slots that are 16-byte aligned.
100  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>>
101]>;
102
103// This calling convention puts vector arguments always on the stack. It is used
104// to assign vector arguments which belong to the variable portion of the
105// parameter list of a variable argument function.
106def CC_PPC32_SVR4_VarArg : CallingConv<[
107  CCDelegateTo<CC_PPC32_SVR4_Common>
108]>;
109
110// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
111// put vector arguments in vector registers before putting them on the stack.
112def CC_PPC32_SVR4 : CallingConv<[
113  // The first 12 Vector arguments are passed in AltiVec registers.
114  CCIfType<[v16i8, v8i16, v4i32, v4f32],
115           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
116           
117  CCDelegateTo<CC_PPC32_SVR4_Common>
118]>;  
119
120// Helper "calling convention" to handle aggregate by value arguments.
121// Aggregate by value arguments are always placed in the local variable space
122// of the caller. This calling convention is only used to assign those stack
123// offsets in the callers stack frame.
124//
125// Still, the address of the aggregate copy in the callers stack frame is passed
126// in a GPR (or in the parameter list area if all GPRs are allocated) from the
127// caller to the callee. The location for the address argument is assigned by
128// the CC_PPC32_SVR4 calling convention.
129//
130// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
131// not passed by value.
132 
133def CC_PPC32_SVR4_ByVal : CallingConv<[
134  CCIfByVal<CCPassByVal<4, 4>>,
135  
136  CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
137]>;
138
139def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
140                                       V28, V29, V30, V31)>;
141
142def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
143                                        R21, R22, R23, R24, R25, R26, R27, R28,
144                                        R29, R30, R31, F14, F15, F16, F17, F18,
145                                        F19, F20, F21, F22, F23, F24, F25, F26,
146                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
147                                   )>;
148
149def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
150
151def CSR_SVR432   : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
152                                        R21, R22, R23, R24, R25, R26, R27, R28,
153                                        R29, R30, R31, F14, F15, F16, F17, F18,
154                                        F19, F20, F21, F22, F23, F24, F25, F26,
155                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
156                                   )>;
157
158def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
159
160def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
161                                        X21, X22, X23, X24, X25, X26, X27, X28,
162                                        X29, X30, X31, F14, F15, F16, F17, F18,
163                                        F19, F20, F21, F22, F23, F24, F25, F26,
164                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
165                                   )>;
166
167def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
168
169def CSR_SVR464   : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
170                                        X21, X22, X23, X24, X25, X26, X27, X28,
171                                        X29, X30, X31, F14, F15, F16, F17, F18,
172                                        F19, F20, F21, F22, F23, F24, F25, F26,
173                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
174                                   )>;
175
176
177def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
178
179def CSR_NoRegs : CalleeSavedRegs<(add)>;
180
181