NVPTXTargetMachine.cpp revision 263508
1//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Top-level implementation for the NVPTX target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "NVPTXTargetMachine.h"
15#include "MCTargetDesc/NVPTXMCAsmInfo.h"
16#include "NVPTX.h"
17#include "NVPTXAllocaHoisting.h"
18#include "NVPTXLowerAggrCopies.h"
19#include "NVPTXSplitBBatBar.h"
20#include "llvm/ADT/OwningPtr.h"
21#include "llvm/Analysis/Passes.h"
22#include "llvm/Analysis/Verifier.h"
23#include "llvm/Assembly/PrintModulePass.h"
24#include "llvm/CodeGen/AsmPrinter.h"
25#include "llvm/CodeGen/MachineFunctionAnalysis.h"
26#include "llvm/CodeGen/MachineModuleInfo.h"
27#include "llvm/CodeGen/Passes.h"
28#include "llvm/IR/DataLayout.h"
29#include "llvm/MC/MCAsmInfo.h"
30#include "llvm/MC/MCInstrInfo.h"
31#include "llvm/MC/MCStreamer.h"
32#include "llvm/MC/MCSubtargetInfo.h"
33#include "llvm/PassManager.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/FormattedStream.h"
37#include "llvm/Support/TargetRegistry.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/Target/TargetInstrInfo.h"
40#include "llvm/Target/TargetLowering.h"
41#include "llvm/Target/TargetLoweringObjectFile.h"
42#include "llvm/Target/TargetMachine.h"
43#include "llvm/Target/TargetOptions.h"
44#include "llvm/Target/TargetRegisterInfo.h"
45#include "llvm/Target/TargetSubtargetInfo.h"
46#include "llvm/Transforms/Scalar.h"
47
48using namespace llvm;
49
50namespace llvm {
51void initializeNVVMReflectPass(PassRegistry&);
52void initializeGenericToNVVMPass(PassRegistry&);
53}
54
55extern "C" void LLVMInitializeNVPTXTarget() {
56  // Register the target.
57  RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
58  RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
59
60  // FIXME: This pass is really intended to be invoked during IR optimization,
61  // but it's very NVPTX-specific.
62  initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
63  initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
64}
65
66NVPTXTargetMachine::NVPTXTargetMachine(
67    const Target &T, StringRef TT, StringRef CPU, StringRef FS,
68    const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
69    CodeGenOpt::Level OL, bool is64bit)
70    : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
71      Subtarget(TT, CPU, FS, is64bit), DL(Subtarget.getDataLayout()),
72      InstrInfo(*this), TLInfo(*this), TSInfo(*this),
73      FrameLowering(
74          *this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {
75  initAsmInfo();
76}
77
78void NVPTXTargetMachine32::anchor() {}
79
80NVPTXTargetMachine32::NVPTXTargetMachine32(
81    const Target &T, StringRef TT, StringRef CPU, StringRef FS,
82    const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
83    CodeGenOpt::Level OL)
84    : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
85
86void NVPTXTargetMachine64::anchor() {}
87
88NVPTXTargetMachine64::NVPTXTargetMachine64(
89    const Target &T, StringRef TT, StringRef CPU, StringRef FS,
90    const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
91    CodeGenOpt::Level OL)
92    : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
93
94namespace {
95class NVPTXPassConfig : public TargetPassConfig {
96public:
97  NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
98      : TargetPassConfig(TM, PM) {}
99
100  NVPTXTargetMachine &getNVPTXTargetMachine() const {
101    return getTM<NVPTXTargetMachine>();
102  }
103
104  virtual void addIRPasses();
105  virtual bool addInstSelector();
106  virtual bool addPreRegAlloc();
107  virtual bool addPostRegAlloc();
108
109  virtual FunctionPass *createTargetRegisterAllocator(bool) LLVM_OVERRIDE;
110  virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
111  virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
112};
113} // end anonymous namespace
114
115TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
116  NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
117  return PassConfig;
118}
119
120void NVPTXPassConfig::addIRPasses() {
121  // The following passes are known to not play well with virtual regs hanging
122  // around after register allocation (which in our case, is *all* registers).
123  // We explicitly disable them here.  We do, however, need some functionality
124  // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
125  // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
126  disablePass(&PrologEpilogCodeInserterID);
127  disablePass(&MachineCopyPropagationID);
128  disablePass(&BranchFolderPassID);
129  disablePass(&TailDuplicateID);
130
131  TargetPassConfig::addIRPasses();
132  addPass(createGenericToNVVMPass());
133}
134
135bool NVPTXPassConfig::addInstSelector() {
136  addPass(createLowerAggrCopies());
137  addPass(createSplitBBatBarPass());
138  addPass(createAllocaHoisting());
139  addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
140  return false;
141}
142
143bool NVPTXPassConfig::addPreRegAlloc() { return false; }
144bool NVPTXPassConfig::addPostRegAlloc() {
145  addPass(createNVPTXPrologEpilogPass());
146  return false;
147}
148
149FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
150  return 0; // No reg alloc
151}
152
153void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
154  assert(!RegAllocPass && "NVPTX uses no regalloc!");
155  addPass(&PHIEliminationID);
156  addPass(&TwoAddressInstructionPassID);
157}
158
159void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
160  assert(!RegAllocPass && "NVPTX uses no regalloc!");
161
162  addPass(&ProcessImplicitDefsID);
163  addPass(&LiveVariablesID);
164  addPass(&MachineLoopInfoID);
165  addPass(&PHIEliminationID);
166
167  addPass(&TwoAddressInstructionPassID);
168  addPass(&RegisterCoalescerID);
169
170  // PreRA instruction scheduling.
171  if (addPass(&MachineSchedulerID))
172    printAndVerify("After Machine Scheduling");
173
174
175  addPass(&StackSlotColoringID);
176
177  // FIXME: Needs physical registers
178  //addPass(&PostRAMachineLICMID);
179
180  printAndVerify("After StackSlotColoring");
181}
182