MipsSERegisterInfo.cpp revision 263508
1228753Smm//===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===// 2228753Smm// 3228753Smm// The LLVM Compiler Infrastructure 4228753Smm// 5228753Smm// This file is distributed under the University of Illinois Open Source 6228753Smm// License. See LICENSE.TXT for details. 7228753Smm// 8228753Smm//===----------------------------------------------------------------------===// 9228753Smm// 10228753Smm// This file contains the MIPS32/64 implementation of the TargetRegisterInfo 11228753Smm// class. 12228753Smm// 13228753Smm//===----------------------------------------------------------------------===// 14228753Smm 15228753Smm#include "MipsSERegisterInfo.h" 16228753Smm#include "Mips.h" 17228753Smm#include "MipsAnalyzeImmediate.h" 18228753Smm#include "MipsMachineFunction.h" 19228753Smm#include "MipsSEInstrInfo.h" 20228753Smm#include "MipsSubtarget.h" 21228753Smm#include "llvm/ADT/BitVector.h" 22228753Smm#include "llvm/ADT/STLExtras.h" 23228753Smm#include "llvm/CodeGen/MachineFrameInfo.h" 24228753Smm#include "llvm/CodeGen/MachineFunction.h" 25228753Smm#include "llvm/CodeGen/MachineInstrBuilder.h" 26228753Smm#include "llvm/CodeGen/MachineRegisterInfo.h" 27228763Smm#include "llvm/CodeGen/ValueTypes.h" 28228753Smm#include "llvm/DebugInfo.h" 29228753Smm#include "llvm/IR/Constants.h" 30228753Smm#include "llvm/IR/Function.h" 31228753Smm#include "llvm/IR/Type.h" 32228753Smm#include "llvm/Support/CommandLine.h" 33228753Smm#include "llvm/Support/Debug.h" 34228753Smm#include "llvm/Support/ErrorHandling.h" 35228753Smm#include "llvm/Support/raw_ostream.h" 36228753Smm#include "llvm/Target/TargetFrameLowering.h" 37228753Smm#include "llvm/Target/TargetInstrInfo.h" 38228753Smm#include "llvm/Target/TargetMachine.h" 39228753Smm#include "llvm/Target/TargetOptions.h" 40228753Smm 41228753Smmusing namespace llvm; 42228753Smm 43228753SmmMipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST) 44228753Smm : MipsRegisterInfo(ST) {} 45228753Smm 46228753Smmbool MipsSERegisterInfo:: 47228753SmmrequiresRegisterScavenging(const MachineFunction &MF) const { 48228753Smm return true; 49228753Smm} 50228753Smm 51228753Smmbool MipsSERegisterInfo:: 52228753SmmrequiresFrameIndexScavenging(const MachineFunction &MF) const { 53228753Smm return true; 54368708Smm} 55228753Smm 56228753Smmconst TargetRegisterClass * 57228753SmmMipsSERegisterInfo::intRegClass(unsigned Size) const { 58228753Smm if (Size == 4) 59228753Smm return &Mips::GPR32RegClass; 60228753Smm 61228753Smm assert(Size == 8); 62228753Smm return &Mips::GPR64RegClass; 63228753Smm} 64228753Smm 65228753Smm/// Determine whether a given opcode is an MSA load/store (supporting 10-bit 66228753Smm/// offsets) or a non-MSA load/store (supporting 16-bit offsets). 67228753Smmstatic inline bool isMSALoadOrStore(const unsigned Opcode) { 68228753Smm switch (Opcode) { 69368708Smm case Mips::LD_B: 70368708Smm case Mips::LD_H: 71228753Smm case Mips::LD_W: 72228753Smm case Mips::LD_D: 73228753Smm case Mips::ST_B: 74228753Smm case Mips::ST_H: 75228753Smm case Mips::ST_W: 76228753Smm case Mips::ST_D: 77228753Smm return true; 78228753Smm default: 79228753Smm return false; 80228753Smm } 81228753Smm} 82228753Smm 83228753Smmvoid MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, 84228753Smm unsigned OpNo, int FrameIndex, 85228753Smm uint64_t StackSize, 86228753Smm int64_t SPOffset) const { 87228753Smm MachineInstr &MI = *II; 88228753Smm MachineFunction &MF = *MI.getParent()->getParent(); 89228753Smm MachineFrameInfo *MFI = MF.getFrameInfo(); 90228753Smm MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 91228753Smm 92228753Smm const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 93228753Smm int MinCSFI = 0; 94228753Smm int MaxCSFI = -1; 95228753Smm 96228753Smm if (CSI.size()) { 97228753Smm MinCSFI = CSI[0].getFrameIdx(); 98228753Smm MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); 99228753Smm } 100228753Smm 101228753Smm bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex); 102368708Smm 103228753Smm // The following stack frame objects are always referenced relative to $sp: 104228753Smm // 1. Outgoing arguments. 105228753Smm // 2. Pointer to dynamically allocated stack space. 106228753Smm // 3. Locations for callee-saved registers. 107368708Smm // 4. Locations for eh data registers. 108368708Smm // Everything else is referenced relative to whatever register 109228753Smm // getFrameRegister() returns. 110228753Smm unsigned FrameReg; 111228753Smm 112 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI) 113 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP; 114 else 115 FrameReg = getFrameRegister(MF); 116 117 // Calculate final offset. 118 // - There is no need to change the offset if the frame object is one of the 119 // following: an outgoing argument, pointer to a dynamically allocated 120 // stack space or a $gp restore location, 121 // - If the frame object is any of the following, its offset must be adjusted 122 // by adding the size of the stack: 123 // incoming argument, callee-saved register location or local variable. 124 bool IsKill = false; 125 int64_t Offset; 126 127 Offset = SPOffset + (int64_t)StackSize; 128 Offset += MI.getOperand(OpNo + 1).getImm(); 129 130 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); 131 132 if (!MI.isDebugValue()) { 133 // Make sure Offset fits within the field available. 134 // For MSA instructions, this is a 10-bit signed immediate, otherwise it is 135 // a 16-bit signed immediate. 136 unsigned OffsetBitSize = isMSALoadOrStore(MI.getOpcode()) ? 10 : 16; 137 138 if (OffsetBitSize == 10 && !isInt<10>(Offset) && isInt<16>(Offset)) { 139 // If we have an offset that needs to fit into a signed 10-bit immediate 140 // and doesn't, but does fit into 16-bits then use an ADDiu 141 MachineBasicBlock &MBB = *MI.getParent(); 142 DebugLoc DL = II->getDebugLoc(); 143 unsigned ADDiu = Subtarget.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 144 const TargetRegisterClass *RC = 145 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; 146 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 147 unsigned Reg = RegInfo.createVirtualRegister(RC); 148 const MipsSEInstrInfo &TII = 149 *static_cast<const MipsSEInstrInfo *>( 150 MBB.getParent()->getTarget().getInstrInfo()); 151 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset); 152 153 FrameReg = Reg; 154 Offset = 0; 155 IsKill = true; 156 } else if (!isInt<16>(Offset)) { 157 // Otherwise split the offset into 16-bit pieces and add it in multiple 158 // instructions. 159 MachineBasicBlock &MBB = *MI.getParent(); 160 DebugLoc DL = II->getDebugLoc(); 161 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu; 162 unsigned NewImm = 0; 163 const MipsSEInstrInfo &TII = 164 *static_cast<const MipsSEInstrInfo *>( 165 MBB.getParent()->getTarget().getInstrInfo()); 166 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, 167 OffsetBitSize == 16 ? &NewImm : NULL); 168 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg) 169 .addReg(Reg, RegState::Kill); 170 171 FrameReg = Reg; 172 Offset = SignExtend64<16>(NewImm); 173 IsKill = true; 174 } 175 } 176 177 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); 178 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset); 179} 180