Mips16ISelDAGToDAG.cpp revision 263508 
1//===-- Mips16ISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips16 ----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsDAGToDAGISel specialized for mips16.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-isel"
15#include "Mips16ISelDAGToDAG.h"
16#include "Mips.h"
17#include "MCTargetDesc/MipsBaseInfo.h"
18#include "MipsAnalyzeImmediate.h"
19#include "MipsMachineFunction.h"
20#include "MipsRegisterInfo.h"
21#include "llvm/CodeGen/MachineConstantPool.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/SelectionDAGNodes.h"
27#include "llvm/IR/GlobalValue.h"
28#include "llvm/IR/Instructions.h"
29#include "llvm/IR/Intrinsics.h"
30#include "llvm/IR/Type.h"
31#include "llvm/Support/CFG.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetMachine.h"
36using namespace llvm;
37
38bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
39  if (!Subtarget.inMips16Mode())
40    return false;
41  return MipsDAGToDAGISel::runOnMachineFunction(MF);
42}
43/// Select multiply instructions.
44std::pair<SDNode*, SDNode*>
45Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
46                               bool HasLo, bool HasHi) {
47  SDNode *Lo = 0, *Hi = 0;
48  SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
49                                       N->getOperand(1));
50  SDValue InFlag = SDValue(Mul, 0);
51
52  if (HasLo) {
53    unsigned Opcode = Mips::Mflo16;
54    Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
55    InFlag = SDValue(Lo, 1);
56  }
57  if (HasHi) {
58    unsigned Opcode = Mips::Mfhi16;
59    Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
60  }
61  return std::make_pair(Lo, Hi);
62}
63
64void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
65  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
66
67  if (!MipsFI->globalBaseRegSet())
68    return;
69
70  MachineBasicBlock &MBB = MF.front();
71  MachineBasicBlock::iterator I = MBB.begin();
72  MachineRegisterInfo &RegInfo = MF.getRegInfo();
73  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
74  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
75  unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
76  const TargetRegisterClass *RC =
77    (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
78
79  V0 = RegInfo.createVirtualRegister(RC);
80  V1 = RegInfo.createVirtualRegister(RC);
81  V2 = RegInfo.createVirtualRegister(RC);
82
83  BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0).
84    addReg(V1, RegState::Define).
85    addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI).
86    addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
87
88  BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
89  BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
90    .addReg(V1).addReg(V2);
91}
92
93// Insert instructions to initialize the Mips16 SP Alias register in the
94// first MBB of the function.
95//
96void Mips16DAGToDAGISel::initMips16SPAliasReg(MachineFunction &MF) {
97  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
98
99  if (!MipsFI->mips16SPAliasRegSet())
100    return;
101
102  MachineBasicBlock &MBB = MF.front();
103  MachineBasicBlock::iterator I = MBB.begin();
104  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
105  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
106  unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg();
107
108  BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
109    .addReg(Mips::SP);
110}
111
112void Mips16DAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
113  initGlobalBaseReg(MF);
114  initMips16SPAliasReg(MF);
115}
116
117/// getMips16SPAliasReg - Output the instructions required to put the
118/// SP into a Mips16 accessible aliased register.
119SDValue Mips16DAGToDAGISel::getMips16SPAliasReg() {
120  unsigned Mips16SPAliasReg =
121    MF->getInfo<MipsFunctionInfo>()->getMips16SPAliasReg();
122  return CurDAG->getRegister(Mips16SPAliasReg,
123                             getTargetLowering()->getPointerTy());
124}
125
126void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
127  SDValue AliasFPReg = CurDAG->getRegister(Mips::S0,
128                                           getTargetLowering()->getPointerTy());
129  if (Parent) {
130    switch (Parent->getOpcode()) {
131      case ISD::LOAD: {
132        LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent);
133        switch (SD->getMemoryVT().getSizeInBits()) {
134        case 8:
135        case 16:
136          AliasReg = TM.getFrameLowering()->hasFP(*MF)?
137            AliasFPReg: getMips16SPAliasReg();
138          return;
139        }
140        break;
141      }
142      case ISD::STORE: {
143        StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent);
144        switch (SD->getMemoryVT().getSizeInBits()) {
145        case 8:
146        case 16:
147          AliasReg = TM.getFrameLowering()->hasFP(*MF)?
148            AliasFPReg: getMips16SPAliasReg();
149          return;
150        }
151        break;
152      }
153    }
154  }
155  AliasReg = CurDAG->getRegister(Mips::SP, getTargetLowering()->getPointerTy());
156  return;
157
158}
159
160bool Mips16DAGToDAGISel::selectAddr16(
161  SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
162  SDValue &Alias) {
163  EVT ValTy = Addr.getValueType();
164
165  Alias = CurDAG->getTargetConstant(0, ValTy);
166
167  // if Address is FI, get the TargetFrameIndex.
168  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
169    Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
170    Offset = CurDAG->getTargetConstant(0, ValTy);
171    getMips16SPRefReg(Parent, Alias);
172    return true;
173  }
174  // on PIC code Load GA
175  if (Addr.getOpcode() == MipsISD::Wrapper) {
176    Base   = Addr.getOperand(0);
177    Offset = Addr.getOperand(1);
178    return true;
179  }
180  if (TM.getRelocationModel() != Reloc::PIC_) {
181    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
182        Addr.getOpcode() == ISD::TargetGlobalAddress))
183      return false;
184  }
185  // Addresses of the form FI+const or FI|const
186  if (CurDAG->isBaseWithConstantOffset(Addr)) {
187    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
188    if (isInt<16>(CN->getSExtValue())) {
189
190      // If the first operand is a FI, get the TargetFI Node
191      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
192                                  (Addr.getOperand(0))) {
193        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
194        getMips16SPRefReg(Parent, Alias);
195      }
196      else
197        Base = Addr.getOperand(0);
198
199      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
200      return true;
201    }
202  }
203  // Operand is a result from an ADD.
204  if (Addr.getOpcode() == ISD::ADD) {
205    // When loading from constant pools, load the lower address part in
206    // the instruction itself. Example, instead of:
207    //  lui $2, %hi($CPI1_0)
208    //  addiu $2, $2, %lo($CPI1_0)
209    //  lwc1 $f0, 0($2)
210    // Generate:
211    //  lui $2, %hi($CPI1_0)
212    //  lwc1 $f0, %lo($CPI1_0)($2)
213    if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
214        Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
215      SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
216      if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
217          isa<JumpTableSDNode>(Opnd0)) {
218        Base = Addr.getOperand(0);
219        Offset = Opnd0;
220        return true;
221      }
222    }
223
224    // If an indexed floating point load/store can be emitted, return false.
225    const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
226
227    if (LS &&
228        (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
229        Subtarget.hasFPIdx())
230      return false;
231  }
232  Base   = Addr;
233  Offset = CurDAG->getTargetConstant(0, ValTy);
234  return true;
235}
236
237/// Select instructions not customized! Used for
238/// expanded, promoted and normal instructions
239std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) {
240  unsigned Opcode = Node->getOpcode();
241  SDLoc DL(Node);
242
243  ///
244  // Instruction Selection not handled by the auto-generated
245  // tablegen selection should be handled here.
246  ///
247  EVT NodeTy = Node->getValueType(0);
248  unsigned MultOpc;
249
250  switch(Opcode) {
251  default: break;
252
253  case ISD::SUBE:
254  case ISD::ADDE: {
255    SDValue InFlag = Node->getOperand(2), CmpLHS;
256    unsigned Opc = InFlag.getOpcode(); (void)Opc;
257    assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
258            (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
259           "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
260
261    unsigned MOp;
262    if (Opcode == ISD::ADDE) {
263      CmpLHS = InFlag.getValue(0);
264      MOp = Mips::AdduRxRyRz16;
265    } else {
266      CmpLHS = InFlag.getOperand(0);
267      MOp = Mips::SubuRxRyRz16;
268    }
269
270    SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
271
272    SDValue LHS = Node->getOperand(0);
273    SDValue RHS = Node->getOperand(1);
274
275    EVT VT = LHS.getValueType();
276
277    unsigned Sltu_op = Mips::SltuRxRyRz16;
278    SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops);
279    unsigned Addu_op = Mips::AdduRxRyRz16;
280    SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
281                                              SDValue(Carry,0), RHS);
282
283    SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
284                                          SDValue(AddCarry,0));
285    return std::make_pair(true, Result);
286  }
287
288  /// Mul with two results
289  case ISD::SMUL_LOHI:
290  case ISD::UMUL_LOHI: {
291    MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
292    std::pair<SDNode*, SDNode*> LoHi = selectMULT(Node, MultOpc, DL, NodeTy,
293                                                  true, true);
294    if (!SDValue(Node, 0).use_empty())
295      ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
296
297    if (!SDValue(Node, 1).use_empty())
298      ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
299
300    return std::make_pair(true, (SDNode*)NULL);
301  }
302
303  case ISD::MULHS:
304  case ISD::MULHU: {
305    MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
306    SDNode *Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second;
307    return std::make_pair(true, Result);
308  }
309  }
310
311  return std::make_pair(false, (SDNode*)NULL);
312}
313
314FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
315  return new Mips16DAGToDAGISel(TM);
316}
317