HexagonInstrInfo.h revision 263508 
1//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef HexagonINSTRUCTIONINFO_H
15#define HexagonINSTRUCTIONINFO_H
16
17#include "HexagonRegisterInfo.h"
18#include "MCTargetDesc/HexagonBaseInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetFrameLowering.h"
21#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
22
23#define GET_INSTRINFO_HEADER
24#include "HexagonGenInstrInfo.inc"
25
26namespace llvm {
27
28class HexagonInstrInfo : public HexagonGenInstrInfo {
29  virtual void anchor();
30  const HexagonRegisterInfo RI;
31  const HexagonSubtarget &Subtarget;
32  typedef unsigned Opcode_t;
33
34public:
35  explicit HexagonInstrInfo(HexagonSubtarget &ST);
36
37  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
38  /// such, whenever a client has an instance of instruction info, it should
39  /// always be able to get register info as well (through this method).
40  ///
41  virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
42
43  /// isLoadFromStackSlot - If the specified machine instruction is a direct
44  /// load from a stack slot, return the virtual or physical register number of
45  /// the destination along with the FrameIndex of the loaded stack slot.  If
46  /// not, return 0.  This predicate must return 0 if the instruction has
47  /// any side effects other than loading from the stack slot.
48  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
49                                       int &FrameIndex) const;
50
51  /// isStoreToStackSlot - If the specified machine instruction is a direct
52  /// store to a stack slot, return the virtual or physical register number of
53  /// the source reg along with the FrameIndex of the loaded stack slot.  If
54  /// not, return 0.  This predicate must return 0 if the instruction has
55  /// any side effects other than storing to the stack slot.
56  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
57                                      int &FrameIndex) const;
58
59
60  virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
61                                 MachineBasicBlock *&FBB,
62                                 SmallVectorImpl<MachineOperand> &Cond,
63                                 bool AllowModify) const;
64
65  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
66
67  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
68                                MachineBasicBlock *FBB,
69                                const SmallVectorImpl<MachineOperand> &Cond,
70                                DebugLoc DL) const;
71
72  virtual bool analyzeCompare(const MachineInstr *MI,
73                              unsigned &SrcReg, unsigned &SrcReg2,
74                              int &Mask, int &Value) const;
75
76  virtual void copyPhysReg(MachineBasicBlock &MBB,
77                           MachineBasicBlock::iterator I, DebugLoc DL,
78                           unsigned DestReg, unsigned SrcReg,
79                           bool KillSrc) const;
80
81  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
82                                   MachineBasicBlock::iterator MBBI,
83                                   unsigned SrcReg, bool isKill, int FrameIndex,
84                                   const TargetRegisterClass *RC,
85                                   const TargetRegisterInfo *TRI) const;
86
87  virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
88                              SmallVectorImpl<MachineOperand> &Addr,
89                              const TargetRegisterClass *RC,
90                              SmallVectorImpl<MachineInstr*> &NewMIs) const;
91
92  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
93                                    MachineBasicBlock::iterator MBBI,
94                                    unsigned DestReg, int FrameIndex,
95                                    const TargetRegisterClass *RC,
96                                    const TargetRegisterInfo *TRI) const;
97
98  virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
99                               SmallVectorImpl<MachineOperand> &Addr,
100                               const TargetRegisterClass *RC,
101                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
102
103  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
104                                              MachineInstr* MI,
105                                           const SmallVectorImpl<unsigned> &Ops,
106                                              int FrameIndex) const;
107
108  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
109                                              MachineInstr* MI,
110                                           const SmallVectorImpl<unsigned> &Ops,
111                                              MachineInstr* LoadMI) const {
112    return 0;
113  }
114
115  unsigned createVR(MachineFunction* MF, MVT VT) const;
116
117  virtual bool isBranch(const MachineInstr *MI) const;
118  virtual bool isPredicable(MachineInstr *MI) const;
119  virtual bool
120  PredicateInstruction(MachineInstr *MI,
121                       const SmallVectorImpl<MachineOperand> &Cond) const;
122
123  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
124                                   unsigned ExtraPredCycles,
125                                   const BranchProbability &Probability) const;
126
127  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
128                                   unsigned NumTCycles, unsigned ExtraTCycles,
129                                   MachineBasicBlock &FMBB,
130                                   unsigned NumFCycles, unsigned ExtraFCycles,
131                                   const BranchProbability &Probability) const;
132
133  virtual bool isPredicated(const MachineInstr *MI) const;
134  virtual bool isPredicated(unsigned Opcode) const;
135  virtual bool isPredicatedTrue(const MachineInstr *MI) const;
136  virtual bool isPredicatedTrue(unsigned Opcode) const;
137  virtual bool isPredicatedNew(const MachineInstr *MI) const;
138  virtual bool isPredicatedNew(unsigned Opcode) const;
139  virtual bool DefinesPredicate(MachineInstr *MI,
140                                std::vector<MachineOperand> &Pred) const;
141  virtual bool
142  SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
143                    const SmallVectorImpl<MachineOperand> &Pred2) const;
144
145  virtual bool
146  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
147
148  virtual bool
149  isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
150                            const BranchProbability &Probability) const;
151
152  virtual DFAPacketizer*
153  CreateTargetScheduleState(const TargetMachine *TM,
154                            const ScheduleDAG *DAG) const;
155
156  virtual bool isSchedulingBoundary(const MachineInstr *MI,
157                                    const MachineBasicBlock *MBB,
158                                    const MachineFunction &MF) const;
159  bool isValidOffset(const int Opcode, const int Offset) const;
160  bool isValidAutoIncImm(const EVT VT, const int Offset) const;
161  bool isMemOp(const MachineInstr *MI) const;
162  bool isSpillPredRegOp(const MachineInstr *MI) const;
163  bool isU6_3Immediate(const int value) const;
164  bool isU6_2Immediate(const int value) const;
165  bool isU6_1Immediate(const int value) const;
166  bool isU6_0Immediate(const int value) const;
167  bool isS4_3Immediate(const int value) const;
168  bool isS4_2Immediate(const int value) const;
169  bool isS4_1Immediate(const int value) const;
170  bool isS4_0Immediate(const int value) const;
171  bool isS12_Immediate(const int value) const;
172  bool isU6_Immediate(const int value) const;
173  bool isS8_Immediate(const int value) const;
174  bool isS6_Immediate(const int value) const;
175
176  bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
177  bool isConditionalTransfer(const MachineInstr* MI) const;
178  bool isConditionalALU32 (const MachineInstr* MI) const;
179  bool isConditionalLoad (const MachineInstr* MI) const;
180  bool isConditionalStore(const MachineInstr* MI) const;
181  bool isNewValueInst(const MachineInstr* MI) const;
182  bool isNewValue(const MachineInstr* MI) const;
183  bool isDotNewInst(const MachineInstr* MI) const;
184  int GetDotOldOp(const int opc) const;
185  int GetDotNewOp(const MachineInstr* MI) const;
186  int GetDotNewPredOp(MachineInstr *MI,
187                      const MachineBranchProbabilityInfo
188                      *MBPI) const;
189  bool mayBeNewStore(const MachineInstr* MI) const;
190  bool isDeallocRet(const MachineInstr *MI) const;
191  unsigned getInvertedPredicatedOpcode(const int Opc) const;
192  bool isExtendable(const MachineInstr* MI) const;
193  bool isExtended(const MachineInstr* MI) const;
194  bool isPostIncrement(const MachineInstr* MI) const;
195  bool isNewValueStore(const MachineInstr* MI) const;
196  bool isNewValueStore(unsigned Opcode) const;
197  bool isNewValueJump(const MachineInstr* MI) const;
198  bool isNewValueJumpCandidate(const MachineInstr *MI) const;
199
200
201  void immediateExtend(MachineInstr *MI) const;
202  bool isConstExtended(MachineInstr *MI) const;
203  int getDotNewPredJumpOp(MachineInstr *MI,
204                      const MachineBranchProbabilityInfo *MBPI) const;
205  unsigned getAddrMode(const MachineInstr* MI) const;
206  bool isOperandExtended(const MachineInstr *MI,
207                         unsigned short OperandNum) const;
208  unsigned short getCExtOpNum(const MachineInstr *MI) const;
209  int getMinValue(const MachineInstr *MI) const;
210  int getMaxValue(const MachineInstr *MI) const;
211  bool NonExtEquivalentExists (const MachineInstr *MI) const;
212  short getNonExtOpcode(const MachineInstr *MI) const;
213  bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
214  bool PredOpcodeHasNot(Opcode_t Opcode) const;
215
216private:
217  int getMatchingCondBranchOpcode(int Opc, bool sense) const;
218
219};
220
221}
222
223#endif
224