HexagonISelLowering.cpp revision 263508
1//===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Hexagon uses to lower LLVM code 11// into a selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "HexagonISelLowering.h" 16#include "HexagonMachineFunctionInfo.h" 17#include "HexagonSubtarget.h" 18#include "HexagonTargetMachine.h" 19#include "HexagonTargetObjectFile.h" 20#include "llvm/CodeGen/CallingConvLower.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/MachineJumpTableInfo.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/SelectionDAGISel.h" 27#include "llvm/CodeGen/ValueTypes.h" 28#include "llvm/IR/CallingConv.h" 29#include "llvm/IR/DerivedTypes.h" 30#include "llvm/IR/Function.h" 31#include "llvm/IR/GlobalAlias.h" 32#include "llvm/IR/GlobalVariable.h" 33#include "llvm/IR/InlineAsm.h" 34#include "llvm/IR/Intrinsics.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/Debug.h" 37#include "llvm/Support/ErrorHandling.h" 38#include "llvm/Support/raw_ostream.h" 39 40using namespace llvm; 41 42static cl::opt<bool> 43EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, 44 cl::desc("Control jump table emission on Hexagon target")); 45 46namespace { 47class HexagonCCState : public CCState { 48 int NumNamedVarArgParams; 49 50public: 51 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, 52 const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs, 53 LLVMContext &C, int NumNamedVarArgParams) 54 : CCState(CC, isVarArg, MF, TM, locs, C), 55 NumNamedVarArgParams(NumNamedVarArgParams) {} 56 57 int getNumNamedVarArgParams() const { return NumNamedVarArgParams; } 58}; 59} 60 61// Implement calling convention for Hexagon. 62static bool 63CC_Hexagon(unsigned ValNo, MVT ValVT, 64 MVT LocVT, CCValAssign::LocInfo LocInfo, 65 ISD::ArgFlagsTy ArgFlags, CCState &State); 66 67static bool 68CC_Hexagon32(unsigned ValNo, MVT ValVT, 69 MVT LocVT, CCValAssign::LocInfo LocInfo, 70 ISD::ArgFlagsTy ArgFlags, CCState &State); 71 72static bool 73CC_Hexagon64(unsigned ValNo, MVT ValVT, 74 MVT LocVT, CCValAssign::LocInfo LocInfo, 75 ISD::ArgFlagsTy ArgFlags, CCState &State); 76 77static bool 78RetCC_Hexagon(unsigned ValNo, MVT ValVT, 79 MVT LocVT, CCValAssign::LocInfo LocInfo, 80 ISD::ArgFlagsTy ArgFlags, CCState &State); 81 82static bool 83RetCC_Hexagon32(unsigned ValNo, MVT ValVT, 84 MVT LocVT, CCValAssign::LocInfo LocInfo, 85 ISD::ArgFlagsTy ArgFlags, CCState &State); 86 87static bool 88RetCC_Hexagon64(unsigned ValNo, MVT ValVT, 89 MVT LocVT, CCValAssign::LocInfo LocInfo, 90 ISD::ArgFlagsTy ArgFlags, CCState &State); 91 92static bool 93CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT, 94 MVT LocVT, CCValAssign::LocInfo LocInfo, 95 ISD::ArgFlagsTy ArgFlags, CCState &State) { 96 HexagonCCState &HState = static_cast<HexagonCCState &>(State); 97 98 // NumNamedVarArgParams can not be zero for a VarArg function. 99 assert((HState.getNumNamedVarArgParams() > 0) && 100 "NumNamedVarArgParams is not bigger than zero."); 101 102 if ((int)ValNo < HState.getNumNamedVarArgParams()) { 103 // Deal with named arguments. 104 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State); 105 } 106 107 // Deal with un-named arguments. 108 unsigned ofst; 109 if (ArgFlags.isByVal()) { 110 // If pass-by-value, the size allocated on stack is decided 111 // by ArgFlags.getByValSize(), not by the size of LocVT. 112 assert ((ArgFlags.getByValSize() > 8) && 113 "ByValSize must be bigger than 8 bytes"); 114 ofst = State.AllocateStack(ArgFlags.getByValSize(), 4); 115 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 116 return false; 117 } 118 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { 119 LocVT = MVT::i32; 120 ValVT = MVT::i32; 121 if (ArgFlags.isSExt()) 122 LocInfo = CCValAssign::SExt; 123 else if (ArgFlags.isZExt()) 124 LocInfo = CCValAssign::ZExt; 125 else 126 LocInfo = CCValAssign::AExt; 127 } 128 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 129 ofst = State.AllocateStack(4, 4); 130 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 131 return false; 132 } 133 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 134 ofst = State.AllocateStack(8, 8); 135 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 136 return false; 137 } 138 llvm_unreachable(0); 139} 140 141 142static bool 143CC_Hexagon (unsigned ValNo, MVT ValVT, 144 MVT LocVT, CCValAssign::LocInfo LocInfo, 145 ISD::ArgFlagsTy ArgFlags, CCState &State) { 146 147 if (ArgFlags.isByVal()) { 148 // Passed on stack. 149 assert ((ArgFlags.getByValSize() > 8) && 150 "ByValSize must be bigger than 8 bytes"); 151 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4); 152 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 153 return false; 154 } 155 156 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { 157 LocVT = MVT::i32; 158 ValVT = MVT::i32; 159 if (ArgFlags.isSExt()) 160 LocInfo = CCValAssign::SExt; 161 else if (ArgFlags.isZExt()) 162 LocInfo = CCValAssign::ZExt; 163 else 164 LocInfo = CCValAssign::AExt; 165 } 166 167 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 168 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 169 return false; 170 } 171 172 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 173 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 174 return false; 175 } 176 177 return true; // CC didn't match. 178} 179 180 181static bool CC_Hexagon32(unsigned ValNo, MVT ValVT, 182 MVT LocVT, CCValAssign::LocInfo LocInfo, 183 ISD::ArgFlagsTy ArgFlags, CCState &State) { 184 185 static const uint16_t RegList[] = { 186 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 187 Hexagon::R5 188 }; 189 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 190 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 191 return false; 192 } 193 194 unsigned Offset = State.AllocateStack(4, 4); 195 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 196 return false; 197} 198 199static bool CC_Hexagon64(unsigned ValNo, MVT ValVT, 200 MVT LocVT, CCValAssign::LocInfo LocInfo, 201 ISD::ArgFlagsTy ArgFlags, CCState &State) { 202 203 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { 204 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 205 return false; 206 } 207 208 static const uint16_t RegList1[] = { 209 Hexagon::D1, Hexagon::D2 210 }; 211 static const uint16_t RegList2[] = { 212 Hexagon::R1, Hexagon::R3 213 }; 214 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) { 215 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 216 return false; 217 } 218 219 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2); 220 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 221 return false; 222} 223 224static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT, 225 MVT LocVT, CCValAssign::LocInfo LocInfo, 226 ISD::ArgFlagsTy ArgFlags, CCState &State) { 227 228 229 if (LocVT == MVT::i1 || 230 LocVT == MVT::i8 || 231 LocVT == MVT::i16) { 232 LocVT = MVT::i32; 233 ValVT = MVT::i32; 234 if (ArgFlags.isSExt()) 235 LocInfo = CCValAssign::SExt; 236 else if (ArgFlags.isZExt()) 237 LocInfo = CCValAssign::ZExt; 238 else 239 LocInfo = CCValAssign::AExt; 240 } 241 242 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 243 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 244 return false; 245 } 246 247 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 248 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 249 return false; 250 } 251 252 return true; // CC didn't match. 253} 254 255static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT, 256 MVT LocVT, CCValAssign::LocInfo LocInfo, 257 ISD::ArgFlagsTy ArgFlags, CCState &State) { 258 259 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 260 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) { 261 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 262 return false; 263 } 264 } 265 266 unsigned Offset = State.AllocateStack(4, 4); 267 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 268 return false; 269} 270 271static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT, 272 MVT LocVT, CCValAssign::LocInfo LocInfo, 273 ISD::ArgFlagsTy ArgFlags, CCState &State) { 274 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 275 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { 276 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 277 return false; 278 } 279 } 280 281 unsigned Offset = State.AllocateStack(8, 8); 282 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 283 return false; 284} 285 286SDValue 287HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) 288const { 289 return SDValue(); 290} 291 292/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 293/// by "Src" to address "Dst" of size "Size". Alignment information is 294/// specified by the specific parameter attribute. The copy will be passed as 295/// a byval function parameter. Sometimes what we are copying is the end of a 296/// larger object, the part that does not fit in registers. 297static SDValue 298CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 299 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 300 SDLoc dl) { 301 302 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 303 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 304 /*isVolatile=*/false, /*AlwaysInline=*/false, 305 MachinePointerInfo(), MachinePointerInfo()); 306} 307 308 309// LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is 310// passed by value, the function prototype is modified to return void and 311// the value is stored in memory pointed by a pointer passed by caller. 312SDValue 313HexagonTargetLowering::LowerReturn(SDValue Chain, 314 CallingConv::ID CallConv, bool isVarArg, 315 const SmallVectorImpl<ISD::OutputArg> &Outs, 316 const SmallVectorImpl<SDValue> &OutVals, 317 SDLoc dl, SelectionDAG &DAG) const { 318 319 // CCValAssign - represent the assignment of the return value to locations. 320 SmallVector<CCValAssign, 16> RVLocs; 321 322 // CCState - Info about the registers and stack slot. 323 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 324 getTargetMachine(), RVLocs, *DAG.getContext()); 325 326 // Analyze return values of ISD::RET 327 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon); 328 329 SDValue Flag; 330 SmallVector<SDValue, 4> RetOps(1, Chain); 331 332 // Copy the result values into the output registers. 333 for (unsigned i = 0; i != RVLocs.size(); ++i) { 334 CCValAssign &VA = RVLocs[i]; 335 336 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 337 338 // Guarantee that all emitted copies are stuck together with flags. 339 Flag = Chain.getValue(1); 340 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 341 } 342 343 RetOps[0] = Chain; // Update chain. 344 345 // Add the flag if we have it. 346 if (Flag.getNode()) 347 RetOps.push_back(Flag); 348 349 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, 350 &RetOps[0], RetOps.size()); 351} 352 353 354 355 356/// LowerCallResult - Lower the result values of an ISD::CALL into the 357/// appropriate copies out of appropriate physical registers. This assumes that 358/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 359/// being lowered. Returns a SDNode with the same number of values as the 360/// ISD::CALL. 361SDValue 362HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 363 CallingConv::ID CallConv, bool isVarArg, 364 const 365 SmallVectorImpl<ISD::InputArg> &Ins, 366 SDLoc dl, SelectionDAG &DAG, 367 SmallVectorImpl<SDValue> &InVals, 368 const SmallVectorImpl<SDValue> &OutVals, 369 SDValue Callee) const { 370 371 // Assign locations to each value returned by this call. 372 SmallVector<CCValAssign, 16> RVLocs; 373 374 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 375 getTargetMachine(), RVLocs, *DAG.getContext()); 376 377 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon); 378 379 // Copy all of the result registers out of their specified physreg. 380 for (unsigned i = 0; i != RVLocs.size(); ++i) { 381 Chain = DAG.getCopyFromReg(Chain, dl, 382 RVLocs[i].getLocReg(), 383 RVLocs[i].getValVT(), InFlag).getValue(1); 384 InFlag = Chain.getValue(2); 385 InVals.push_back(Chain.getValue(0)); 386 } 387 388 return Chain; 389} 390 391/// LowerCall - Functions arguments are copied from virtual regs to 392/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 393SDValue 394HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 395 SmallVectorImpl<SDValue> &InVals) const { 396 SelectionDAG &DAG = CLI.DAG; 397 SDLoc &dl = CLI.DL; 398 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 399 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 400 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 401 SDValue Chain = CLI.Chain; 402 SDValue Callee = CLI.Callee; 403 bool &isTailCall = CLI.IsTailCall; 404 CallingConv::ID CallConv = CLI.CallConv; 405 bool isVarArg = CLI.IsVarArg; 406 407 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 408 409 // Check for varargs. 410 int NumNamedVarArgParams = -1; 411 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee)) 412 { 413 const Function* CalleeFn = NULL; 414 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32); 415 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal()))) 416 { 417 // If a function has zero args and is a vararg function, that's 418 // disallowed so it must be an undeclared function. Do not assume 419 // varargs if the callee is undefined. 420 if (CalleeFn->isVarArg() && 421 CalleeFn->getFunctionType()->getNumParams() != 0) { 422 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams(); 423 } 424 } 425 } 426 427 // Analyze operands of the call, assigning locations to each operand. 428 SmallVector<CCValAssign, 16> ArgLocs; 429 HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 430 getTargetMachine(), ArgLocs, *DAG.getContext(), 431 NumNamedVarArgParams); 432 433 if (NumNamedVarArgParams > 0) 434 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg); 435 else 436 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon); 437 438 439 if(isTailCall) { 440 bool StructAttrFlag = 441 DAG.getMachineFunction().getFunction()->hasStructRetAttr(); 442 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 443 isVarArg, IsStructRet, 444 StructAttrFlag, 445 Outs, OutVals, Ins, DAG); 446 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){ 447 CCValAssign &VA = ArgLocs[i]; 448 if (VA.isMemLoc()) { 449 isTailCall = false; 450 break; 451 } 452 } 453 if (isTailCall) { 454 DEBUG(dbgs () << "Eligible for Tail Call\n"); 455 } else { 456 DEBUG(dbgs () << 457 "Argument must be passed on stack. Not eligible for Tail Call\n"); 458 } 459 } 460 // Get a count of how many bytes are to be pushed on the stack. 461 unsigned NumBytes = CCInfo.getNextStackOffset(); 462 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 463 SmallVector<SDValue, 8> MemOpChains; 464 465 SDValue StackPtr = 466 DAG.getCopyFromReg(Chain, dl, TM.getRegisterInfo()->getStackRegister(), 467 getPointerTy()); 468 469 // Walk the register/memloc assignments, inserting copies/loads. 470 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 471 CCValAssign &VA = ArgLocs[i]; 472 SDValue Arg = OutVals[i]; 473 ISD::ArgFlagsTy Flags = Outs[i].Flags; 474 475 // Promote the value if needed. 476 switch (VA.getLocInfo()) { 477 default: 478 // Loc info must be one of Full, SExt, ZExt, or AExt. 479 llvm_unreachable("Unknown loc info!"); 480 case CCValAssign::Full: 481 break; 482 case CCValAssign::SExt: 483 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 484 break; 485 case CCValAssign::ZExt: 486 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 487 break; 488 case CCValAssign::AExt: 489 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 490 break; 491 } 492 493 if (VA.isMemLoc()) { 494 unsigned LocMemOffset = VA.getLocMemOffset(); 495 SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType()); 496 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 497 498 if (Flags.isByVal()) { 499 // The argument is a struct passed by value. According to LLVM, "Arg" 500 // is is pointer. 501 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain, 502 Flags, DAG, dl)); 503 } else { 504 // The argument is not passed by value. "Arg" is a buildin type. It is 505 // not a pointer. 506 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 507 MachinePointerInfo(),false, false, 508 0)); 509 } 510 continue; 511 } 512 513 // Arguments that can be passed on register must be kept at RegsToPass 514 // vector. 515 if (VA.isRegLoc()) { 516 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 517 } 518 } 519 520 // Transform all store nodes into one single node because all store 521 // nodes are independent of each other. 522 if (!MemOpChains.empty()) { 523 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], 524 MemOpChains.size()); 525 } 526 527 if (!isTailCall) 528 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, 529 getPointerTy(), true), 530 dl); 531 532 // Build a sequence of copy-to-reg nodes chained together with token 533 // chain and flag operands which copy the outgoing args into registers. 534 // The InFlag in necessary since all emitted instructions must be 535 // stuck together. 536 SDValue InFlag; 537 if (!isTailCall) { 538 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 539 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 540 RegsToPass[i].second, InFlag); 541 InFlag = Chain.getValue(1); 542 } 543 } 544 545 // For tail calls lower the arguments to the 'real' stack slot. 546 if (isTailCall) { 547 // Force all the incoming stack arguments to be loaded from the stack 548 // before any new outgoing arguments are stored to the stack, because the 549 // outgoing stack slots may alias the incoming argument stack slots, and 550 // the alias isn't otherwise explicit. This is slightly more conservative 551 // than necessary, because it means that each store effectively depends 552 // on every argument instead of just those arguments it would clobber. 553 // 554 // Do not flag preceding copytoreg stuff together with the following stuff. 555 InFlag = SDValue(); 556 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 557 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 558 RegsToPass[i].second, InFlag); 559 InFlag = Chain.getValue(1); 560 } 561 InFlag =SDValue(); 562 } 563 564 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 565 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 566 // node so that legalize doesn't hack it. 567 if (flag_aligned_memcpy) { 568 const char *MemcpyName = 569 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes"; 570 Callee = 571 DAG.getTargetExternalSymbol(MemcpyName, getPointerTy()); 572 flag_aligned_memcpy = false; 573 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 574 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy()); 575 } else if (ExternalSymbolSDNode *S = 576 dyn_cast<ExternalSymbolSDNode>(Callee)) { 577 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 578 } 579 580 // Returns a chain & a flag for retval copy to use. 581 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 582 SmallVector<SDValue, 8> Ops; 583 Ops.push_back(Chain); 584 Ops.push_back(Callee); 585 586 // Add argument registers to the end of the list so that they are 587 // known live into the call. 588 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 589 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 590 RegsToPass[i].second.getValueType())); 591 } 592 593 if (InFlag.getNode()) { 594 Ops.push_back(InFlag); 595 } 596 597 if (isTailCall) 598 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 599 600 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 601 InFlag = Chain.getValue(1); 602 603 // Create the CALLSEQ_END node. 604 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 605 DAG.getIntPtrConstant(0, true), InFlag, dl); 606 InFlag = Chain.getValue(1); 607 608 // Handle result values, copying them out of physregs into vregs that we 609 // return. 610 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG, 611 InVals, OutVals, Callee); 612} 613 614static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, 615 bool isSEXTLoad, SDValue &Base, 616 SDValue &Offset, bool &isInc, 617 SelectionDAG &DAG) { 618 if (Ptr->getOpcode() != ISD::ADD) 619 return false; 620 621 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 622 isInc = (Ptr->getOpcode() == ISD::ADD); 623 Base = Ptr->getOperand(0); 624 Offset = Ptr->getOperand(1); 625 // Ensure that Offset is a constant. 626 return (isa<ConstantSDNode>(Offset)); 627 } 628 629 return false; 630} 631 632// TODO: Put this function along with the other isS* functions in 633// HexagonISelDAGToDAG.cpp into a common file. Or better still, use the 634// functions defined in HexagonOperands.td. 635static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) { 636 ConstantSDNode *N = cast<ConstantSDNode>(S); 637 638 // immS4 predicate - True if the immediate fits in a 4-bit sign extended. 639 // field. 640 int64_t v = (int64_t)N->getSExtValue(); 641 int64_t m = 0; 642 if (ShiftAmount > 0) { 643 m = v % ShiftAmount; 644 v = v >> ShiftAmount; 645 } 646 return (v <= 7) && (v >= -8) && (m == 0); 647} 648 649/// getPostIndexedAddressParts - returns true by value, base pointer and 650/// offset pointer and addressing mode by reference if this node can be 651/// combined with a load / store to form a post-indexed load / store. 652bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 653 SDValue &Base, 654 SDValue &Offset, 655 ISD::MemIndexedMode &AM, 656 SelectionDAG &DAG) const 657{ 658 EVT VT; 659 SDValue Ptr; 660 bool isSEXTLoad = false; 661 662 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 663 VT = LD->getMemoryVT(); 664 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 665 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 666 VT = ST->getMemoryVT(); 667 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) { 668 return false; 669 } 670 } else { 671 return false; 672 } 673 674 bool isInc = false; 675 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 676 isInc, DAG); 677 // ShiftAmount = number of left-shifted bits in the Hexagon instruction. 678 int ShiftAmount = VT.getSizeInBits() / 16; 679 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) { 680 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 681 return true; 682 } 683 684 return false; 685} 686 687SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op, 688 SelectionDAG &DAG) const { 689 SDNode *Node = Op.getNode(); 690 MachineFunction &MF = DAG.getMachineFunction(); 691 HexagonMachineFunctionInfo *FuncInfo = 692 MF.getInfo<HexagonMachineFunctionInfo>(); 693 switch (Node->getOpcode()) { 694 case ISD::INLINEASM: { 695 unsigned NumOps = Node->getNumOperands(); 696 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 697 --NumOps; // Ignore the flag operand. 698 699 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 700 if (FuncInfo->hasClobberLR()) 701 break; 702 unsigned Flags = 703 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 704 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 705 ++i; // Skip the ID value. 706 707 switch (InlineAsm::getKind(Flags)) { 708 default: llvm_unreachable("Bad flags!"); 709 case InlineAsm::Kind_RegDef: 710 case InlineAsm::Kind_RegUse: 711 case InlineAsm::Kind_Imm: 712 case InlineAsm::Kind_Clobber: 713 case InlineAsm::Kind_Mem: { 714 for (; NumVals; --NumVals, ++i) {} 715 break; 716 } 717 case InlineAsm::Kind_RegDefEarlyClobber: { 718 for (; NumVals; --NumVals, ++i) { 719 unsigned Reg = 720 cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 721 722 // Check it to be lr 723 if (Reg == TM.getRegisterInfo()->getRARegister()) { 724 FuncInfo->setHasClobberLR(true); 725 break; 726 } 727 } 728 break; 729 } 730 } 731 } 732 } 733 } // Node->getOpcode 734 return Op; 735} 736 737 738// 739// Taken from the XCore backend. 740// 741SDValue HexagonTargetLowering:: 742LowerBR_JT(SDValue Op, SelectionDAG &DAG) const 743{ 744 SDValue Chain = Op.getOperand(0); 745 SDValue Table = Op.getOperand(1); 746 SDValue Index = Op.getOperand(2); 747 SDLoc dl(Op); 748 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 749 unsigned JTI = JT->getIndex(); 750 MachineFunction &MF = DAG.getMachineFunction(); 751 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); 752 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32); 753 754 // Mark all jump table targets as address taken. 755 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables(); 756 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs; 757 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) { 758 MachineBasicBlock *MBB = JTBBs[i]; 759 MBB->setHasAddressTaken(); 760 // This line is needed to set the hasAddressTaken flag on the BasicBlock 761 // object. 762 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock())); 763 } 764 765 SDValue JumpTableBase = DAG.getNode(HexagonISD::WrapperJT, dl, 766 getPointerTy(), TargetJT); 767 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, 768 DAG.getConstant(2, MVT::i32)); 769 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase, 770 ShiftIndex); 771 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress, 772 MachinePointerInfo(), false, false, false, 773 0); 774 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget); 775} 776 777 778SDValue 779HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 780 SelectionDAG &DAG) const { 781 SDValue Chain = Op.getOperand(0); 782 SDValue Size = Op.getOperand(1); 783 SDLoc dl(Op); 784 785 unsigned SPReg = getStackPointerRegisterToSaveRestore(); 786 787 // Get a reference to the stack pointer. 788 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 789 790 // Subtract the dynamic size from the actual stack size to 791 // obtain the new stack size. 792 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 793 794 // 795 // For Hexagon, the outgoing memory arguments area should be on top of the 796 // alloca area on the stack i.e., the outgoing memory arguments should be 797 // at a lower address than the alloca area. Move the alloca area down the 798 // stack by adding back the space reserved for outgoing arguments to SP 799 // here. 800 // 801 // We do not know what the size of the outgoing args is at this point. 802 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the 803 // stack pointer. We patch this instruction with the correct, known 804 // offset in emitPrologue(). 805 // 806 // Use a placeholder immediate (zero) for now. This will be patched up 807 // by emitPrologue(). 808 SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl, 809 MVT::i32, 810 Sub, 811 DAG.getConstant(0, MVT::i32)); 812 813 // The Sub result contains the new stack start address, so it 814 // must be placed in the stack pointer register. 815 SDValue CopyChain = DAG.getCopyToReg(Chain, dl, 816 TM.getRegisterInfo()->getStackRegister(), 817 Sub); 818 819 SDValue Ops[2] = { ArgAdjust, CopyChain }; 820 return DAG.getMergeValues(Ops, 2, dl); 821} 822 823SDValue 824HexagonTargetLowering::LowerFormalArguments(SDValue Chain, 825 CallingConv::ID CallConv, 826 bool isVarArg, 827 const 828 SmallVectorImpl<ISD::InputArg> &Ins, 829 SDLoc dl, SelectionDAG &DAG, 830 SmallVectorImpl<SDValue> &InVals) 831const { 832 833 MachineFunction &MF = DAG.getMachineFunction(); 834 MachineFrameInfo *MFI = MF.getFrameInfo(); 835 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 836 HexagonMachineFunctionInfo *FuncInfo = 837 MF.getInfo<HexagonMachineFunctionInfo>(); 838 839 840 // Assign locations to all of the incoming arguments. 841 SmallVector<CCValAssign, 16> ArgLocs; 842 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 843 getTargetMachine(), ArgLocs, *DAG.getContext()); 844 845 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon); 846 847 // For LLVM, in the case when returning a struct by value (>8byte), 848 // the first argument is a pointer that points to the location on caller's 849 // stack where the return value will be stored. For Hexagon, the location on 850 // caller's stack is passed only when the struct size is smaller than (and 851 // equal to) 8 bytes. If not, no address will be passed into callee and 852 // callee return the result direclty through R0/R1. 853 854 SmallVector<SDValue, 4> MemOps; 855 856 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 857 CCValAssign &VA = ArgLocs[i]; 858 ISD::ArgFlagsTy Flags = Ins[i].Flags; 859 unsigned ObjSize; 860 unsigned StackLocation; 861 int FI; 862 863 if ( (VA.isRegLoc() && !Flags.isByVal()) 864 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) { 865 // Arguments passed in registers 866 // 1. int, long long, ptr args that get allocated in register. 867 // 2. Large struct that gets an register to put its address in. 868 EVT RegVT = VA.getLocVT(); 869 if (RegVT == MVT::i8 || RegVT == MVT::i16 || 870 RegVT == MVT::i32 || RegVT == MVT::f32) { 871 unsigned VReg = 872 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass); 873 RegInfo.addLiveIn(VA.getLocReg(), VReg); 874 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 875 } else if (RegVT == MVT::i64) { 876 unsigned VReg = 877 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass); 878 RegInfo.addLiveIn(VA.getLocReg(), VReg); 879 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 880 } else { 881 assert (0); 882 } 883 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) { 884 assert (0 && "ByValSize must be bigger than 8 bytes"); 885 } else { 886 // Sanity check. 887 assert(VA.isMemLoc()); 888 889 if (Flags.isByVal()) { 890 // If it's a byval parameter, then we need to compute the 891 // "real" size, not the size of the pointer. 892 ObjSize = Flags.getByValSize(); 893 } else { 894 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3; 895 } 896 897 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset(); 898 // Create the frame index object for this incoming parameter... 899 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true); 900 901 // Create the SelectionDAG nodes cordl, responding to a load 902 // from this parameter. 903 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 904 905 if (Flags.isByVal()) { 906 // If it's a pass-by-value aggregate, then do not dereference the stack 907 // location. Instead, we should generate a reference to the stack 908 // location. 909 InVals.push_back(FIN); 910 } else { 911 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 912 MachinePointerInfo(), false, false, 913 false, 0)); 914 } 915 } 916 } 917 918 if (!MemOps.empty()) 919 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], 920 MemOps.size()); 921 922 if (isVarArg) { 923 // This will point to the next argument passed via stack. 924 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize, 925 HEXAGON_LRFP_SIZE + 926 CCInfo.getNextStackOffset(), 927 true); 928 FuncInfo->setVarArgsFrameIndex(FrameIndex); 929 } 930 931 return Chain; 932} 933 934SDValue 935HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 936 // VASTART stores the address of the VarArgsFrameIndex slot into the 937 // memory location argument. 938 MachineFunction &MF = DAG.getMachineFunction(); 939 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>(); 940 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32); 941 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 942 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, 943 Op.getOperand(1), MachinePointerInfo(SV), false, 944 false, 0); 945} 946 947SDValue 948HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 949 SDValue LHS = Op.getOperand(0); 950 SDValue RHS = Op.getOperand(1); 951 SDValue CC = Op.getOperand(4); 952 SDValue TrueVal = Op.getOperand(2); 953 SDValue FalseVal = Op.getOperand(3); 954 SDLoc dl(Op); 955 SDNode* OpNode = Op.getNode(); 956 EVT SVT = OpNode->getValueType(0); 957 958 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i1, LHS, RHS, CC); 959 return DAG.getNode(ISD::SELECT, dl, SVT, Cond, TrueVal, FalseVal); 960} 961 962SDValue 963HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 964 EVT ValTy = Op.getValueType(); 965 SDLoc dl(Op); 966 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 967 SDValue Res; 968 if (CP->isMachineConstantPoolEntry()) 969 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), ValTy, 970 CP->getAlignment()); 971 else 972 Res = DAG.getTargetConstantPool(CP->getConstVal(), ValTy, 973 CP->getAlignment()); 974 return DAG.getNode(HexagonISD::CONST32, dl, ValTy, Res); 975} 976 977SDValue 978HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { 979 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 980 MachineFunction &MF = DAG.getMachineFunction(); 981 MachineFrameInfo *MFI = MF.getFrameInfo(); 982 MFI->setReturnAddressIsTaken(true); 983 984 EVT VT = Op.getValueType(); 985 SDLoc dl(Op); 986 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 987 if (Depth) { 988 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 989 SDValue Offset = DAG.getConstant(4, MVT::i32); 990 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 991 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 992 MachinePointerInfo(), false, false, false, 0); 993 } 994 995 // Return LR, which contains the return address. Mark it an implicit live-in. 996 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); 997 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 998} 999 1000SDValue 1001HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1002 const HexagonRegisterInfo *TRI = TM.getRegisterInfo(); 1003 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1004 MFI->setFrameAddressIsTaken(true); 1005 1006 EVT VT = Op.getValueType(); 1007 SDLoc dl(Op); 1008 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1009 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 1010 TRI->getFrameRegister(), VT); 1011 while (Depth--) 1012 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 1013 MachinePointerInfo(), 1014 false, false, false, 0); 1015 return FrameAddr; 1016} 1017 1018SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, 1019 SelectionDAG& DAG) const { 1020 SDLoc dl(Op); 1021 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0)); 1022} 1023 1024 1025SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, 1026 SelectionDAG &DAG) const { 1027 SDValue Result; 1028 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1029 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 1030 SDLoc dl(Op); 1031 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 1032 1033 const HexagonTargetObjectFile &TLOF = 1034 static_cast<const HexagonTargetObjectFile &>(getObjFileLowering()); 1035 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1036 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result); 1037 } 1038 1039 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result); 1040} 1041 1042SDValue 1043HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 1044 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1045 SDValue BA_SD = DAG.getTargetBlockAddress(BA, MVT::i32); 1046 SDLoc dl(Op); 1047 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), BA_SD); 1048} 1049 1050//===----------------------------------------------------------------------===// 1051// TargetLowering Implementation 1052//===----------------------------------------------------------------------===// 1053 1054HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine 1055 &targetmachine) 1056 : TargetLowering(targetmachine, new HexagonTargetObjectFile()), 1057 TM(targetmachine) { 1058 1059 const HexagonRegisterInfo* QRI = TM.getRegisterInfo(); 1060 1061 // Set up the register classes. 1062 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); 1063 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); 1064 1065 if (QRI->Subtarget.hasV5TOps()) { 1066 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); 1067 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); 1068 } 1069 1070 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); 1071 1072 computeRegisterProperties(); 1073 1074 // Align loop entry 1075 setPrefLoopAlignment(4); 1076 1077 // Limits for inline expansion of memcpy/memmove 1078 MaxStoresPerMemcpy = 6; 1079 MaxStoresPerMemmove = 6; 1080 1081 // 1082 // Library calls for unsupported operations 1083 // 1084 1085 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf"); 1086 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf"); 1087 1088 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti"); 1089 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti"); 1090 1091 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti"); 1092 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti"); 1093 1094 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3"); 1095 setOperationAction(ISD::SDIV, MVT::i32, Expand); 1096 setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3"); 1097 setOperationAction(ISD::SREM, MVT::i32, Expand); 1098 1099 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3"); 1100 setOperationAction(ISD::SDIV, MVT::i64, Expand); 1101 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3"); 1102 setOperationAction(ISD::SREM, MVT::i64, Expand); 1103 1104 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3"); 1105 setOperationAction(ISD::UDIV, MVT::i32, Expand); 1106 1107 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3"); 1108 setOperationAction(ISD::UDIV, MVT::i64, Expand); 1109 1110 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3"); 1111 setOperationAction(ISD::UREM, MVT::i32, Expand); 1112 1113 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3"); 1114 setOperationAction(ISD::UREM, MVT::i64, Expand); 1115 1116 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3"); 1117 setOperationAction(ISD::FDIV, MVT::f32, Expand); 1118 1119 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3"); 1120 setOperationAction(ISD::FDIV, MVT::f64, Expand); 1121 1122 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 1123 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 1124 setOperationAction(ISD::FSIN, MVT::f32, Expand); 1125 setOperationAction(ISD::FSIN, MVT::f64, Expand); 1126 1127 if (QRI->Subtarget.hasV5TOps()) { 1128 // Hexagon V5 Support. 1129 setOperationAction(ISD::FADD, MVT::f32, Legal); 1130 setOperationAction(ISD::FADD, MVT::f64, Legal); 1131 setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal); 1132 setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal); 1133 setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal); 1134 setCondCodeAction(ISD::SETUEQ, MVT::f32, Legal); 1135 setCondCodeAction(ISD::SETUEQ, MVT::f64, Legal); 1136 1137 setCondCodeAction(ISD::SETOGE, MVT::f32, Legal); 1138 setCondCodeAction(ISD::SETOGE, MVT::f64, Legal); 1139 setCondCodeAction(ISD::SETUGE, MVT::f32, Legal); 1140 setCondCodeAction(ISD::SETUGE, MVT::f64, Legal); 1141 1142 setCondCodeAction(ISD::SETOGT, MVT::f32, Legal); 1143 setCondCodeAction(ISD::SETOGT, MVT::f64, Legal); 1144 setCondCodeAction(ISD::SETUGT, MVT::f32, Legal); 1145 setCondCodeAction(ISD::SETUGT, MVT::f64, Legal); 1146 1147 setCondCodeAction(ISD::SETOLE, MVT::f32, Legal); 1148 setCondCodeAction(ISD::SETOLE, MVT::f64, Legal); 1149 setCondCodeAction(ISD::SETOLT, MVT::f32, Legal); 1150 setCondCodeAction(ISD::SETOLT, MVT::f64, Legal); 1151 1152 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 1153 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); 1154 1155 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); 1156 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); 1157 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); 1158 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); 1159 1160 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); 1161 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); 1162 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); 1163 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); 1164 1165 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); 1166 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); 1167 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); 1168 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); 1169 1170 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal); 1171 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); 1172 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); 1173 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); 1174 1175 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal); 1176 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal); 1177 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal); 1178 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal); 1179 1180 setOperationAction(ISD::FABS, MVT::f32, Legal); 1181 setOperationAction(ISD::FABS, MVT::f64, Expand); 1182 1183 setOperationAction(ISD::FNEG, MVT::f32, Legal); 1184 setOperationAction(ISD::FNEG, MVT::f64, Expand); 1185 } else { 1186 1187 // Expand fp<->uint. 1188 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); 1189 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 1190 1191 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 1192 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 1193 1194 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf"); 1195 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf"); 1196 1197 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf"); 1198 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf"); 1199 1200 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf"); 1201 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf"); 1202 1203 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf"); 1204 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf"); 1205 1206 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi"); 1207 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi"); 1208 1209 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi"); 1210 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi"); 1211 1212 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi"); 1213 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi"); 1214 1215 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3"); 1216 setOperationAction(ISD::FADD, MVT::f64, Expand); 1217 1218 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3"); 1219 setOperationAction(ISD::FADD, MVT::f32, Expand); 1220 1221 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2"); 1222 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand); 1223 1224 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2"); 1225 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 1226 1227 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2"); 1228 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 1229 1230 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2"); 1231 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 1232 1233 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2"); 1234 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 1235 1236 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2"); 1237 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); 1238 1239 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2"); 1240 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand); 1241 1242 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi"); 1243 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand); 1244 1245 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi"); 1246 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand); 1247 1248 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2"); 1249 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 1250 1251 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2"); 1252 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 1253 1254 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2"); 1255 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand); 1256 1257 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2"); 1258 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); 1259 1260 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3"); 1261 setOperationAction(ISD::FMUL, MVT::f64, Expand); 1262 1263 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3"); 1264 setOperationAction(ISD::MUL, MVT::f32, Expand); 1265 1266 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2"); 1267 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 1268 1269 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2"); 1270 1271 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3"); 1272 setOperationAction(ISD::SUB, MVT::f64, Expand); 1273 1274 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3"); 1275 setOperationAction(ISD::SUB, MVT::f32, Expand); 1276 1277 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2"); 1278 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand); 1279 1280 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2"); 1281 setCondCodeAction(ISD::SETUO, MVT::f64, Expand); 1282 1283 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2"); 1284 setCondCodeAction(ISD::SETO, MVT::f64, Expand); 1285 1286 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2"); 1287 setCondCodeAction(ISD::SETO, MVT::f32, Expand); 1288 1289 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2"); 1290 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); 1291 1292 setOperationAction(ISD::FABS, MVT::f32, Expand); 1293 setOperationAction(ISD::FABS, MVT::f64, Expand); 1294 setOperationAction(ISD::FNEG, MVT::f32, Expand); 1295 setOperationAction(ISD::FNEG, MVT::f64, Expand); 1296 } 1297 1298 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3"); 1299 setOperationAction(ISD::SREM, MVT::i32, Expand); 1300 1301 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 1302 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 1303 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); 1304 setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal); 1305 1306 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); 1307 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); 1308 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); 1309 setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal); 1310 1311 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 1312 1313 // Turn FP extload into load/fextend. 1314 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 1315 // Hexagon has a i1 sign extending load. 1316 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand); 1317 // Turn FP truncstore into trunc + store. 1318 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 1319 1320 // Custom legalize GlobalAddress nodes into CONST32. 1321 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 1322 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom); 1323 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 1324 // Truncate action? 1325 setOperationAction(ISD::TRUNCATE, MVT::i64, Expand); 1326 1327 // Hexagon doesn't have sext_inreg, replace them with shl/sra. 1328 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 1329 1330 // Hexagon has no REM or DIVREM operations. 1331 setOperationAction(ISD::UREM, MVT::i32, Expand); 1332 setOperationAction(ISD::SREM, MVT::i32, Expand); 1333 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 1334 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 1335 setOperationAction(ISD::SREM, MVT::i64, Expand); 1336 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 1337 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 1338 1339 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 1340 1341 // Lower SELECT_CC to SETCC and SELECT. 1342 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 1343 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 1344 1345 if (QRI->Subtarget.hasV5TOps()) { 1346 1347 // We need to make the operation type of SELECT node to be Custom, 1348 // such that we don't go into the infinite loop of 1349 // select -> setcc -> select_cc -> select loop. 1350 setOperationAction(ISD::SELECT, MVT::f32, Custom); 1351 setOperationAction(ISD::SELECT, MVT::f64, Custom); 1352 1353 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 1354 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 1355 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 1356 1357 } else { 1358 1359 // Hexagon has no select or setcc: expand to SELECT_CC. 1360 setOperationAction(ISD::SELECT, MVT::f32, Expand); 1361 setOperationAction(ISD::SELECT, MVT::f64, Expand); 1362 1363 // This is a workaround documented in DAGCombiner.cpp:2892 We don't 1364 // support SELECT_CC on every type. 1365 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 1366 1367 } 1368 1369 if (EmitJumpTables) { 1370 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 1371 } else { 1372 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 1373 } 1374 // Increase jump tables cutover to 5, was 4. 1375 setMinimumJumpTableEntries(5); 1376 1377 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 1378 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 1379 setOperationAction(ISD::BR_CC, MVT::i1, Expand); 1380 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 1381 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 1382 1383 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 1384 1385 setOperationAction(ISD::FSIN , MVT::f64, Expand); 1386 setOperationAction(ISD::FCOS , MVT::f64, Expand); 1387 setOperationAction(ISD::FREM , MVT::f64, Expand); 1388 setOperationAction(ISD::FSIN , MVT::f32, Expand); 1389 setOperationAction(ISD::FCOS , MVT::f32, Expand); 1390 setOperationAction(ISD::FREM , MVT::f32, Expand); 1391 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 1392 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 1393 1394 // In V4, we have double word add/sub with carry. The problem with 1395 // modelling this instruction is that it produces 2 results - Rdd and Px. 1396 // To model update of Px, we will have to use Defs[p0..p3] which will 1397 // cause any predicate live range to spill. So, we pretend we dont't 1398 // have these instructions. 1399 setOperationAction(ISD::ADDE, MVT::i8, Expand); 1400 setOperationAction(ISD::ADDE, MVT::i16, Expand); 1401 setOperationAction(ISD::ADDE, MVT::i32, Expand); 1402 setOperationAction(ISD::ADDE, MVT::i64, Expand); 1403 setOperationAction(ISD::SUBE, MVT::i8, Expand); 1404 setOperationAction(ISD::SUBE, MVT::i16, Expand); 1405 setOperationAction(ISD::SUBE, MVT::i32, Expand); 1406 setOperationAction(ISD::SUBE, MVT::i64, Expand); 1407 setOperationAction(ISD::ADDC, MVT::i8, Expand); 1408 setOperationAction(ISD::ADDC, MVT::i16, Expand); 1409 setOperationAction(ISD::ADDC, MVT::i32, Expand); 1410 setOperationAction(ISD::ADDC, MVT::i64, Expand); 1411 setOperationAction(ISD::SUBC, MVT::i8, Expand); 1412 setOperationAction(ISD::SUBC, MVT::i16, Expand); 1413 setOperationAction(ISD::SUBC, MVT::i32, Expand); 1414 setOperationAction(ISD::SUBC, MVT::i64, Expand); 1415 1416 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 1417 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 1418 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 1419 setOperationAction(ISD::CTTZ , MVT::i64, Expand); 1420 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 1421 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 1422 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 1423 setOperationAction(ISD::CTLZ , MVT::i64, Expand); 1424 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 1425 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 1426 setOperationAction(ISD::ROTL , MVT::i32, Expand); 1427 setOperationAction(ISD::ROTR , MVT::i32, Expand); 1428 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 1429 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 1430 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 1431 setOperationAction(ISD::FPOW , MVT::f64, Expand); 1432 setOperationAction(ISD::FPOW , MVT::f32, Expand); 1433 1434 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 1435 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 1436 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 1437 1438 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 1439 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 1440 1441 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 1442 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 1443 1444 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 1445 1446 if (TM.getSubtargetImpl()->isSubtargetV2()) { 1447 setExceptionPointerRegister(Hexagon::R20); 1448 setExceptionSelectorRegister(Hexagon::R21); 1449 } else { 1450 setExceptionPointerRegister(Hexagon::R0); 1451 setExceptionSelectorRegister(Hexagon::R1); 1452 } 1453 1454 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 1455 setOperationAction(ISD::VASTART , MVT::Other, Custom); 1456 1457 // Use the default implementation. 1458 setOperationAction(ISD::VAARG , MVT::Other, Expand); 1459 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 1460 setOperationAction(ISD::VAEND , MVT::Other, Expand); 1461 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 1462 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 1463 1464 1465 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 1466 setOperationAction(ISD::INLINEASM , MVT::Other, Custom); 1467 1468 setMinFunctionAlignment(2); 1469 1470 // Needed for DYNAMIC_STACKALLOC expansion. 1471 unsigned StackRegister = TM.getRegisterInfo()->getStackRegister(); 1472 setStackPointerRegisterToSaveRestore(StackRegister); 1473 setSchedulingPreference(Sched::VLIW); 1474} 1475 1476 1477const char* 1478HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { 1479 switch (Opcode) { 1480 default: return 0; 1481 case HexagonISD::CONST32: return "HexagonISD::CONST32"; 1482 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP"; 1483 case HexagonISD::CONST32_Int_Real: return "HexagonISD::CONST32_Int_Real"; 1484 case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC"; 1485 case HexagonISD::CMPICC: return "HexagonISD::CMPICC"; 1486 case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC"; 1487 case HexagonISD::BRICC: return "HexagonISD::BRICC"; 1488 case HexagonISD::BRFCC: return "HexagonISD::BRFCC"; 1489 case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC"; 1490 case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC"; 1491 case HexagonISD::Hi: return "HexagonISD::Hi"; 1492 case HexagonISD::Lo: return "HexagonISD::Lo"; 1493 case HexagonISD::FTOI: return "HexagonISD::FTOI"; 1494 case HexagonISD::ITOF: return "HexagonISD::ITOF"; 1495 case HexagonISD::CALL: return "HexagonISD::CALL"; 1496 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG"; 1497 case HexagonISD::BR_JT: return "HexagonISD::BR_JT"; 1498 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN"; 1499 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN"; 1500 } 1501} 1502 1503bool 1504HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 1505 EVT MTy1 = EVT::getEVT(Ty1); 1506 EVT MTy2 = EVT::getEVT(Ty2); 1507 if (!MTy1.isSimple() || !MTy2.isSimple()) { 1508 return false; 1509 } 1510 return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32)); 1511} 1512 1513bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 1514 if (!VT1.isSimple() || !VT2.isSimple()) { 1515 return false; 1516 } 1517 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32)); 1518} 1519 1520bool 1521HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const { 1522 // Assuming the caller does not have either a signext or zeroext modifier, and 1523 // only one value is accepted, any reasonable truncation is allowed. 1524 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 1525 return false; 1526 1527 // FIXME: in principle up to 64-bit could be made safe, but it would be very 1528 // fragile at the moment: any support for multiple value returns would be 1529 // liable to disallow tail calls involving i64 -> iN truncation in many cases. 1530 return Ty1->getPrimitiveSizeInBits() <= 32; 1531} 1532 1533SDValue 1534HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 1535 SDValue Chain = Op.getOperand(0); 1536 SDValue Offset = Op.getOperand(1); 1537 SDValue Handler = Op.getOperand(2); 1538 SDLoc dl(Op); 1539 1540 // Mark function as containing a call to EH_RETURN. 1541 HexagonMachineFunctionInfo *FuncInfo = 1542 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>(); 1543 FuncInfo->setHasEHReturn(); 1544 1545 unsigned OffsetReg = Hexagon::R28; 1546 1547 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), 1548 DAG.getRegister(Hexagon::R30, getPointerTy()), 1549 DAG.getIntPtrConstant(4)); 1550 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 1551 false, false, 0); 1552 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); 1553 1554 // Not needed we already use it as explict input to EH_RETURN. 1555 // MF.getRegInfo().addLiveOut(OffsetReg); 1556 1557 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain); 1558} 1559 1560SDValue 1561HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 1562 switch (Op.getOpcode()) { 1563 default: llvm_unreachable("Should not custom lower this!"); 1564 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1565 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 1566 // Frame & Return address. Currently unimplemented. 1567 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1568 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1569 case ISD::GlobalTLSAddress: 1570 llvm_unreachable("TLS not implemented for Hexagon."); 1571 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 1572 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); 1573 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 1574 case ISD::VASTART: return LowerVASTART(Op, DAG); 1575 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1576 1577 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 1578 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1579 case ISD::SELECT: return Op; 1580 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 1581 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG); 1582 1583 } 1584} 1585 1586 1587 1588//===----------------------------------------------------------------------===// 1589// Hexagon Scheduler Hooks 1590//===----------------------------------------------------------------------===// 1591MachineBasicBlock * 1592HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1593 MachineBasicBlock *BB) 1594const { 1595 switch (MI->getOpcode()) { 1596 case Hexagon::ADJDYNALLOC: { 1597 MachineFunction *MF = BB->getParent(); 1598 HexagonMachineFunctionInfo *FuncInfo = 1599 MF->getInfo<HexagonMachineFunctionInfo>(); 1600 FuncInfo->addAllocaAdjustInst(MI); 1601 return BB; 1602 } 1603 default: llvm_unreachable("Unexpected instr type to insert"); 1604 } // switch 1605} 1606 1607//===----------------------------------------------------------------------===// 1608// Inline Assembly Support 1609//===----------------------------------------------------------------------===// 1610 1611std::pair<unsigned, const TargetRegisterClass*> 1612HexagonTargetLowering::getRegForInlineAsmConstraint(const 1613 std::string &Constraint, 1614 MVT VT) const { 1615 if (Constraint.size() == 1) { 1616 switch (Constraint[0]) { 1617 case 'r': // R0-R31 1618 switch (VT.SimpleTy) { 1619 default: 1620 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type"); 1621 case MVT::i32: 1622 case MVT::i16: 1623 case MVT::i8: 1624 case MVT::f32: 1625 return std::make_pair(0U, &Hexagon::IntRegsRegClass); 1626 case MVT::i64: 1627 case MVT::f64: 1628 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass); 1629 } 1630 default: 1631 llvm_unreachable("Unknown asm register class"); 1632 } 1633 } 1634 1635 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1636} 1637 1638/// isFPImmLegal - Returns true if the target can instruction select the 1639/// specified FP immediate natively. If false, the legalizer will 1640/// materialize the FP immediate as a load from a constant pool. 1641bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 1642 const HexagonRegisterInfo* QRI = TM.getRegisterInfo(); 1643 return QRI->Subtarget.hasV5TOps(); 1644} 1645 1646/// isLegalAddressingMode - Return true if the addressing mode represented by 1647/// AM is legal for this target, for a load/store of the specified type. 1648bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1649 Type *Ty) const { 1650 // Allows a signed-extended 11-bit immediate field. 1651 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) { 1652 return false; 1653 } 1654 1655 // No global is ever allowed as a base. 1656 if (AM.BaseGV) { 1657 return false; 1658 } 1659 1660 int Scale = AM.Scale; 1661 if (Scale < 0) Scale = -Scale; 1662 switch (Scale) { 1663 case 0: // No scale reg, "r+i", "r", or just "i". 1664 break; 1665 default: // No scaled addressing mode. 1666 return false; 1667 } 1668 return true; 1669} 1670 1671/// isLegalICmpImmediate - Return true if the specified immediate is legal 1672/// icmp immediate, that is the target has icmp instructions which can compare 1673/// a register against the immediate without having to materialize the 1674/// immediate into a register. 1675bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 1676 return Imm >= -512 && Imm <= 511; 1677} 1678 1679/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1680/// for tail call optimization. Targets which want to do tail call 1681/// optimization should implement this function. 1682bool HexagonTargetLowering::IsEligibleForTailCallOptimization( 1683 SDValue Callee, 1684 CallingConv::ID CalleeCC, 1685 bool isVarArg, 1686 bool isCalleeStructRet, 1687 bool isCallerStructRet, 1688 const SmallVectorImpl<ISD::OutputArg> &Outs, 1689 const SmallVectorImpl<SDValue> &OutVals, 1690 const SmallVectorImpl<ISD::InputArg> &Ins, 1691 SelectionDAG& DAG) const { 1692 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1693 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1694 bool CCMatch = CallerCC == CalleeCC; 1695 1696 // *************************************************************************** 1697 // Look for obvious safe cases to perform tail call optimization that do not 1698 // require ABI changes. 1699 // *************************************************************************** 1700 1701 // If this is a tail call via a function pointer, then don't do it! 1702 if (!(dyn_cast<GlobalAddressSDNode>(Callee)) 1703 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) { 1704 return false; 1705 } 1706 1707 // Do not optimize if the calling conventions do not match. 1708 if (!CCMatch) 1709 return false; 1710 1711 // Do not tail call optimize vararg calls. 1712 if (isVarArg) 1713 return false; 1714 1715 // Also avoid tail call optimization if either caller or callee uses struct 1716 // return semantics. 1717 if (isCalleeStructRet || isCallerStructRet) 1718 return false; 1719 1720 // In addition to the cases above, we also disable Tail Call Optimization if 1721 // the calling convention code that at least one outgoing argument needs to 1722 // go on the stack. We cannot check that here because at this point that 1723 // information is not available. 1724 return true; 1725} 1726