ARMSelectionDAGInfo.h revision 263508 
1//===-- ARMSelectionDAGInfo.h - ARM SelectionDAG Info -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the ARM subclass for TargetSelectionDAGInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSELECTIONDAGINFO_H
15#define ARMSELECTIONDAGINFO_H
16
17#include "MCTargetDesc/ARMAddressingModes.h"
18#include "llvm/Target/TargetSelectionDAGInfo.h"
19
20namespace llvm {
21
22namespace ARM_AM {
23  static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
24    switch (Opcode) {
25    default:          return ARM_AM::no_shift;
26    case ISD::SHL:    return ARM_AM::lsl;
27    case ISD::SRL:    return ARM_AM::lsr;
28    case ISD::SRA:    return ARM_AM::asr;
29    case ISD::ROTR:   return ARM_AM::ror;
30    //case ISD::ROTL:  // Only if imm -> turn into ROTR.
31    // Can't handle RRX here, because it would require folding a flag into
32    // the addressing mode.  :(  This causes us to miss certain things.
33    //case ARMISD::RRX: return ARM_AM::rrx;
34    }
35  }
36}  // end namespace ARM_AM
37
38class ARMSelectionDAGInfo : public TargetSelectionDAGInfo {
39  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
40  /// make the right decision when generating code for different targets.
41  const ARMSubtarget *Subtarget;
42
43public:
44  explicit ARMSelectionDAGInfo(const TargetMachine &TM);
45  ~ARMSelectionDAGInfo();
46
47  virtual
48  SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
49                                  SDValue Chain,
50                                  SDValue Dst, SDValue Src,
51                                  SDValue Size, unsigned Align,
52                                  bool isVolatile, bool AlwaysInline,
53                                  MachinePointerInfo DstPtrInfo,
54                                  MachinePointerInfo SrcPtrInfo) const;
55
56  // Adjust parameters for memset, see RTABI section 4.3.4
57  virtual
58  SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
59                                  SDValue Chain,
60                                  SDValue Op1, SDValue Op2,
61                                  SDValue Op3, unsigned Align,
62                                  bool isVolatile,
63                                  MachinePointerInfo DstPtrInfo) const;
64};
65
66}
67
68#endif
69