ARMISelDAGToDAG.cpp revision 263508 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "arm-isel"
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMTargetMachine.h"
18#include "MCTargetDesc/ARMAddressingModes.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24#include "llvm/CodeGen/SelectionDAGISel.h"
25#include "llvm/IR/CallingConv.h"
26#include "llvm/IR/Constants.h"
27#include "llvm/IR/DerivedTypes.h"
28#include "llvm/IR/Function.h"
29#include "llvm/IR/Intrinsics.h"
30#include "llvm/IR/LLVMContext.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/Compiler.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/raw_ostream.h"
36#include "llvm/Target/TargetLowering.h"
37#include "llvm/Target/TargetOptions.h"
38
39using namespace llvm;
40
41static cl::opt<bool>
42DisableShifterOp("disable-shifter-op", cl::Hidden,
43  cl::desc("Disable isel of shifter-op"),
44  cl::init(false));
45
46static cl::opt<bool>
47CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
48  cl::desc("Check fp vmla / vmls hazard at isel time"),
49  cl::init(true));
50
51//===--------------------------------------------------------------------===//
52/// ARMDAGToDAGISel - ARM specific code to select ARM machine
53/// instructions for SelectionDAG operations.
54///
55namespace {
56
57enum AddrMode2Type {
58  AM2_BASE, // Simple AM2 (+-imm12)
59  AM2_SHOP  // Shifter-op AM2
60};
61
62class ARMDAGToDAGISel : public SelectionDAGISel {
63  ARMBaseTargetMachine &TM;
64
65  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66  /// make the right decision when generating code for different targets.
67  const ARMSubtarget *Subtarget;
68
69public:
70  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
71                           CodeGenOpt::Level OptLevel)
72    : SelectionDAGISel(tm, OptLevel), TM(tm),
73      Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
74  }
75
76  virtual const char *getPassName() const {
77    return "ARM Instruction Selection";
78  }
79
80  virtual void PreprocessISelDAG();
81
82  /// getI32Imm - Return a target constant of type i32 with the specified
83  /// value.
84  inline SDValue getI32Imm(unsigned Imm) {
85    return CurDAG->getTargetConstant(Imm, MVT::i32);
86  }
87
88  SDNode *Select(SDNode *N);
89
90
91  bool hasNoVMLxHazardUse(SDNode *N) const;
92  bool isShifterOpProfitable(const SDValue &Shift,
93                             ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
94  bool SelectRegShifterOperand(SDValue N, SDValue &A,
95                               SDValue &B, SDValue &C,
96                               bool CheckProfitability = true);
97  bool SelectImmShifterOperand(SDValue N, SDValue &A,
98                               SDValue &B, bool CheckProfitability = true);
99  bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
100                                    SDValue &B, SDValue &C) {
101    // Don't apply the profitability check
102    return SelectRegShifterOperand(N, A, B, C, false);
103  }
104  bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
105                                    SDValue &B) {
106    // Don't apply the profitability check
107    return SelectImmShifterOperand(N, A, B, false);
108  }
109
110  bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
111  bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
112
113  AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
114                                      SDValue &Offset, SDValue &Opc);
115  bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
116                           SDValue &Opc) {
117    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
118  }
119
120  bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
121                           SDValue &Opc) {
122    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
123  }
124
125  bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
126                       SDValue &Opc) {
127    SelectAddrMode2Worker(N, Base, Offset, Opc);
128//    return SelectAddrMode2ShOp(N, Base, Offset, Opc);
129    // This always matches one way or another.
130    return true;
131  }
132
133  bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
134    const ConstantSDNode *CN = cast<ConstantSDNode>(N);
135    Pred = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
136    Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
137    return true;
138  }
139
140  bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
141                             SDValue &Offset, SDValue &Opc);
142  bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
143                             SDValue &Offset, SDValue &Opc);
144  bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
145                             SDValue &Offset, SDValue &Opc);
146  bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
147  bool SelectAddrMode3(SDValue N, SDValue &Base,
148                       SDValue &Offset, SDValue &Opc);
149  bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
150                             SDValue &Offset, SDValue &Opc);
151  bool SelectAddrMode5(SDValue N, SDValue &Base,
152                       SDValue &Offset);
153  bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
154  bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
155
156  bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
157
158  // Thumb Addressing Modes:
159  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
160  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
161                             unsigned Scale);
162  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
163  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
164  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
165  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
166                                SDValue &OffImm);
167  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
168                                 SDValue &OffImm);
169  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
170                                 SDValue &OffImm);
171  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
172                                 SDValue &OffImm);
173  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
174
175  // Thumb 2 Addressing Modes:
176  bool SelectT2ShifterOperandReg(SDValue N,
177                                 SDValue &BaseReg, SDValue &Opc);
178  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
179  bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
180                            SDValue &OffImm);
181  bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
182                                 SDValue &OffImm);
183  bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
184                             SDValue &OffReg, SDValue &ShImm);
185  bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
186
187  inline bool is_so_imm(unsigned Imm) const {
188    return ARM_AM::getSOImmVal(Imm) != -1;
189  }
190
191  inline bool is_so_imm_not(unsigned Imm) const {
192    return ARM_AM::getSOImmVal(~Imm) != -1;
193  }
194
195  inline bool is_t2_so_imm(unsigned Imm) const {
196    return ARM_AM::getT2SOImmVal(Imm) != -1;
197  }
198
199  inline bool is_t2_so_imm_not(unsigned Imm) const {
200    return ARM_AM::getT2SOImmVal(~Imm) != -1;
201  }
202
203  // Include the pieces autogenerated from the target description.
204#include "ARMGenDAGISel.inc"
205
206private:
207  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
208  /// ARM.
209  SDNode *SelectARMIndexedLoad(SDNode *N);
210  SDNode *SelectT2IndexedLoad(SDNode *N);
211
212  /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
213  /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
214  /// loads of D registers and even subregs and odd subregs of Q registers.
215  /// For NumVecs <= 2, QOpcodes1 is not used.
216  SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
217                    const uint16_t *DOpcodes,
218                    const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
219
220  /// SelectVST - Select NEON store intrinsics.  NumVecs should
221  /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
222  /// stores of D registers and even subregs and odd subregs of Q registers.
223  /// For NumVecs <= 2, QOpcodes1 is not used.
224  SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
225                    const uint16_t *DOpcodes,
226                    const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
227
228  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
229  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
230  /// load/store of D registers and Q registers.
231  SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
232                          bool isUpdating, unsigned NumVecs,
233                          const uint16_t *DOpcodes, const uint16_t *QOpcodes);
234
235  /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
236  /// should be 2, 3 or 4.  The opcode array specifies the instructions used
237  /// for loading D registers.  (Q registers are not supported.)
238  SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
239                       const uint16_t *Opcodes);
240
241  /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
242  /// 3 or 4.  These are custom-selected so that a REG_SEQUENCE can be
243  /// generated to force the table registers to be consecutive.
244  SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
245
246  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
247  SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
248
249  // Select special operations if node forms integer ABS pattern
250  SDNode *SelectABSOp(SDNode *N);
251
252  SDNode *SelectInlineAsm(SDNode *N);
253
254  SDNode *SelectConcatVector(SDNode *N);
255
256  SDNode *SelectAtomic(SDNode *N, unsigned Op8, unsigned Op16, unsigned Op32, unsigned Op64);
257
258  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
259  /// inline asm expressions.
260  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
261                                            char ConstraintCode,
262                                            std::vector<SDValue> &OutOps);
263
264  // Form pairs of consecutive R, S, D, or Q registers.
265  SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
266  SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
267  SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
268  SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
269
270  // Form sequences of 4 consecutive S, D, or Q registers.
271  SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
272  SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
273  SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
274
275  // Get the alignment operand for a NEON VLD or VST instruction.
276  SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
277};
278}
279
280/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
281/// operand. If so Imm will receive the 32-bit value.
282static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
283  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
284    Imm = cast<ConstantSDNode>(N)->getZExtValue();
285    return true;
286  }
287  return false;
288}
289
290// isInt32Immediate - This method tests to see if a constant operand.
291// If so Imm will receive the 32 bit value.
292static bool isInt32Immediate(SDValue N, unsigned &Imm) {
293  return isInt32Immediate(N.getNode(), Imm);
294}
295
296// isOpcWithIntImmediate - This method tests to see if the node is a specific
297// opcode and that it has a immediate integer right operand.
298// If so Imm will receive the 32 bit value.
299static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
300  return N->getOpcode() == Opc &&
301         isInt32Immediate(N->getOperand(1).getNode(), Imm);
302}
303
304/// \brief Check whether a particular node is a constant value representable as
305/// (N * Scale) where (N in [\p RangeMin, \p RangeMax).
306///
307/// \param ScaledConstant [out] - On success, the pre-scaled constant value.
308static bool isScaledConstantInRange(SDValue Node, int Scale,
309                                    int RangeMin, int RangeMax,
310                                    int &ScaledConstant) {
311  assert(Scale > 0 && "Invalid scale!");
312
313  // Check that this is a constant.
314  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
315  if (!C)
316    return false;
317
318  ScaledConstant = (int) C->getZExtValue();
319  if ((ScaledConstant % Scale) != 0)
320    return false;
321
322  ScaledConstant /= Scale;
323  return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
324}
325
326void ARMDAGToDAGISel::PreprocessISelDAG() {
327  if (!Subtarget->hasV6T2Ops())
328    return;
329
330  bool isThumb2 = Subtarget->isThumb();
331  for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
332       E = CurDAG->allnodes_end(); I != E; ) {
333    SDNode *N = I++;  // Preincrement iterator to avoid invalidation issues.
334
335    if (N->getOpcode() != ISD::ADD)
336      continue;
337
338    // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
339    // leading zeros, followed by consecutive set bits, followed by 1 or 2
340    // trailing zeros, e.g. 1020.
341    // Transform the expression to
342    // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
343    // of trailing zeros of c2. The left shift would be folded as an shifter
344    // operand of 'add' and the 'and' and 'srl' would become a bits extraction
345    // node (UBFX).
346
347    SDValue N0 = N->getOperand(0);
348    SDValue N1 = N->getOperand(1);
349    unsigned And_imm = 0;
350    if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
351      if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
352        std::swap(N0, N1);
353    }
354    if (!And_imm)
355      continue;
356
357    // Check if the AND mask is an immediate of the form: 000.....1111111100
358    unsigned TZ = countTrailingZeros(And_imm);
359    if (TZ != 1 && TZ != 2)
360      // Be conservative here. Shifter operands aren't always free. e.g. On
361      // Swift, left shifter operand of 1 / 2 for free but others are not.
362      // e.g.
363      //  ubfx   r3, r1, #16, #8
364      //  ldr.w  r3, [r0, r3, lsl #2]
365      // vs.
366      //  mov.w  r9, #1020
367      //  and.w  r2, r9, r1, lsr #14
368      //  ldr    r2, [r0, r2]
369      continue;
370    And_imm >>= TZ;
371    if (And_imm & (And_imm + 1))
372      continue;
373
374    // Look for (and (srl X, c1), c2).
375    SDValue Srl = N1.getOperand(0);
376    unsigned Srl_imm = 0;
377    if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
378        (Srl_imm <= 2))
379      continue;
380
381    // Make sure first operand is not a shifter operand which would prevent
382    // folding of the left shift.
383    SDValue CPTmp0;
384    SDValue CPTmp1;
385    SDValue CPTmp2;
386    if (isThumb2) {
387      if (SelectT2ShifterOperandReg(N0, CPTmp0, CPTmp1))
388        continue;
389    } else {
390      if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1) ||
391          SelectRegShifterOperand(N0, CPTmp0, CPTmp1, CPTmp2))
392        continue;
393    }
394
395    // Now make the transformation.
396    Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
397                          Srl.getOperand(0),
398                          CurDAG->getConstant(Srl_imm+TZ, MVT::i32));
399    N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
400                         Srl, CurDAG->getConstant(And_imm, MVT::i32));
401    N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
402                         N1, CurDAG->getConstant(TZ, MVT::i32));
403    CurDAG->UpdateNodeOperands(N, N0, N1);
404  }
405}
406
407/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
408/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
409/// least on current ARM implementations) which should be avoidded.
410bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
411  if (OptLevel == CodeGenOpt::None)
412    return true;
413
414  if (!CheckVMLxHazard)
415    return true;
416
417  if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9() &&
418      !Subtarget->isSwift())
419    return true;
420
421  if (!N->hasOneUse())
422    return false;
423
424  SDNode *Use = *N->use_begin();
425  if (Use->getOpcode() == ISD::CopyToReg)
426    return true;
427  if (Use->isMachineOpcode()) {
428    const ARMBaseInstrInfo *TII =
429      static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
430
431    const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
432    if (MCID.mayStore())
433      return true;
434    unsigned Opcode = MCID.getOpcode();
435    if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
436      return true;
437    // vmlx feeding into another vmlx. We actually want to unfold
438    // the use later in the MLxExpansion pass. e.g.
439    // vmla
440    // vmla (stall 8 cycles)
441    //
442    // vmul (5 cycles)
443    // vadd (5 cycles)
444    // vmla
445    // This adds up to about 18 - 19 cycles.
446    //
447    // vmla
448    // vmul (stall 4 cycles)
449    // vadd adds up to about 14 cycles.
450    return TII->isFpMLxInstruction(Opcode);
451  }
452
453  return false;
454}
455
456bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
457                                            ARM_AM::ShiftOpc ShOpcVal,
458                                            unsigned ShAmt) {
459  if (!Subtarget->isLikeA9() && !Subtarget->isSwift())
460    return true;
461  if (Shift.hasOneUse())
462    return true;
463  // R << 2 is free.
464  return ShOpcVal == ARM_AM::lsl &&
465         (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
466}
467
468bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
469                                              SDValue &BaseReg,
470                                              SDValue &Opc,
471                                              bool CheckProfitability) {
472  if (DisableShifterOp)
473    return false;
474
475  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
476
477  // Don't match base register only case. That is matched to a separate
478  // lower complexity pattern with explicit register operand.
479  if (ShOpcVal == ARM_AM::no_shift) return false;
480
481  BaseReg = N.getOperand(0);
482  unsigned ShImmVal = 0;
483  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
484  if (!RHS) return false;
485  ShImmVal = RHS->getZExtValue() & 31;
486  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
487                                  MVT::i32);
488  return true;
489}
490
491bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
492                                              SDValue &BaseReg,
493                                              SDValue &ShReg,
494                                              SDValue &Opc,
495                                              bool CheckProfitability) {
496  if (DisableShifterOp)
497    return false;
498
499  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
500
501  // Don't match base register only case. That is matched to a separate
502  // lower complexity pattern with explicit register operand.
503  if (ShOpcVal == ARM_AM::no_shift) return false;
504
505  BaseReg = N.getOperand(0);
506  unsigned ShImmVal = 0;
507  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
508  if (RHS) return false;
509
510  ShReg = N.getOperand(1);
511  if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
512    return false;
513  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
514                                  MVT::i32);
515  return true;
516}
517
518
519bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
520                                          SDValue &Base,
521                                          SDValue &OffImm) {
522  // Match simple R + imm12 operands.
523
524  // Base only.
525  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
526      !CurDAG->isBaseWithConstantOffset(N)) {
527    if (N.getOpcode() == ISD::FrameIndex) {
528      // Match frame index.
529      int FI = cast<FrameIndexSDNode>(N)->getIndex();
530      Base = CurDAG->getTargetFrameIndex(FI,
531                                         getTargetLowering()->getPointerTy());
532      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
533      return true;
534    }
535
536    if (N.getOpcode() == ARMISD::Wrapper &&
537        !(Subtarget->useMovt() &&
538                     N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
539      Base = N.getOperand(0);
540    } else
541      Base = N;
542    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
543    return true;
544  }
545
546  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
547    int RHSC = (int)RHS->getZExtValue();
548    if (N.getOpcode() == ISD::SUB)
549      RHSC = -RHSC;
550
551    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
552      Base   = N.getOperand(0);
553      if (Base.getOpcode() == ISD::FrameIndex) {
554        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
555        Base = CurDAG->getTargetFrameIndex(FI,
556                                           getTargetLowering()->getPointerTy());
557      }
558      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
559      return true;
560    }
561  }
562
563  // Base only.
564  Base = N;
565  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
566  return true;
567}
568
569
570
571bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
572                                      SDValue &Opc) {
573  if (N.getOpcode() == ISD::MUL &&
574      ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.hasOneUse())) {
575    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
576      // X * [3,5,9] -> X + X * [2,4,8] etc.
577      int RHSC = (int)RHS->getZExtValue();
578      if (RHSC & 1) {
579        RHSC = RHSC & ~1;
580        ARM_AM::AddrOpc AddSub = ARM_AM::add;
581        if (RHSC < 0) {
582          AddSub = ARM_AM::sub;
583          RHSC = - RHSC;
584        }
585        if (isPowerOf2_32(RHSC)) {
586          unsigned ShAmt = Log2_32(RHSC);
587          Base = Offset = N.getOperand(0);
588          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
589                                                            ARM_AM::lsl),
590                                          MVT::i32);
591          return true;
592        }
593      }
594    }
595  }
596
597  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
598      // ISD::OR that is equivalent to an ISD::ADD.
599      !CurDAG->isBaseWithConstantOffset(N))
600    return false;
601
602  // Leave simple R +/- imm12 operands for LDRi12
603  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
604    int RHSC;
605    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
606                                -0x1000+1, 0x1000, RHSC)) // 12 bits.
607      return false;
608  }
609
610  // Otherwise this is R +/- [possibly shifted] R.
611  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
612  ARM_AM::ShiftOpc ShOpcVal =
613    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
614  unsigned ShAmt = 0;
615
616  Base   = N.getOperand(0);
617  Offset = N.getOperand(1);
618
619  if (ShOpcVal != ARM_AM::no_shift) {
620    // Check to see if the RHS of the shift is a constant, if not, we can't fold
621    // it.
622    if (ConstantSDNode *Sh =
623           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
624      ShAmt = Sh->getZExtValue();
625      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
626        Offset = N.getOperand(1).getOperand(0);
627      else {
628        ShAmt = 0;
629        ShOpcVal = ARM_AM::no_shift;
630      }
631    } else {
632      ShOpcVal = ARM_AM::no_shift;
633    }
634  }
635
636  // Try matching (R shl C) + (R).
637  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
638      !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
639        N.getOperand(0).hasOneUse())) {
640    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
641    if (ShOpcVal != ARM_AM::no_shift) {
642      // Check to see if the RHS of the shift is a constant, if not, we can't
643      // fold it.
644      if (ConstantSDNode *Sh =
645          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
646        ShAmt = Sh->getZExtValue();
647        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
648          Offset = N.getOperand(0).getOperand(0);
649          Base = N.getOperand(1);
650        } else {
651          ShAmt = 0;
652          ShOpcVal = ARM_AM::no_shift;
653        }
654      } else {
655        ShOpcVal = ARM_AM::no_shift;
656      }
657    }
658  }
659
660  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
661                                  MVT::i32);
662  return true;
663}
664
665
666//-----
667
668AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
669                                                     SDValue &Base,
670                                                     SDValue &Offset,
671                                                     SDValue &Opc) {
672  if (N.getOpcode() == ISD::MUL &&
673      (!(Subtarget->isLikeA9() || Subtarget->isSwift()) || N.hasOneUse())) {
674    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
675      // X * [3,5,9] -> X + X * [2,4,8] etc.
676      int RHSC = (int)RHS->getZExtValue();
677      if (RHSC & 1) {
678        RHSC = RHSC & ~1;
679        ARM_AM::AddrOpc AddSub = ARM_AM::add;
680        if (RHSC < 0) {
681          AddSub = ARM_AM::sub;
682          RHSC = - RHSC;
683        }
684        if (isPowerOf2_32(RHSC)) {
685          unsigned ShAmt = Log2_32(RHSC);
686          Base = Offset = N.getOperand(0);
687          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
688                                                            ARM_AM::lsl),
689                                          MVT::i32);
690          return AM2_SHOP;
691        }
692      }
693    }
694  }
695
696  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
697      // ISD::OR that is equivalent to an ADD.
698      !CurDAG->isBaseWithConstantOffset(N)) {
699    Base = N;
700    if (N.getOpcode() == ISD::FrameIndex) {
701      int FI = cast<FrameIndexSDNode>(N)->getIndex();
702      Base = CurDAG->getTargetFrameIndex(FI,
703                                         getTargetLowering()->getPointerTy());
704    } else if (N.getOpcode() == ARMISD::Wrapper &&
705               !(Subtarget->useMovt() &&
706                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
707      Base = N.getOperand(0);
708    }
709    Offset = CurDAG->getRegister(0, MVT::i32);
710    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
711                                                      ARM_AM::no_shift),
712                                    MVT::i32);
713    return AM2_BASE;
714  }
715
716  // Match simple R +/- imm12 operands.
717  if (N.getOpcode() != ISD::SUB) {
718    int RHSC;
719    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
720                                -0x1000+1, 0x1000, RHSC)) { // 12 bits.
721      Base = N.getOperand(0);
722      if (Base.getOpcode() == ISD::FrameIndex) {
723        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
724        Base = CurDAG->getTargetFrameIndex(FI,
725                                           getTargetLowering()->getPointerTy());
726      }
727      Offset = CurDAG->getRegister(0, MVT::i32);
728
729      ARM_AM::AddrOpc AddSub = ARM_AM::add;
730      if (RHSC < 0) {
731        AddSub = ARM_AM::sub;
732        RHSC = - RHSC;
733      }
734      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
735                                                        ARM_AM::no_shift),
736                                      MVT::i32);
737      return AM2_BASE;
738    }
739  }
740
741  if ((Subtarget->isLikeA9() || Subtarget->isSwift()) && !N.hasOneUse()) {
742    // Compute R +/- (R << N) and reuse it.
743    Base = N;
744    Offset = CurDAG->getRegister(0, MVT::i32);
745    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
746                                                      ARM_AM::no_shift),
747                                    MVT::i32);
748    return AM2_BASE;
749  }
750
751  // Otherwise this is R +/- [possibly shifted] R.
752  ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
753  ARM_AM::ShiftOpc ShOpcVal =
754    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
755  unsigned ShAmt = 0;
756
757  Base   = N.getOperand(0);
758  Offset = N.getOperand(1);
759
760  if (ShOpcVal != ARM_AM::no_shift) {
761    // Check to see if the RHS of the shift is a constant, if not, we can't fold
762    // it.
763    if (ConstantSDNode *Sh =
764           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
765      ShAmt = Sh->getZExtValue();
766      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
767        Offset = N.getOperand(1).getOperand(0);
768      else {
769        ShAmt = 0;
770        ShOpcVal = ARM_AM::no_shift;
771      }
772    } else {
773      ShOpcVal = ARM_AM::no_shift;
774    }
775  }
776
777  // Try matching (R shl C) + (R).
778  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
779      !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
780        N.getOperand(0).hasOneUse())) {
781    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
782    if (ShOpcVal != ARM_AM::no_shift) {
783      // Check to see if the RHS of the shift is a constant, if not, we can't
784      // fold it.
785      if (ConstantSDNode *Sh =
786          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
787        ShAmt = Sh->getZExtValue();
788        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
789          Offset = N.getOperand(0).getOperand(0);
790          Base = N.getOperand(1);
791        } else {
792          ShAmt = 0;
793          ShOpcVal = ARM_AM::no_shift;
794        }
795      } else {
796        ShOpcVal = ARM_AM::no_shift;
797      }
798    }
799  }
800
801  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
802                                  MVT::i32);
803  return AM2_SHOP;
804}
805
806bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
807                                            SDValue &Offset, SDValue &Opc) {
808  unsigned Opcode = Op->getOpcode();
809  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
810    ? cast<LoadSDNode>(Op)->getAddressingMode()
811    : cast<StoreSDNode>(Op)->getAddressingMode();
812  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
813    ? ARM_AM::add : ARM_AM::sub;
814  int Val;
815  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
816    return false;
817
818  Offset = N;
819  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
820  unsigned ShAmt = 0;
821  if (ShOpcVal != ARM_AM::no_shift) {
822    // Check to see if the RHS of the shift is a constant, if not, we can't fold
823    // it.
824    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
825      ShAmt = Sh->getZExtValue();
826      if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
827        Offset = N.getOperand(0);
828      else {
829        ShAmt = 0;
830        ShOpcVal = ARM_AM::no_shift;
831      }
832    } else {
833      ShOpcVal = ARM_AM::no_shift;
834    }
835  }
836
837  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
838                                  MVT::i32);
839  return true;
840}
841
842bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
843                                            SDValue &Offset, SDValue &Opc) {
844  unsigned Opcode = Op->getOpcode();
845  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
846    ? cast<LoadSDNode>(Op)->getAddressingMode()
847    : cast<StoreSDNode>(Op)->getAddressingMode();
848  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
849    ? ARM_AM::add : ARM_AM::sub;
850  int Val;
851  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
852    if (AddSub == ARM_AM::sub) Val *= -1;
853    Offset = CurDAG->getRegister(0, MVT::i32);
854    Opc = CurDAG->getTargetConstant(Val, MVT::i32);
855    return true;
856  }
857
858  return false;
859}
860
861
862bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
863                                            SDValue &Offset, SDValue &Opc) {
864  unsigned Opcode = Op->getOpcode();
865  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
866    ? cast<LoadSDNode>(Op)->getAddressingMode()
867    : cast<StoreSDNode>(Op)->getAddressingMode();
868  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
869    ? ARM_AM::add : ARM_AM::sub;
870  int Val;
871  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
872    Offset = CurDAG->getRegister(0, MVT::i32);
873    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
874                                                      ARM_AM::no_shift),
875                                    MVT::i32);
876    return true;
877  }
878
879  return false;
880}
881
882bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
883  Base = N;
884  return true;
885}
886
887bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
888                                      SDValue &Base, SDValue &Offset,
889                                      SDValue &Opc) {
890  if (N.getOpcode() == ISD::SUB) {
891    // X - C  is canonicalize to X + -C, no need to handle it here.
892    Base = N.getOperand(0);
893    Offset = N.getOperand(1);
894    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
895    return true;
896  }
897
898  if (!CurDAG->isBaseWithConstantOffset(N)) {
899    Base = N;
900    if (N.getOpcode() == ISD::FrameIndex) {
901      int FI = cast<FrameIndexSDNode>(N)->getIndex();
902      Base = CurDAG->getTargetFrameIndex(FI,
903                                         getTargetLowering()->getPointerTy());
904    }
905    Offset = CurDAG->getRegister(0, MVT::i32);
906    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
907    return true;
908  }
909
910  // If the RHS is +/- imm8, fold into addr mode.
911  int RHSC;
912  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
913                              -256 + 1, 256, RHSC)) { // 8 bits.
914    Base = N.getOperand(0);
915    if (Base.getOpcode() == ISD::FrameIndex) {
916      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
917      Base = CurDAG->getTargetFrameIndex(FI,
918                                         getTargetLowering()->getPointerTy());
919    }
920    Offset = CurDAG->getRegister(0, MVT::i32);
921
922    ARM_AM::AddrOpc AddSub = ARM_AM::add;
923    if (RHSC < 0) {
924      AddSub = ARM_AM::sub;
925      RHSC = -RHSC;
926    }
927    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
928    return true;
929  }
930
931  Base = N.getOperand(0);
932  Offset = N.getOperand(1);
933  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
934  return true;
935}
936
937bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
938                                            SDValue &Offset, SDValue &Opc) {
939  unsigned Opcode = Op->getOpcode();
940  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
941    ? cast<LoadSDNode>(Op)->getAddressingMode()
942    : cast<StoreSDNode>(Op)->getAddressingMode();
943  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
944    ? ARM_AM::add : ARM_AM::sub;
945  int Val;
946  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
947    Offset = CurDAG->getRegister(0, MVT::i32);
948    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
949    return true;
950  }
951
952  Offset = N;
953  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
954  return true;
955}
956
957bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
958                                      SDValue &Base, SDValue &Offset) {
959  if (!CurDAG->isBaseWithConstantOffset(N)) {
960    Base = N;
961    if (N.getOpcode() == ISD::FrameIndex) {
962      int FI = cast<FrameIndexSDNode>(N)->getIndex();
963      Base = CurDAG->getTargetFrameIndex(FI,
964                                         getTargetLowering()->getPointerTy());
965    } else if (N.getOpcode() == ARMISD::Wrapper &&
966               !(Subtarget->useMovt() &&
967                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
968      Base = N.getOperand(0);
969    }
970    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
971                                       MVT::i32);
972    return true;
973  }
974
975  // If the RHS is +/- imm8, fold into addr mode.
976  int RHSC;
977  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
978                              -256 + 1, 256, RHSC)) {
979    Base = N.getOperand(0);
980    if (Base.getOpcode() == ISD::FrameIndex) {
981      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
982      Base = CurDAG->getTargetFrameIndex(FI,
983                                         getTargetLowering()->getPointerTy());
984    }
985
986    ARM_AM::AddrOpc AddSub = ARM_AM::add;
987    if (RHSC < 0) {
988      AddSub = ARM_AM::sub;
989      RHSC = -RHSC;
990    }
991    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
992                                       MVT::i32);
993    return true;
994  }
995
996  Base = N;
997  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
998                                     MVT::i32);
999  return true;
1000}
1001
1002bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
1003                                      SDValue &Align) {
1004  Addr = N;
1005
1006  unsigned Alignment = 0;
1007  if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
1008    // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
1009    // The maximum alignment is equal to the memory size being referenced.
1010    unsigned LSNAlign = LSN->getAlignment();
1011    unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
1012    if (LSNAlign >= MemSize && MemSize > 1)
1013      Alignment = MemSize;
1014  } else {
1015    // All other uses of addrmode6 are for intrinsics.  For now just record
1016    // the raw alignment value; it will be refined later based on the legal
1017    // alignment operands for the intrinsic.
1018    Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
1019  }
1020
1021  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1022  return true;
1023}
1024
1025bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
1026                                            SDValue &Offset) {
1027  LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
1028  ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1029  if (AM != ISD::POST_INC)
1030    return false;
1031  Offset = N;
1032  if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
1033    if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
1034      Offset = CurDAG->getRegister(0, MVT::i32);
1035  }
1036  return true;
1037}
1038
1039bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
1040                                       SDValue &Offset, SDValue &Label) {
1041  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
1042    Offset = N.getOperand(0);
1043    SDValue N1 = N.getOperand(1);
1044    Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
1045                                      MVT::i32);
1046    return true;
1047  }
1048
1049  return false;
1050}
1051
1052
1053//===----------------------------------------------------------------------===//
1054//                         Thumb Addressing Modes
1055//===----------------------------------------------------------------------===//
1056
1057bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
1058                                            SDValue &Base, SDValue &Offset){
1059  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1060    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
1061    if (!NC || !NC->isNullValue())
1062      return false;
1063
1064    Base = Offset = N;
1065    return true;
1066  }
1067
1068  Base = N.getOperand(0);
1069  Offset = N.getOperand(1);
1070  return true;
1071}
1072
1073bool
1074ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
1075                                       SDValue &Offset, unsigned Scale) {
1076  if (Scale == 4) {
1077    SDValue TmpBase, TmpOffImm;
1078    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1079      return false;  // We want to select tLDRspi / tSTRspi instead.
1080
1081    if (N.getOpcode() == ARMISD::Wrapper &&
1082        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1083      return false;  // We want to select tLDRpci instead.
1084  }
1085
1086  if (!CurDAG->isBaseWithConstantOffset(N))
1087    return false;
1088
1089  // Thumb does not have [sp, r] address mode.
1090  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1091  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1092  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1093      (RHSR && RHSR->getReg() == ARM::SP))
1094    return false;
1095
1096  // FIXME: Why do we explicitly check for a match here and then return false?
1097  // Presumably to allow something else to match, but shouldn't this be
1098  // documented?
1099  int RHSC;
1100  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1101    return false;
1102
1103  Base = N.getOperand(0);
1104  Offset = N.getOperand(1);
1105  return true;
1106}
1107
1108bool
1109ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1110                                          SDValue &Base,
1111                                          SDValue &Offset) {
1112  return SelectThumbAddrModeRI(N, Base, Offset, 1);
1113}
1114
1115bool
1116ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1117                                          SDValue &Base,
1118                                          SDValue &Offset) {
1119  return SelectThumbAddrModeRI(N, Base, Offset, 2);
1120}
1121
1122bool
1123ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1124                                          SDValue &Base,
1125                                          SDValue &Offset) {
1126  return SelectThumbAddrModeRI(N, Base, Offset, 4);
1127}
1128
1129bool
1130ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1131                                          SDValue &Base, SDValue &OffImm) {
1132  if (Scale == 4) {
1133    SDValue TmpBase, TmpOffImm;
1134    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1135      return false;  // We want to select tLDRspi / tSTRspi instead.
1136
1137    if (N.getOpcode() == ARMISD::Wrapper &&
1138        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1139      return false;  // We want to select tLDRpci instead.
1140  }
1141
1142  if (!CurDAG->isBaseWithConstantOffset(N)) {
1143    if (N.getOpcode() == ARMISD::Wrapper &&
1144        !(Subtarget->useMovt() &&
1145          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1146      Base = N.getOperand(0);
1147    } else {
1148      Base = N;
1149    }
1150
1151    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1152    return true;
1153  }
1154
1155  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1156  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1157  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1158      (RHSR && RHSR->getReg() == ARM::SP)) {
1159    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1160    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1161    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1162    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1163
1164    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1165    if (LHSC != 0 || RHSC != 0) return false;
1166
1167    Base = N;
1168    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1169    return true;
1170  }
1171
1172  // If the RHS is + imm5 * scale, fold into addr mode.
1173  int RHSC;
1174  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1175    Base = N.getOperand(0);
1176    OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1177    return true;
1178  }
1179
1180  Base = N.getOperand(0);
1181  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1182  return true;
1183}
1184
1185bool
1186ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1187                                           SDValue &OffImm) {
1188  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1189}
1190
1191bool
1192ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1193                                           SDValue &OffImm) {
1194  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1195}
1196
1197bool
1198ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1199                                           SDValue &OffImm) {
1200  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1201}
1202
1203bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1204                                            SDValue &Base, SDValue &OffImm) {
1205  if (N.getOpcode() == ISD::FrameIndex) {
1206    int FI = cast<FrameIndexSDNode>(N)->getIndex();
1207    Base = CurDAG->getTargetFrameIndex(FI,
1208                                       getTargetLowering()->getPointerTy());
1209    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1210    return true;
1211  }
1212
1213  if (!CurDAG->isBaseWithConstantOffset(N))
1214    return false;
1215
1216  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1217  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1218      (LHSR && LHSR->getReg() == ARM::SP)) {
1219    // If the RHS is + imm8 * scale, fold into addr mode.
1220    int RHSC;
1221    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1222      Base = N.getOperand(0);
1223      if (Base.getOpcode() == ISD::FrameIndex) {
1224        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1225        Base = CurDAG->getTargetFrameIndex(FI,
1226                                           getTargetLowering()->getPointerTy());
1227      }
1228      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1229      return true;
1230    }
1231  }
1232
1233  return false;
1234}
1235
1236
1237//===----------------------------------------------------------------------===//
1238//                        Thumb 2 Addressing Modes
1239//===----------------------------------------------------------------------===//
1240
1241
1242bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1243                                                SDValue &Opc) {
1244  if (DisableShifterOp)
1245    return false;
1246
1247  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1248
1249  // Don't match base register only case. That is matched to a separate
1250  // lower complexity pattern with explicit register operand.
1251  if (ShOpcVal == ARM_AM::no_shift) return false;
1252
1253  BaseReg = N.getOperand(0);
1254  unsigned ShImmVal = 0;
1255  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1256    ShImmVal = RHS->getZExtValue() & 31;
1257    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1258    return true;
1259  }
1260
1261  return false;
1262}
1263
1264bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1265                                            SDValue &Base, SDValue &OffImm) {
1266  // Match simple R + imm12 operands.
1267
1268  // Base only.
1269  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1270      !CurDAG->isBaseWithConstantOffset(N)) {
1271    if (N.getOpcode() == ISD::FrameIndex) {
1272      // Match frame index.
1273      int FI = cast<FrameIndexSDNode>(N)->getIndex();
1274      Base = CurDAG->getTargetFrameIndex(FI,
1275                                         getTargetLowering()->getPointerTy());
1276      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1277      return true;
1278    }
1279
1280    if (N.getOpcode() == ARMISD::Wrapper &&
1281               !(Subtarget->useMovt() &&
1282                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1283      Base = N.getOperand(0);
1284      if (Base.getOpcode() == ISD::TargetConstantPool)
1285        return false;  // We want to select t2LDRpci instead.
1286    } else
1287      Base = N;
1288    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1289    return true;
1290  }
1291
1292  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1293    if (SelectT2AddrModeImm8(N, Base, OffImm))
1294      // Let t2LDRi8 handle (R - imm8).
1295      return false;
1296
1297    int RHSC = (int)RHS->getZExtValue();
1298    if (N.getOpcode() == ISD::SUB)
1299      RHSC = -RHSC;
1300
1301    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1302      Base   = N.getOperand(0);
1303      if (Base.getOpcode() == ISD::FrameIndex) {
1304        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1305        Base = CurDAG->getTargetFrameIndex(FI,
1306                                           getTargetLowering()->getPointerTy());
1307      }
1308      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1309      return true;
1310    }
1311  }
1312
1313  // Base only.
1314  Base = N;
1315  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1316  return true;
1317}
1318
1319bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1320                                           SDValue &Base, SDValue &OffImm) {
1321  // Match simple R - imm8 operands.
1322  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1323      !CurDAG->isBaseWithConstantOffset(N))
1324    return false;
1325
1326  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1327    int RHSC = (int)RHS->getSExtValue();
1328    if (N.getOpcode() == ISD::SUB)
1329      RHSC = -RHSC;
1330
1331    if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1332      Base = N.getOperand(0);
1333      if (Base.getOpcode() == ISD::FrameIndex) {
1334        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1335        Base = CurDAG->getTargetFrameIndex(FI,
1336                                           getTargetLowering()->getPointerTy());
1337      }
1338      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1339      return true;
1340    }
1341  }
1342
1343  return false;
1344}
1345
1346bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1347                                                 SDValue &OffImm){
1348  unsigned Opcode = Op->getOpcode();
1349  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1350    ? cast<LoadSDNode>(Op)->getAddressingMode()
1351    : cast<StoreSDNode>(Op)->getAddressingMode();
1352  int RHSC;
1353  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1354    OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1355      ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1356      : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1357    return true;
1358  }
1359
1360  return false;
1361}
1362
1363bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1364                                            SDValue &Base,
1365                                            SDValue &OffReg, SDValue &ShImm) {
1366  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1367  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1368    return false;
1369
1370  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1371  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1372    int RHSC = (int)RHS->getZExtValue();
1373    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1374      return false;
1375    else if (RHSC < 0 && RHSC >= -255) // 8 bits
1376      return false;
1377  }
1378
1379  // Look for (R + R) or (R + (R << [1,2,3])).
1380  unsigned ShAmt = 0;
1381  Base   = N.getOperand(0);
1382  OffReg = N.getOperand(1);
1383
1384  // Swap if it is ((R << c) + R).
1385  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1386  if (ShOpcVal != ARM_AM::lsl) {
1387    ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1388    if (ShOpcVal == ARM_AM::lsl)
1389      std::swap(Base, OffReg);
1390  }
1391
1392  if (ShOpcVal == ARM_AM::lsl) {
1393    // Check to see if the RHS of the shift is a constant, if not, we can't fold
1394    // it.
1395    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1396      ShAmt = Sh->getZExtValue();
1397      if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1398        OffReg = OffReg.getOperand(0);
1399      else {
1400        ShAmt = 0;
1401        ShOpcVal = ARM_AM::no_shift;
1402      }
1403    } else {
1404      ShOpcVal = ARM_AM::no_shift;
1405    }
1406  }
1407
1408  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1409
1410  return true;
1411}
1412
1413bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
1414                                                SDValue &OffImm) {
1415  // This *must* succeed since it's used for the irreplacable ldrex and strex
1416  // instructions.
1417  Base = N;
1418  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1419
1420  if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
1421    return true;
1422
1423  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1424  if (!RHS)
1425    return true;
1426
1427  uint32_t RHSC = (int)RHS->getZExtValue();
1428  if (RHSC > 1020 || RHSC % 4 != 0)
1429    return true;
1430
1431  Base = N.getOperand(0);
1432  if (Base.getOpcode() == ISD::FrameIndex) {
1433    int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1434    Base = CurDAG->getTargetFrameIndex(FI, getTargetLowering()->getPointerTy());
1435  }
1436
1437  OffImm = CurDAG->getTargetConstant(RHSC / 4, MVT::i32);
1438  return true;
1439}
1440
1441//===--------------------------------------------------------------------===//
1442
1443/// getAL - Returns a ARMCC::AL immediate node.
1444static inline SDValue getAL(SelectionDAG *CurDAG) {
1445  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1446}
1447
1448SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1449  LoadSDNode *LD = cast<LoadSDNode>(N);
1450  ISD::MemIndexedMode AM = LD->getAddressingMode();
1451  if (AM == ISD::UNINDEXED)
1452    return NULL;
1453
1454  EVT LoadedVT = LD->getMemoryVT();
1455  SDValue Offset, AMOpc;
1456  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1457  unsigned Opcode = 0;
1458  bool Match = false;
1459  if (LoadedVT == MVT::i32 && isPre &&
1460      SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1461    Opcode = ARM::LDR_PRE_IMM;
1462    Match = true;
1463  } else if (LoadedVT == MVT::i32 && !isPre &&
1464      SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1465    Opcode = ARM::LDR_POST_IMM;
1466    Match = true;
1467  } else if (LoadedVT == MVT::i32 &&
1468      SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1469    Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1470    Match = true;
1471
1472  } else if (LoadedVT == MVT::i16 &&
1473             SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1474    Match = true;
1475    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1476      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1477      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1478  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1479    if (LD->getExtensionType() == ISD::SEXTLOAD) {
1480      if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1481        Match = true;
1482        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1483      }
1484    } else {
1485      if (isPre &&
1486          SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1487        Match = true;
1488        Opcode = ARM::LDRB_PRE_IMM;
1489      } else if (!isPre &&
1490                  SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1491        Match = true;
1492        Opcode = ARM::LDRB_POST_IMM;
1493      } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1494        Match = true;
1495        Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1496      }
1497    }
1498  }
1499
1500  if (Match) {
1501    if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1502      SDValue Chain = LD->getChain();
1503      SDValue Base = LD->getBasePtr();
1504      SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1505                       CurDAG->getRegister(0, MVT::i32), Chain };
1506      return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1507                                    MVT::i32, MVT::Other, Ops);
1508    } else {
1509      SDValue Chain = LD->getChain();
1510      SDValue Base = LD->getBasePtr();
1511      SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1512                       CurDAG->getRegister(0, MVT::i32), Chain };
1513      return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1514                                    MVT::i32, MVT::Other, Ops);
1515    }
1516  }
1517
1518  return NULL;
1519}
1520
1521SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1522  LoadSDNode *LD = cast<LoadSDNode>(N);
1523  ISD::MemIndexedMode AM = LD->getAddressingMode();
1524  if (AM == ISD::UNINDEXED)
1525    return NULL;
1526
1527  EVT LoadedVT = LD->getMemoryVT();
1528  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1529  SDValue Offset;
1530  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1531  unsigned Opcode = 0;
1532  bool Match = false;
1533  if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1534    switch (LoadedVT.getSimpleVT().SimpleTy) {
1535    case MVT::i32:
1536      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1537      break;
1538    case MVT::i16:
1539      if (isSExtLd)
1540        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1541      else
1542        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1543      break;
1544    case MVT::i8:
1545    case MVT::i1:
1546      if (isSExtLd)
1547        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1548      else
1549        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1550      break;
1551    default:
1552      return NULL;
1553    }
1554    Match = true;
1555  }
1556
1557  if (Match) {
1558    SDValue Chain = LD->getChain();
1559    SDValue Base = LD->getBasePtr();
1560    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1561                     CurDAG->getRegister(0, MVT::i32), Chain };
1562    return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
1563                                  MVT::Other, Ops);
1564  }
1565
1566  return NULL;
1567}
1568
1569/// \brief Form a GPRPair pseudo register from a pair of GPR regs.
1570SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1571  SDLoc dl(V0.getNode());
1572  SDValue RegClass =
1573    CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);
1574  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
1575  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
1576  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1577  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1578}
1579
1580/// \brief Form a D register from a pair of S registers.
1581SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1582  SDLoc dl(V0.getNode());
1583  SDValue RegClass =
1584    CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1585  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1586  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1587  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1588  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1589}
1590
1591/// \brief Form a quad register from a pair of D registers.
1592SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1593  SDLoc dl(V0.getNode());
1594  SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1595  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1596  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1597  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1598  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1599}
1600
1601/// \brief Form 4 consecutive D registers from a pair of Q registers.
1602SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1603  SDLoc dl(V0.getNode());
1604  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1605  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1606  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1607  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1608  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1609}
1610
1611/// \brief Form 4 consecutive S registers.
1612SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1613                                   SDValue V2, SDValue V3) {
1614  SDLoc dl(V0.getNode());
1615  SDValue RegClass =
1616    CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1617  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1618  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1619  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1620  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1621  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1622                                    V2, SubReg2, V3, SubReg3 };
1623  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1624}
1625
1626/// \brief Form 4 consecutive D registers.
1627SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1628                                   SDValue V2, SDValue V3) {
1629  SDLoc dl(V0.getNode());
1630  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1631  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1632  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1633  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1634  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1635  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1636                                    V2, SubReg2, V3, SubReg3 };
1637  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1638}
1639
1640/// \brief Form 4 consecutive Q registers.
1641SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1642                                   SDValue V2, SDValue V3) {
1643  SDLoc dl(V0.getNode());
1644  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1645  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1646  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1647  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1648  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1649  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1650                                    V2, SubReg2, V3, SubReg3 };
1651  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1652}
1653
1654/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1655/// of a NEON VLD or VST instruction.  The supported values depend on the
1656/// number of registers being loaded.
1657SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1658                                       bool is64BitVector) {
1659  unsigned NumRegs = NumVecs;
1660  if (!is64BitVector && NumVecs < 3)
1661    NumRegs *= 2;
1662
1663  unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1664  if (Alignment >= 32 && NumRegs == 4)
1665    Alignment = 32;
1666  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1667    Alignment = 16;
1668  else if (Alignment >= 8)
1669    Alignment = 8;
1670  else
1671    Alignment = 0;
1672
1673  return CurDAG->getTargetConstant(Alignment, MVT::i32);
1674}
1675
1676// Get the register stride update opcode of a VLD/VST instruction that
1677// is otherwise equivalent to the given fixed stride updating instruction.
1678static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1679  switch (Opc) {
1680  default: break;
1681  case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1682  case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1683  case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1684  case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1685  case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1686  case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1687  case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1688  case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1689
1690  case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1691  case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1692  case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1693  case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1694  case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1695  case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1696  case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1697  case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1698  case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1699  case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1700
1701  case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1702  case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1703  case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1704  case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1705  case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1706  case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1707
1708  case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1709  case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1710  case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1711  case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1712  case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1713  case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1714
1715  case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1716  case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1717  case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1718  }
1719  return Opc; // If not one we handle, return it unchanged.
1720}
1721
1722SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1723                                   const uint16_t *DOpcodes,
1724                                   const uint16_t *QOpcodes0,
1725                                   const uint16_t *QOpcodes1) {
1726  assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1727  SDLoc dl(N);
1728
1729  SDValue MemAddr, Align;
1730  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1731  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1732    return NULL;
1733
1734  SDValue Chain = N->getOperand(0);
1735  EVT VT = N->getValueType(0);
1736  bool is64BitVector = VT.is64BitVector();
1737  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1738
1739  unsigned OpcodeIndex;
1740  switch (VT.getSimpleVT().SimpleTy) {
1741  default: llvm_unreachable("unhandled vld type");
1742    // Double-register operations:
1743  case MVT::v8i8:  OpcodeIndex = 0; break;
1744  case MVT::v4i16: OpcodeIndex = 1; break;
1745  case MVT::v2f32:
1746  case MVT::v2i32: OpcodeIndex = 2; break;
1747  case MVT::v1i64: OpcodeIndex = 3; break;
1748    // Quad-register operations:
1749  case MVT::v16i8: OpcodeIndex = 0; break;
1750  case MVT::v8i16: OpcodeIndex = 1; break;
1751  case MVT::v4f32:
1752  case MVT::v4i32: OpcodeIndex = 2; break;
1753  case MVT::v2i64: OpcodeIndex = 3;
1754    assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1755    break;
1756  }
1757
1758  EVT ResTy;
1759  if (NumVecs == 1)
1760    ResTy = VT;
1761  else {
1762    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1763    if (!is64BitVector)
1764      ResTyElts *= 2;
1765    ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1766  }
1767  std::vector<EVT> ResTys;
1768  ResTys.push_back(ResTy);
1769  if (isUpdating)
1770    ResTys.push_back(MVT::i32);
1771  ResTys.push_back(MVT::Other);
1772
1773  SDValue Pred = getAL(CurDAG);
1774  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1775  SDNode *VLd;
1776  SmallVector<SDValue, 7> Ops;
1777
1778  // Double registers and VLD1/VLD2 quad registers are directly supported.
1779  if (is64BitVector || NumVecs <= 2) {
1780    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1781                    QOpcodes0[OpcodeIndex]);
1782    Ops.push_back(MemAddr);
1783    Ops.push_back(Align);
1784    if (isUpdating) {
1785      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1786      // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1787      // case entirely when the rest are updated to that form, too.
1788      if ((NumVecs == 1 || NumVecs == 2) && !isa<ConstantSDNode>(Inc.getNode()))
1789        Opc = getVLDSTRegisterUpdateOpcode(Opc);
1790      // We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1791      // check for that explicitly too. Horribly hacky, but temporary.
1792      if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64wb_fixed) ||
1793          !isa<ConstantSDNode>(Inc.getNode()))
1794        Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1795    }
1796    Ops.push_back(Pred);
1797    Ops.push_back(Reg0);
1798    Ops.push_back(Chain);
1799    VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1800
1801  } else {
1802    // Otherwise, quad registers are loaded with two separate instructions,
1803    // where one loads the even registers and the other loads the odd registers.
1804    EVT AddrTy = MemAddr.getValueType();
1805
1806    // Load the even subregs.  This is always an updating load, so that it
1807    // provides the address to the second load for the odd subregs.
1808    SDValue ImplDef =
1809      SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1810    const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1811    SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1812                                          ResTy, AddrTy, MVT::Other, OpsA);
1813    Chain = SDValue(VLdA, 2);
1814
1815    // Load the odd subregs.
1816    Ops.push_back(SDValue(VLdA, 1));
1817    Ops.push_back(Align);
1818    if (isUpdating) {
1819      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1820      assert(isa<ConstantSDNode>(Inc.getNode()) &&
1821             "only constant post-increment update allowed for VLD3/4");
1822      (void)Inc;
1823      Ops.push_back(Reg0);
1824    }
1825    Ops.push_back(SDValue(VLdA, 0));
1826    Ops.push_back(Pred);
1827    Ops.push_back(Reg0);
1828    Ops.push_back(Chain);
1829    VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
1830  }
1831
1832  // Transfer memoperands.
1833  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1834  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1835  cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1836
1837  if (NumVecs == 1)
1838    return VLd;
1839
1840  // Extract out the subregisters.
1841  SDValue SuperReg = SDValue(VLd, 0);
1842  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1843         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1844  unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1845  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1846    ReplaceUses(SDValue(N, Vec),
1847                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1848  ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1849  if (isUpdating)
1850    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1851  return NULL;
1852}
1853
1854SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1855                                   const uint16_t *DOpcodes,
1856                                   const uint16_t *QOpcodes0,
1857                                   const uint16_t *QOpcodes1) {
1858  assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1859  SDLoc dl(N);
1860
1861  SDValue MemAddr, Align;
1862  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1863  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1864  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1865    return NULL;
1866
1867  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1868  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1869
1870  SDValue Chain = N->getOperand(0);
1871  EVT VT = N->getOperand(Vec0Idx).getValueType();
1872  bool is64BitVector = VT.is64BitVector();
1873  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1874
1875  unsigned OpcodeIndex;
1876  switch (VT.getSimpleVT().SimpleTy) {
1877  default: llvm_unreachable("unhandled vst type");
1878    // Double-register operations:
1879  case MVT::v8i8:  OpcodeIndex = 0; break;
1880  case MVT::v4i16: OpcodeIndex = 1; break;
1881  case MVT::v2f32:
1882  case MVT::v2i32: OpcodeIndex = 2; break;
1883  case MVT::v1i64: OpcodeIndex = 3; break;
1884    // Quad-register operations:
1885  case MVT::v16i8: OpcodeIndex = 0; break;
1886  case MVT::v8i16: OpcodeIndex = 1; break;
1887  case MVT::v4f32:
1888  case MVT::v4i32: OpcodeIndex = 2; break;
1889  case MVT::v2i64: OpcodeIndex = 3;
1890    assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1891    break;
1892  }
1893
1894  std::vector<EVT> ResTys;
1895  if (isUpdating)
1896    ResTys.push_back(MVT::i32);
1897  ResTys.push_back(MVT::Other);
1898
1899  SDValue Pred = getAL(CurDAG);
1900  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1901  SmallVector<SDValue, 7> Ops;
1902
1903  // Double registers and VST1/VST2 quad registers are directly supported.
1904  if (is64BitVector || NumVecs <= 2) {
1905    SDValue SrcReg;
1906    if (NumVecs == 1) {
1907      SrcReg = N->getOperand(Vec0Idx);
1908    } else if (is64BitVector) {
1909      // Form a REG_SEQUENCE to force register allocation.
1910      SDValue V0 = N->getOperand(Vec0Idx + 0);
1911      SDValue V1 = N->getOperand(Vec0Idx + 1);
1912      if (NumVecs == 2)
1913        SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
1914      else {
1915        SDValue V2 = N->getOperand(Vec0Idx + 2);
1916        // If it's a vst3, form a quad D-register and leave the last part as
1917        // an undef.
1918        SDValue V3 = (NumVecs == 3)
1919          ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1920          : N->getOperand(Vec0Idx + 3);
1921        SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
1922      }
1923    } else {
1924      // Form a QQ register.
1925      SDValue Q0 = N->getOperand(Vec0Idx);
1926      SDValue Q1 = N->getOperand(Vec0Idx + 1);
1927      SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
1928    }
1929
1930    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1931                    QOpcodes0[OpcodeIndex]);
1932    Ops.push_back(MemAddr);
1933    Ops.push_back(Align);
1934    if (isUpdating) {
1935      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1936      // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1937      // case entirely when the rest are updated to that form, too.
1938      if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1939        Opc = getVLDSTRegisterUpdateOpcode(Opc);
1940      // We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
1941      // check for that explicitly too. Horribly hacky, but temporary.
1942      if ((NumVecs > 2 && Opc != ARM::VST1q64wb_fixed) ||
1943          !isa<ConstantSDNode>(Inc.getNode()))
1944        Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1945    }
1946    Ops.push_back(SrcReg);
1947    Ops.push_back(Pred);
1948    Ops.push_back(Reg0);
1949    Ops.push_back(Chain);
1950    SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1951
1952    // Transfer memoperands.
1953    cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1954
1955    return VSt;
1956  }
1957
1958  // Otherwise, quad registers are stored with two separate instructions,
1959  // where one stores the even registers and the other stores the odd registers.
1960
1961  // Form the QQQQ REG_SEQUENCE.
1962  SDValue V0 = N->getOperand(Vec0Idx + 0);
1963  SDValue V1 = N->getOperand(Vec0Idx + 1);
1964  SDValue V2 = N->getOperand(Vec0Idx + 2);
1965  SDValue V3 = (NumVecs == 3)
1966    ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1967    : N->getOperand(Vec0Idx + 3);
1968  SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
1969
1970  // Store the even D registers.  This is always an updating store, so that it
1971  // provides the address to the second store for the odd subregs.
1972  const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1973  SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1974                                        MemAddr.getValueType(),
1975                                        MVT::Other, OpsA);
1976  cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1977  Chain = SDValue(VStA, 1);
1978
1979  // Store the odd D registers.
1980  Ops.push_back(SDValue(VStA, 0));
1981  Ops.push_back(Align);
1982  if (isUpdating) {
1983    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1984    assert(isa<ConstantSDNode>(Inc.getNode()) &&
1985           "only constant post-increment update allowed for VST3/4");
1986    (void)Inc;
1987    Ops.push_back(Reg0);
1988  }
1989  Ops.push_back(RegSeq);
1990  Ops.push_back(Pred);
1991  Ops.push_back(Reg0);
1992  Ops.push_back(Chain);
1993  SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1994                                        Ops);
1995  cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1996  return VStB;
1997}
1998
1999SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
2000                                         bool isUpdating, unsigned NumVecs,
2001                                         const uint16_t *DOpcodes,
2002                                         const uint16_t *QOpcodes) {
2003  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2004  SDLoc dl(N);
2005
2006  SDValue MemAddr, Align;
2007  unsigned AddrOpIdx = isUpdating ? 1 : 2;
2008  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
2009  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
2010    return NULL;
2011
2012  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2013  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2014
2015  SDValue Chain = N->getOperand(0);
2016  unsigned Lane =
2017    cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
2018  EVT VT = N->getOperand(Vec0Idx).getValueType();
2019  bool is64BitVector = VT.is64BitVector();
2020
2021  unsigned Alignment = 0;
2022  if (NumVecs != 3) {
2023    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2024    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2025    if (Alignment > NumBytes)
2026      Alignment = NumBytes;
2027    if (Alignment < 8 && Alignment < NumBytes)
2028      Alignment = 0;
2029    // Alignment must be a power of two; make sure of that.
2030    Alignment = (Alignment & -Alignment);
2031    if (Alignment == 1)
2032      Alignment = 0;
2033  }
2034  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2035
2036  unsigned OpcodeIndex;
2037  switch (VT.getSimpleVT().SimpleTy) {
2038  default: llvm_unreachable("unhandled vld/vst lane type");
2039    // Double-register operations:
2040  case MVT::v8i8:  OpcodeIndex = 0; break;
2041  case MVT::v4i16: OpcodeIndex = 1; break;
2042  case MVT::v2f32:
2043  case MVT::v2i32: OpcodeIndex = 2; break;
2044    // Quad-register operations:
2045  case MVT::v8i16: OpcodeIndex = 0; break;
2046  case MVT::v4f32:
2047  case MVT::v4i32: OpcodeIndex = 1; break;
2048  }
2049
2050  std::vector<EVT> ResTys;
2051  if (IsLoad) {
2052    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2053    if (!is64BitVector)
2054      ResTyElts *= 2;
2055    ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
2056                                      MVT::i64, ResTyElts));
2057  }
2058  if (isUpdating)
2059    ResTys.push_back(MVT::i32);
2060  ResTys.push_back(MVT::Other);
2061
2062  SDValue Pred = getAL(CurDAG);
2063  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2064
2065  SmallVector<SDValue, 8> Ops;
2066  Ops.push_back(MemAddr);
2067  Ops.push_back(Align);
2068  if (isUpdating) {
2069    SDValue Inc = N->getOperand(AddrOpIdx + 1);
2070    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2071  }
2072
2073  SDValue SuperReg;
2074  SDValue V0 = N->getOperand(Vec0Idx + 0);
2075  SDValue V1 = N->getOperand(Vec0Idx + 1);
2076  if (NumVecs == 2) {
2077    if (is64BitVector)
2078      SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2079    else
2080      SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2081  } else {
2082    SDValue V2 = N->getOperand(Vec0Idx + 2);
2083    SDValue V3 = (NumVecs == 3)
2084      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2085      : N->getOperand(Vec0Idx + 3);
2086    if (is64BitVector)
2087      SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2088    else
2089      SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2090  }
2091  Ops.push_back(SuperReg);
2092  Ops.push_back(getI32Imm(Lane));
2093  Ops.push_back(Pred);
2094  Ops.push_back(Reg0);
2095  Ops.push_back(Chain);
2096
2097  unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
2098                                  QOpcodes[OpcodeIndex]);
2099  SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2100  cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
2101  if (!IsLoad)
2102    return VLdLn;
2103
2104  // Extract the subregisters.
2105  SuperReg = SDValue(VLdLn, 0);
2106  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
2107         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
2108  unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2109  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2110    ReplaceUses(SDValue(N, Vec),
2111                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2112  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2113  if (isUpdating)
2114    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2115  return NULL;
2116}
2117
2118SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
2119                                      unsigned NumVecs,
2120                                      const uint16_t *Opcodes) {
2121  assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2122  SDLoc dl(N);
2123
2124  SDValue MemAddr, Align;
2125  if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2126    return NULL;
2127
2128  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2129  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2130
2131  SDValue Chain = N->getOperand(0);
2132  EVT VT = N->getValueType(0);
2133
2134  unsigned Alignment = 0;
2135  if (NumVecs != 3) {
2136    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2137    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2138    if (Alignment > NumBytes)
2139      Alignment = NumBytes;
2140    if (Alignment < 8 && Alignment < NumBytes)
2141      Alignment = 0;
2142    // Alignment must be a power of two; make sure of that.
2143    Alignment = (Alignment & -Alignment);
2144    if (Alignment == 1)
2145      Alignment = 0;
2146  }
2147  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2148
2149  unsigned OpcodeIndex;
2150  switch (VT.getSimpleVT().SimpleTy) {
2151  default: llvm_unreachable("unhandled vld-dup type");
2152  case MVT::v8i8:  OpcodeIndex = 0; break;
2153  case MVT::v4i16: OpcodeIndex = 1; break;
2154  case MVT::v2f32:
2155  case MVT::v2i32: OpcodeIndex = 2; break;
2156  }
2157
2158  SDValue Pred = getAL(CurDAG);
2159  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2160  SDValue SuperReg;
2161  unsigned Opc = Opcodes[OpcodeIndex];
2162  SmallVector<SDValue, 6> Ops;
2163  Ops.push_back(MemAddr);
2164  Ops.push_back(Align);
2165  if (isUpdating) {
2166    // fixed-stride update instructions don't have an explicit writeback
2167    // operand. It's implicit in the opcode itself.
2168    SDValue Inc = N->getOperand(2);
2169    if (!isa<ConstantSDNode>(Inc.getNode()))
2170      Ops.push_back(Inc);
2171    // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2172    else if (NumVecs > 2)
2173      Ops.push_back(Reg0);
2174  }
2175  Ops.push_back(Pred);
2176  Ops.push_back(Reg0);
2177  Ops.push_back(Chain);
2178
2179  unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2180  std::vector<EVT> ResTys;
2181  ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2182  if (isUpdating)
2183    ResTys.push_back(MVT::i32);
2184  ResTys.push_back(MVT::Other);
2185  SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2186  cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2187  SuperReg = SDValue(VLdDup, 0);
2188
2189  // Extract the subregisters.
2190  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2191  unsigned SubIdx = ARM::dsub_0;
2192  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2193    ReplaceUses(SDValue(N, Vec),
2194                CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2195  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2196  if (isUpdating)
2197    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2198  return NULL;
2199}
2200
2201SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2202                                    unsigned Opc) {
2203  assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2204  SDLoc dl(N);
2205  EVT VT = N->getValueType(0);
2206  unsigned FirstTblReg = IsExt ? 2 : 1;
2207
2208  // Form a REG_SEQUENCE to force register allocation.
2209  SDValue RegSeq;
2210  SDValue V0 = N->getOperand(FirstTblReg + 0);
2211  SDValue V1 = N->getOperand(FirstTblReg + 1);
2212  if (NumVecs == 2)
2213    RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
2214  else {
2215    SDValue V2 = N->getOperand(FirstTblReg + 2);
2216    // If it's a vtbl3, form a quad D-register and leave the last part as
2217    // an undef.
2218    SDValue V3 = (NumVecs == 3)
2219      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2220      : N->getOperand(FirstTblReg + 3);
2221    RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2222  }
2223
2224  SmallVector<SDValue, 6> Ops;
2225  if (IsExt)
2226    Ops.push_back(N->getOperand(1));
2227  Ops.push_back(RegSeq);
2228  Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2229  Ops.push_back(getAL(CurDAG)); // predicate
2230  Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2231  return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2232}
2233
2234SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2235                                                     bool isSigned) {
2236  if (!Subtarget->hasV6T2Ops())
2237    return NULL;
2238
2239  unsigned Opc = isSigned
2240    ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2241    : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2242
2243  // For unsigned extracts, check for a shift right and mask
2244  unsigned And_imm = 0;
2245  if (N->getOpcode() == ISD::AND) {
2246    if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2247
2248      // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2249      if (And_imm & (And_imm + 1))
2250        return NULL;
2251
2252      unsigned Srl_imm = 0;
2253      if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2254                                Srl_imm)) {
2255        assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2256
2257        // Note: The width operand is encoded as width-1.
2258        unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2259        unsigned LSB = Srl_imm;
2260
2261        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2262
2263        if ((LSB + Width + 1) == N->getValueType(0).getSizeInBits()) {
2264          // It's cheaper to use a right shift to extract the top bits.
2265          if (Subtarget->isThumb()) {
2266            Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
2267            SDValue Ops[] = { N->getOperand(0).getOperand(0),
2268                              CurDAG->getTargetConstant(LSB, MVT::i32),
2269                              getAL(CurDAG), Reg0, Reg0 };
2270            return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2271          }
2272
2273          // ARM models shift instructions as MOVsi with shifter operand.
2274          ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
2275          SDValue ShOpc =
2276            CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, LSB),
2277                                      MVT::i32);
2278          SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
2279                            getAL(CurDAG), Reg0, Reg0 };
2280          return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops, 5);
2281        }
2282
2283        SDValue Ops[] = { N->getOperand(0).getOperand(0),
2284                          CurDAG->getTargetConstant(LSB, MVT::i32),
2285                          CurDAG->getTargetConstant(Width, MVT::i32),
2286          getAL(CurDAG), Reg0 };
2287        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2288      }
2289    }
2290    return NULL;
2291  }
2292
2293  // Otherwise, we're looking for a shift of a shift
2294  unsigned Shl_imm = 0;
2295  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2296    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2297    unsigned Srl_imm = 0;
2298    if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2299      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2300      // Note: The width operand is encoded as width-1.
2301      unsigned Width = 32 - Srl_imm - 1;
2302      int LSB = Srl_imm - Shl_imm;
2303      if (LSB < 0)
2304        return NULL;
2305      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2306      SDValue Ops[] = { N->getOperand(0).getOperand(0),
2307                        CurDAG->getTargetConstant(LSB, MVT::i32),
2308                        CurDAG->getTargetConstant(Width, MVT::i32),
2309                        getAL(CurDAG), Reg0 };
2310      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2311    }
2312  }
2313  return NULL;
2314}
2315
2316/// Target-specific DAG combining for ISD::XOR.
2317/// Target-independent combining lowers SELECT_CC nodes of the form
2318/// select_cc setg[ge] X,  0,  X, -X
2319/// select_cc setgt    X, -1,  X, -X
2320/// select_cc setl[te] X,  0, -X,  X
2321/// select_cc setlt    X,  1, -X,  X
2322/// which represent Integer ABS into:
2323/// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2324/// ARM instruction selection detects the latter and matches it to
2325/// ARM::ABS or ARM::t2ABS machine node.
2326SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2327  SDValue XORSrc0 = N->getOperand(0);
2328  SDValue XORSrc1 = N->getOperand(1);
2329  EVT VT = N->getValueType(0);
2330
2331  if (Subtarget->isThumb1Only())
2332    return NULL;
2333
2334  if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2335    return NULL;
2336
2337  SDValue ADDSrc0 = XORSrc0.getOperand(0);
2338  SDValue ADDSrc1 = XORSrc0.getOperand(1);
2339  SDValue SRASrc0 = XORSrc1.getOperand(0);
2340  SDValue SRASrc1 = XORSrc1.getOperand(1);
2341  ConstantSDNode *SRAConstant =  dyn_cast<ConstantSDNode>(SRASrc1);
2342  EVT XType = SRASrc0.getValueType();
2343  unsigned Size = XType.getSizeInBits() - 1;
2344
2345  if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2346      XType.isInteger() && SRAConstant != NULL &&
2347      Size == SRAConstant->getZExtValue()) {
2348    unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2349    return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2350  }
2351
2352  return NULL;
2353}
2354
2355SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2356  // The only time a CONCAT_VECTORS operation can have legal types is when
2357  // two 64-bit vectors are concatenated to a 128-bit vector.
2358  EVT VT = N->getValueType(0);
2359  if (!VT.is128BitVector() || N->getNumOperands() != 2)
2360    llvm_unreachable("unexpected CONCAT_VECTORS");
2361  return createDRegPairNode(VT, N->getOperand(0), N->getOperand(1));
2362}
2363
2364SDNode *ARMDAGToDAGISel::SelectAtomic(SDNode *Node, unsigned Op8,
2365                                      unsigned Op16,unsigned Op32,
2366                                      unsigned Op64) {
2367  // Mostly direct translation to the given operations, except that we preserve
2368  // the AtomicOrdering for use later on.
2369  AtomicSDNode *AN = cast<AtomicSDNode>(Node);
2370  EVT VT = AN->getMemoryVT();
2371
2372  unsigned Op;
2373  SDVTList VTs = CurDAG->getVTList(AN->getValueType(0), MVT::Other);
2374  if (VT == MVT::i8)
2375    Op = Op8;
2376  else if (VT == MVT::i16)
2377    Op = Op16;
2378  else if (VT == MVT::i32)
2379    Op = Op32;
2380  else if (VT == MVT::i64) {
2381    Op = Op64;
2382    VTs = CurDAG->getVTList(MVT::i32, MVT::i32, MVT::Other);
2383  } else
2384    llvm_unreachable("Unexpected atomic operation");
2385
2386  SmallVector<SDValue, 6> Ops;
2387  for (unsigned i = 1; i < AN->getNumOperands(); ++i)
2388      Ops.push_back(AN->getOperand(i));
2389
2390  Ops.push_back(CurDAG->getTargetConstant(AN->getOrdering(), MVT::i32));
2391  Ops.push_back(AN->getOperand(0)); // Chain moves to the end
2392
2393  return CurDAG->SelectNodeTo(Node, Op, VTs, &Ops[0], Ops.size());
2394}
2395
2396SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2397  SDLoc dl(N);
2398
2399  if (N->isMachineOpcode()) {
2400    N->setNodeId(-1);
2401    return NULL;   // Already selected.
2402  }
2403
2404  switch (N->getOpcode()) {
2405  default: break;
2406  case ISD::INLINEASM: {
2407    SDNode *ResNode = SelectInlineAsm(N);
2408    if (ResNode)
2409      return ResNode;
2410    break;
2411  }
2412  case ISD::XOR: {
2413    // Select special operations if XOR node forms integer ABS pattern
2414    SDNode *ResNode = SelectABSOp(N);
2415    if (ResNode)
2416      return ResNode;
2417    // Other cases are autogenerated.
2418    break;
2419  }
2420  case ISD::Constant: {
2421    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2422    bool UseCP = true;
2423    if (Subtarget->hasThumb2())
2424      // Thumb2-aware targets have the MOVT instruction, so all immediates can
2425      // be done with MOV + MOVT, at worst.
2426      UseCP = 0;
2427    else {
2428      if (Subtarget->isThumb()) {
2429        UseCP = (Val > 255 &&                          // MOV
2430                 ~Val > 255 &&                         // MOV + MVN
2431                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
2432      } else
2433        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
2434                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
2435                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
2436    }
2437
2438    if (UseCP) {
2439      SDValue CPIdx =
2440        CurDAG->getTargetConstantPool(ConstantInt::get(
2441                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
2442                                      getTargetLowering()->getPointerTy());
2443
2444      SDNode *ResNode;
2445      if (Subtarget->isThumb1Only()) {
2446        SDValue Pred = getAL(CurDAG);
2447        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2448        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2449        ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2450                                         Ops);
2451      } else {
2452        SDValue Ops[] = {
2453          CPIdx,
2454          CurDAG->getTargetConstant(0, MVT::i32),
2455          getAL(CurDAG),
2456          CurDAG->getRegister(0, MVT::i32),
2457          CurDAG->getEntryNode()
2458        };
2459        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2460                                       Ops);
2461      }
2462      ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2463      return NULL;
2464    }
2465
2466    // Other cases are autogenerated.
2467    break;
2468  }
2469  case ISD::FrameIndex: {
2470    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2471    int FI = cast<FrameIndexSDNode>(N)->getIndex();
2472    SDValue TFI = CurDAG->getTargetFrameIndex(FI,
2473                                           getTargetLowering()->getPointerTy());
2474    if (Subtarget->isThumb1Only()) {
2475      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2476                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2477      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2478    } else {
2479      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2480                      ARM::t2ADDri : ARM::ADDri);
2481      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2482                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2483                        CurDAG->getRegister(0, MVT::i32) };
2484      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2485    }
2486  }
2487  case ISD::SRL:
2488    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2489      return I;
2490    break;
2491  case ISD::SRA:
2492    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2493      return I;
2494    break;
2495  case ISD::MUL:
2496    if (Subtarget->isThumb1Only())
2497      break;
2498    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2499      unsigned RHSV = C->getZExtValue();
2500      if (!RHSV) break;
2501      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
2502        unsigned ShImm = Log2_32(RHSV-1);
2503        if (ShImm >= 32)
2504          break;
2505        SDValue V = N->getOperand(0);
2506        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2507        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2508        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2509        if (Subtarget->isThumb()) {
2510          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2511          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2512        } else {
2513          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2514          return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2515        }
2516      }
2517      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
2518        unsigned ShImm = Log2_32(RHSV+1);
2519        if (ShImm >= 32)
2520          break;
2521        SDValue V = N->getOperand(0);
2522        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2523        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2524        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2525        if (Subtarget->isThumb()) {
2526          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2527          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2528        } else {
2529          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2530          return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2531        }
2532      }
2533    }
2534    break;
2535  case ISD::AND: {
2536    // Check for unsigned bitfield extract
2537    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2538      return I;
2539
2540    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2541    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2542    // are entirely contributed by c2 and lower 16-bits are entirely contributed
2543    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2544    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2545    EVT VT = N->getValueType(0);
2546    if (VT != MVT::i32)
2547      break;
2548    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2549      ? ARM::t2MOVTi16
2550      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2551    if (!Opc)
2552      break;
2553    SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2554    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2555    if (!N1C)
2556      break;
2557    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2558      SDValue N2 = N0.getOperand(1);
2559      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2560      if (!N2C)
2561        break;
2562      unsigned N1CVal = N1C->getZExtValue();
2563      unsigned N2CVal = N2C->getZExtValue();
2564      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2565          (N1CVal & 0xffffU) == 0xffffU &&
2566          (N2CVal & 0xffffU) == 0x0U) {
2567        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2568                                                  MVT::i32);
2569        SDValue Ops[] = { N0.getOperand(0), Imm16,
2570                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2571        return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2572      }
2573    }
2574    break;
2575  }
2576  case ARMISD::VMOVRRD:
2577    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2578                                  N->getOperand(0), getAL(CurDAG),
2579                                  CurDAG->getRegister(0, MVT::i32));
2580  case ISD::UMUL_LOHI: {
2581    if (Subtarget->isThumb1Only())
2582      break;
2583    if (Subtarget->isThumb()) {
2584      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2585                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2586      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
2587    } else {
2588      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2589                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2590                        CurDAG->getRegister(0, MVT::i32) };
2591      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2592                                    ARM::UMULL : ARM::UMULLv5,
2593                                    dl, MVT::i32, MVT::i32, Ops);
2594    }
2595  }
2596  case ISD::SMUL_LOHI: {
2597    if (Subtarget->isThumb1Only())
2598      break;
2599    if (Subtarget->isThumb()) {
2600      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2601                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2602      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
2603    } else {
2604      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2605                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2606                        CurDAG->getRegister(0, MVT::i32) };
2607      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2608                                    ARM::SMULL : ARM::SMULLv5,
2609                                    dl, MVT::i32, MVT::i32, Ops);
2610    }
2611  }
2612  case ARMISD::UMLAL:{
2613    if (Subtarget->isThumb()) {
2614      SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2615                        N->getOperand(3), getAL(CurDAG),
2616                        CurDAG->getRegister(0, MVT::i32)};
2617      return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
2618    }else{
2619      SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2620                        N->getOperand(3), getAL(CurDAG),
2621                        CurDAG->getRegister(0, MVT::i32),
2622                        CurDAG->getRegister(0, MVT::i32) };
2623      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2624                                      ARM::UMLAL : ARM::UMLALv5,
2625                                      dl, MVT::i32, MVT::i32, Ops);
2626    }
2627  }
2628  case ARMISD::SMLAL:{
2629    if (Subtarget->isThumb()) {
2630      SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2631                        N->getOperand(3), getAL(CurDAG),
2632                        CurDAG->getRegister(0, MVT::i32)};
2633      return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
2634    }else{
2635      SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2636                        N->getOperand(3), getAL(CurDAG),
2637                        CurDAG->getRegister(0, MVT::i32),
2638                        CurDAG->getRegister(0, MVT::i32) };
2639      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2640                                      ARM::SMLAL : ARM::SMLALv5,
2641                                      dl, MVT::i32, MVT::i32, Ops);
2642    }
2643  }
2644  case ISD::LOAD: {
2645    SDNode *ResNode = 0;
2646    if (Subtarget->isThumb() && Subtarget->hasThumb2())
2647      ResNode = SelectT2IndexedLoad(N);
2648    else
2649      ResNode = SelectARMIndexedLoad(N);
2650    if (ResNode)
2651      return ResNode;
2652    // Other cases are autogenerated.
2653    break;
2654  }
2655  case ARMISD::BRCOND: {
2656    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2657    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2658    // Pattern complexity = 6  cost = 1  size = 0
2659
2660    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2661    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2662    // Pattern complexity = 6  cost = 1  size = 0
2663
2664    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2665    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2666    // Pattern complexity = 6  cost = 1  size = 0
2667
2668    unsigned Opc = Subtarget->isThumb() ?
2669      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2670    SDValue Chain = N->getOperand(0);
2671    SDValue N1 = N->getOperand(1);
2672    SDValue N2 = N->getOperand(2);
2673    SDValue N3 = N->getOperand(3);
2674    SDValue InFlag = N->getOperand(4);
2675    assert(N1.getOpcode() == ISD::BasicBlock);
2676    assert(N2.getOpcode() == ISD::Constant);
2677    assert(N3.getOpcode() == ISD::Register);
2678
2679    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2680                               cast<ConstantSDNode>(N2)->getZExtValue()),
2681                               MVT::i32);
2682    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2683    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2684                                             MVT::Glue, Ops);
2685    Chain = SDValue(ResNode, 0);
2686    if (N->getNumValues() == 2) {
2687      InFlag = SDValue(ResNode, 1);
2688      ReplaceUses(SDValue(N, 1), InFlag);
2689    }
2690    ReplaceUses(SDValue(N, 0),
2691                SDValue(Chain.getNode(), Chain.getResNo()));
2692    return NULL;
2693  }
2694  case ARMISD::VZIP: {
2695    unsigned Opc = 0;
2696    EVT VT = N->getValueType(0);
2697    switch (VT.getSimpleVT().SimpleTy) {
2698    default: return NULL;
2699    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
2700    case MVT::v4i16: Opc = ARM::VZIPd16; break;
2701    case MVT::v2f32:
2702    // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2703    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2704    case MVT::v16i8: Opc = ARM::VZIPq8; break;
2705    case MVT::v8i16: Opc = ARM::VZIPq16; break;
2706    case MVT::v4f32:
2707    case MVT::v4i32: Opc = ARM::VZIPq32; break;
2708    }
2709    SDValue Pred = getAL(CurDAG);
2710    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2711    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2712    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2713  }
2714  case ARMISD::VUZP: {
2715    unsigned Opc = 0;
2716    EVT VT = N->getValueType(0);
2717    switch (VT.getSimpleVT().SimpleTy) {
2718    default: return NULL;
2719    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
2720    case MVT::v4i16: Opc = ARM::VUZPd16; break;
2721    case MVT::v2f32:
2722    // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2723    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2724    case MVT::v16i8: Opc = ARM::VUZPq8; break;
2725    case MVT::v8i16: Opc = ARM::VUZPq16; break;
2726    case MVT::v4f32:
2727    case MVT::v4i32: Opc = ARM::VUZPq32; break;
2728    }
2729    SDValue Pred = getAL(CurDAG);
2730    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2731    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2732    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2733  }
2734  case ARMISD::VTRN: {
2735    unsigned Opc = 0;
2736    EVT VT = N->getValueType(0);
2737    switch (VT.getSimpleVT().SimpleTy) {
2738    default: return NULL;
2739    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
2740    case MVT::v4i16: Opc = ARM::VTRNd16; break;
2741    case MVT::v2f32:
2742    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2743    case MVT::v16i8: Opc = ARM::VTRNq8; break;
2744    case MVT::v8i16: Opc = ARM::VTRNq16; break;
2745    case MVT::v4f32:
2746    case MVT::v4i32: Opc = ARM::VTRNq32; break;
2747    }
2748    SDValue Pred = getAL(CurDAG);
2749    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2750    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2751    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2752  }
2753  case ARMISD::BUILD_VECTOR: {
2754    EVT VecVT = N->getValueType(0);
2755    EVT EltVT = VecVT.getVectorElementType();
2756    unsigned NumElts = VecVT.getVectorNumElements();
2757    if (EltVT == MVT::f64) {
2758      assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2759      return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2760    }
2761    assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2762    if (NumElts == 2)
2763      return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2764    assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2765    return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
2766                     N->getOperand(2), N->getOperand(3));
2767  }
2768
2769  case ARMISD::VLD2DUP: {
2770    static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2771                                        ARM::VLD2DUPd32 };
2772    return SelectVLDDup(N, false, 2, Opcodes);
2773  }
2774
2775  case ARMISD::VLD3DUP: {
2776    static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
2777                                        ARM::VLD3DUPd16Pseudo,
2778                                        ARM::VLD3DUPd32Pseudo };
2779    return SelectVLDDup(N, false, 3, Opcodes);
2780  }
2781
2782  case ARMISD::VLD4DUP: {
2783    static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
2784                                        ARM::VLD4DUPd16Pseudo,
2785                                        ARM::VLD4DUPd32Pseudo };
2786    return SelectVLDDup(N, false, 4, Opcodes);
2787  }
2788
2789  case ARMISD::VLD2DUP_UPD: {
2790    static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
2791                                        ARM::VLD2DUPd16wb_fixed,
2792                                        ARM::VLD2DUPd32wb_fixed };
2793    return SelectVLDDup(N, true, 2, Opcodes);
2794  }
2795
2796  case ARMISD::VLD3DUP_UPD: {
2797    static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
2798                                        ARM::VLD3DUPd16Pseudo_UPD,
2799                                        ARM::VLD3DUPd32Pseudo_UPD };
2800    return SelectVLDDup(N, true, 3, Opcodes);
2801  }
2802
2803  case ARMISD::VLD4DUP_UPD: {
2804    static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
2805                                        ARM::VLD4DUPd16Pseudo_UPD,
2806                                        ARM::VLD4DUPd32Pseudo_UPD };
2807    return SelectVLDDup(N, true, 4, Opcodes);
2808  }
2809
2810  case ARMISD::VLD1_UPD: {
2811    static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
2812                                         ARM::VLD1d16wb_fixed,
2813                                         ARM::VLD1d32wb_fixed,
2814                                         ARM::VLD1d64wb_fixed };
2815    static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
2816                                         ARM::VLD1q16wb_fixed,
2817                                         ARM::VLD1q32wb_fixed,
2818                                         ARM::VLD1q64wb_fixed };
2819    return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2820  }
2821
2822  case ARMISD::VLD2_UPD: {
2823    static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
2824                                         ARM::VLD2d16wb_fixed,
2825                                         ARM::VLD2d32wb_fixed,
2826                                         ARM::VLD1q64wb_fixed};
2827    static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2828                                         ARM::VLD2q16PseudoWB_fixed,
2829                                         ARM::VLD2q32PseudoWB_fixed };
2830    return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2831  }
2832
2833  case ARMISD::VLD3_UPD: {
2834    static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
2835                                         ARM::VLD3d16Pseudo_UPD,
2836                                         ARM::VLD3d32Pseudo_UPD,
2837                                         ARM::VLD1q64wb_fixed};
2838    static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2839                                          ARM::VLD3q16Pseudo_UPD,
2840                                          ARM::VLD3q32Pseudo_UPD };
2841    static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2842                                          ARM::VLD3q16oddPseudo_UPD,
2843                                          ARM::VLD3q32oddPseudo_UPD };
2844    return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2845  }
2846
2847  case ARMISD::VLD4_UPD: {
2848    static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
2849                                         ARM::VLD4d16Pseudo_UPD,
2850                                         ARM::VLD4d32Pseudo_UPD,
2851                                         ARM::VLD1q64wb_fixed};
2852    static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2853                                          ARM::VLD4q16Pseudo_UPD,
2854                                          ARM::VLD4q32Pseudo_UPD };
2855    static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2856                                          ARM::VLD4q16oddPseudo_UPD,
2857                                          ARM::VLD4q32oddPseudo_UPD };
2858    return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2859  }
2860
2861  case ARMISD::VLD2LN_UPD: {
2862    static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
2863                                         ARM::VLD2LNd16Pseudo_UPD,
2864                                         ARM::VLD2LNd32Pseudo_UPD };
2865    static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2866                                         ARM::VLD2LNq32Pseudo_UPD };
2867    return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2868  }
2869
2870  case ARMISD::VLD3LN_UPD: {
2871    static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
2872                                         ARM::VLD3LNd16Pseudo_UPD,
2873                                         ARM::VLD3LNd32Pseudo_UPD };
2874    static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2875                                         ARM::VLD3LNq32Pseudo_UPD };
2876    return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2877  }
2878
2879  case ARMISD::VLD4LN_UPD: {
2880    static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
2881                                         ARM::VLD4LNd16Pseudo_UPD,
2882                                         ARM::VLD4LNd32Pseudo_UPD };
2883    static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2884                                         ARM::VLD4LNq32Pseudo_UPD };
2885    return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2886  }
2887
2888  case ARMISD::VST1_UPD: {
2889    static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
2890                                         ARM::VST1d16wb_fixed,
2891                                         ARM::VST1d32wb_fixed,
2892                                         ARM::VST1d64wb_fixed };
2893    static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
2894                                         ARM::VST1q16wb_fixed,
2895                                         ARM::VST1q32wb_fixed,
2896                                         ARM::VST1q64wb_fixed };
2897    return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2898  }
2899
2900  case ARMISD::VST2_UPD: {
2901    static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
2902                                         ARM::VST2d16wb_fixed,
2903                                         ARM::VST2d32wb_fixed,
2904                                         ARM::VST1q64wb_fixed};
2905    static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
2906                                         ARM::VST2q16PseudoWB_fixed,
2907                                         ARM::VST2q32PseudoWB_fixed };
2908    return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2909  }
2910
2911  case ARMISD::VST3_UPD: {
2912    static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
2913                                         ARM::VST3d16Pseudo_UPD,
2914                                         ARM::VST3d32Pseudo_UPD,
2915                                         ARM::VST1d64TPseudoWB_fixed};
2916    static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2917                                          ARM::VST3q16Pseudo_UPD,
2918                                          ARM::VST3q32Pseudo_UPD };
2919    static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2920                                          ARM::VST3q16oddPseudo_UPD,
2921                                          ARM::VST3q32oddPseudo_UPD };
2922    return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2923  }
2924
2925  case ARMISD::VST4_UPD: {
2926    static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
2927                                         ARM::VST4d16Pseudo_UPD,
2928                                         ARM::VST4d32Pseudo_UPD,
2929                                         ARM::VST1d64QPseudoWB_fixed};
2930    static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2931                                          ARM::VST4q16Pseudo_UPD,
2932                                          ARM::VST4q32Pseudo_UPD };
2933    static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2934                                          ARM::VST4q16oddPseudo_UPD,
2935                                          ARM::VST4q32oddPseudo_UPD };
2936    return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2937  }
2938
2939  case ARMISD::VST2LN_UPD: {
2940    static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
2941                                         ARM::VST2LNd16Pseudo_UPD,
2942                                         ARM::VST2LNd32Pseudo_UPD };
2943    static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2944                                         ARM::VST2LNq32Pseudo_UPD };
2945    return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2946  }
2947
2948  case ARMISD::VST3LN_UPD: {
2949    static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
2950                                         ARM::VST3LNd16Pseudo_UPD,
2951                                         ARM::VST3LNd32Pseudo_UPD };
2952    static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2953                                         ARM::VST3LNq32Pseudo_UPD };
2954    return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2955  }
2956
2957  case ARMISD::VST4LN_UPD: {
2958    static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
2959                                         ARM::VST4LNd16Pseudo_UPD,
2960                                         ARM::VST4LNd32Pseudo_UPD };
2961    static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2962                                         ARM::VST4LNq32Pseudo_UPD };
2963    return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2964  }
2965
2966  case ISD::INTRINSIC_VOID:
2967  case ISD::INTRINSIC_W_CHAIN: {
2968    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2969    switch (IntNo) {
2970    default:
2971      break;
2972
2973    case Intrinsic::arm_ldrexd: {
2974      SDValue MemAddr = N->getOperand(2);
2975      SDLoc dl(N);
2976      SDValue Chain = N->getOperand(0);
2977
2978      bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
2979      unsigned NewOpc = isThumb ? ARM::t2LDREXD :ARM::LDREXD;
2980
2981      // arm_ldrexd returns a i64 value in {i32, i32}
2982      std::vector<EVT> ResTys;
2983      if (isThumb) {
2984        ResTys.push_back(MVT::i32);
2985        ResTys.push_back(MVT::i32);
2986      } else
2987        ResTys.push_back(MVT::Untyped);
2988      ResTys.push_back(MVT::Other);
2989
2990      // Place arguments in the right order.
2991      SmallVector<SDValue, 7> Ops;
2992      Ops.push_back(MemAddr);
2993      Ops.push_back(getAL(CurDAG));
2994      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2995      Ops.push_back(Chain);
2996      SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
2997      // Transfer memoperands.
2998      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2999      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3000      cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
3001
3002      // Remap uses.
3003      SDValue OutChain = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
3004      if (!SDValue(N, 0).use_empty()) {
3005        SDValue Result;
3006        if (isThumb)
3007          Result = SDValue(Ld, 0);
3008        else {
3009          SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
3010          SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3011              dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3012          Result = SDValue(ResNode,0);
3013        }
3014        ReplaceUses(SDValue(N, 0), Result);
3015      }
3016      if (!SDValue(N, 1).use_empty()) {
3017        SDValue Result;
3018        if (isThumb)
3019          Result = SDValue(Ld, 1);
3020        else {
3021          SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
3022          SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3023              dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3024          Result = SDValue(ResNode,0);
3025        }
3026        ReplaceUses(SDValue(N, 1), Result);
3027      }
3028      ReplaceUses(SDValue(N, 2), OutChain);
3029      return NULL;
3030    }
3031
3032    case Intrinsic::arm_strexd: {
3033      SDLoc dl(N);
3034      SDValue Chain = N->getOperand(0);
3035      SDValue Val0 = N->getOperand(2);
3036      SDValue Val1 = N->getOperand(3);
3037      SDValue MemAddr = N->getOperand(4);
3038
3039      // Store exclusive double return a i32 value which is the return status
3040      // of the issued store.
3041      EVT ResTys[] = { MVT::i32, MVT::Other };
3042
3043      bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3044      // Place arguments in the right order.
3045      SmallVector<SDValue, 7> Ops;
3046      if (isThumb) {
3047        Ops.push_back(Val0);
3048        Ops.push_back(Val1);
3049      } else
3050        // arm_strexd uses GPRPair.
3051        Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
3052      Ops.push_back(MemAddr);
3053      Ops.push_back(getAL(CurDAG));
3054      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3055      Ops.push_back(Chain);
3056
3057      unsigned NewOpc = isThumb ? ARM::t2STREXD : ARM::STREXD;
3058
3059      SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3060      // Transfer memoperands.
3061      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3062      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3063      cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3064
3065      return St;
3066    }
3067
3068    case Intrinsic::arm_neon_vld1: {
3069      static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3070                                           ARM::VLD1d32, ARM::VLD1d64 };
3071      static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3072                                           ARM::VLD1q32, ARM::VLD1q64};
3073      return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
3074    }
3075
3076    case Intrinsic::arm_neon_vld2: {
3077      static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3078                                           ARM::VLD2d32, ARM::VLD1q64 };
3079      static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3080                                           ARM::VLD2q32Pseudo };
3081      return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
3082    }
3083
3084    case Intrinsic::arm_neon_vld3: {
3085      static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
3086                                           ARM::VLD3d16Pseudo,
3087                                           ARM::VLD3d32Pseudo,
3088                                           ARM::VLD1d64TPseudo };
3089      static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3090                                            ARM::VLD3q16Pseudo_UPD,
3091                                            ARM::VLD3q32Pseudo_UPD };
3092      static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3093                                            ARM::VLD3q16oddPseudo,
3094                                            ARM::VLD3q32oddPseudo };
3095      return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3096    }
3097
3098    case Intrinsic::arm_neon_vld4: {
3099      static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
3100                                           ARM::VLD4d16Pseudo,
3101                                           ARM::VLD4d32Pseudo,
3102                                           ARM::VLD1d64QPseudo };
3103      static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3104                                            ARM::VLD4q16Pseudo_UPD,
3105                                            ARM::VLD4q32Pseudo_UPD };
3106      static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3107                                            ARM::VLD4q16oddPseudo,
3108                                            ARM::VLD4q32oddPseudo };
3109      return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3110    }
3111
3112    case Intrinsic::arm_neon_vld2lane: {
3113      static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
3114                                           ARM::VLD2LNd16Pseudo,
3115                                           ARM::VLD2LNd32Pseudo };
3116      static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
3117                                           ARM::VLD2LNq32Pseudo };
3118      return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3119    }
3120
3121    case Intrinsic::arm_neon_vld3lane: {
3122      static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
3123                                           ARM::VLD3LNd16Pseudo,
3124                                           ARM::VLD3LNd32Pseudo };
3125      static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
3126                                           ARM::VLD3LNq32Pseudo };
3127      return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3128    }
3129
3130    case Intrinsic::arm_neon_vld4lane: {
3131      static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
3132                                           ARM::VLD4LNd16Pseudo,
3133                                           ARM::VLD4LNd32Pseudo };
3134      static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
3135                                           ARM::VLD4LNq32Pseudo };
3136      return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3137    }
3138
3139    case Intrinsic::arm_neon_vst1: {
3140      static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3141                                           ARM::VST1d32, ARM::VST1d64 };
3142      static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3143                                           ARM::VST1q32, ARM::VST1q64 };
3144      return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3145    }
3146
3147    case Intrinsic::arm_neon_vst2: {
3148      static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3149                                           ARM::VST2d32, ARM::VST1q64 };
3150      static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3151                                     ARM::VST2q32Pseudo };
3152      return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3153    }
3154
3155    case Intrinsic::arm_neon_vst3: {
3156      static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
3157                                           ARM::VST3d16Pseudo,
3158                                           ARM::VST3d32Pseudo,
3159                                           ARM::VST1d64TPseudo };
3160      static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3161                                            ARM::VST3q16Pseudo_UPD,
3162                                            ARM::VST3q32Pseudo_UPD };
3163      static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
3164                                            ARM::VST3q16oddPseudo,
3165                                            ARM::VST3q32oddPseudo };
3166      return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3167    }
3168
3169    case Intrinsic::arm_neon_vst4: {
3170      static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
3171                                           ARM::VST4d16Pseudo,
3172                                           ARM::VST4d32Pseudo,
3173                                           ARM::VST1d64QPseudo };
3174      static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3175                                            ARM::VST4q16Pseudo_UPD,
3176                                            ARM::VST4q32Pseudo_UPD };
3177      static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
3178                                            ARM::VST4q16oddPseudo,
3179                                            ARM::VST4q32oddPseudo };
3180      return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3181    }
3182
3183    case Intrinsic::arm_neon_vst2lane: {
3184      static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
3185                                           ARM::VST2LNd16Pseudo,
3186                                           ARM::VST2LNd32Pseudo };
3187      static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
3188                                           ARM::VST2LNq32Pseudo };
3189      return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3190    }
3191
3192    case Intrinsic::arm_neon_vst3lane: {
3193      static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
3194                                           ARM::VST3LNd16Pseudo,
3195                                           ARM::VST3LNd32Pseudo };
3196      static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
3197                                           ARM::VST3LNq32Pseudo };
3198      return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3199    }
3200
3201    case Intrinsic::arm_neon_vst4lane: {
3202      static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
3203                                           ARM::VST4LNd16Pseudo,
3204                                           ARM::VST4LNd32Pseudo };
3205      static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
3206                                           ARM::VST4LNq32Pseudo };
3207      return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3208    }
3209    }
3210    break;
3211  }
3212
3213  case ISD::INTRINSIC_WO_CHAIN: {
3214    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3215    switch (IntNo) {
3216    default:
3217      break;
3218
3219    case Intrinsic::arm_neon_vtbl2:
3220      return SelectVTBL(N, false, 2, ARM::VTBL2);
3221    case Intrinsic::arm_neon_vtbl3:
3222      return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3223    case Intrinsic::arm_neon_vtbl4:
3224      return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3225
3226    case Intrinsic::arm_neon_vtbx2:
3227      return SelectVTBL(N, true, 2, ARM::VTBX2);
3228    case Intrinsic::arm_neon_vtbx3:
3229      return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3230    case Intrinsic::arm_neon_vtbx4:
3231      return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3232    }
3233    break;
3234  }
3235
3236  case ARMISD::VTBL1: {
3237    SDLoc dl(N);
3238    EVT VT = N->getValueType(0);
3239    SmallVector<SDValue, 6> Ops;
3240
3241    Ops.push_back(N->getOperand(0));
3242    Ops.push_back(N->getOperand(1));
3243    Ops.push_back(getAL(CurDAG));                    // Predicate
3244    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3245    return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
3246  }
3247  case ARMISD::VTBL2: {
3248    SDLoc dl(N);
3249    EVT VT = N->getValueType(0);
3250
3251    // Form a REG_SEQUENCE to force register allocation.
3252    SDValue V0 = N->getOperand(0);
3253    SDValue V1 = N->getOperand(1);
3254    SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
3255
3256    SmallVector<SDValue, 6> Ops;
3257    Ops.push_back(RegSeq);
3258    Ops.push_back(N->getOperand(2));
3259    Ops.push_back(getAL(CurDAG));                    // Predicate
3260    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3261    return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
3262  }
3263
3264  case ISD::CONCAT_VECTORS:
3265    return SelectConcatVector(N);
3266
3267  case ISD::ATOMIC_LOAD:
3268    if (cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64)
3269      return SelectAtomic(N, 0, 0, 0, ARM::ATOMIC_LOAD_I64);
3270    else
3271      break;
3272
3273  case ISD::ATOMIC_STORE:
3274    if (cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64)
3275      return SelectAtomic(N, 0, 0, 0, ARM::ATOMIC_STORE_I64);
3276    else
3277      break;
3278
3279  case ISD::ATOMIC_LOAD_ADD:
3280    return SelectAtomic(N,
3281                        ARM::ATOMIC_LOAD_ADD_I8,
3282                        ARM::ATOMIC_LOAD_ADD_I16,
3283                        ARM::ATOMIC_LOAD_ADD_I32,
3284                        ARM::ATOMIC_LOAD_ADD_I64);
3285  case ISD::ATOMIC_LOAD_SUB:
3286    return SelectAtomic(N,
3287                        ARM::ATOMIC_LOAD_SUB_I8,
3288                        ARM::ATOMIC_LOAD_SUB_I16,
3289                        ARM::ATOMIC_LOAD_SUB_I32,
3290                        ARM::ATOMIC_LOAD_SUB_I64);
3291  case ISD::ATOMIC_LOAD_AND:
3292    return SelectAtomic(N,
3293                        ARM::ATOMIC_LOAD_AND_I8,
3294                        ARM::ATOMIC_LOAD_AND_I16,
3295                        ARM::ATOMIC_LOAD_AND_I32,
3296                        ARM::ATOMIC_LOAD_AND_I64);
3297  case ISD::ATOMIC_LOAD_OR:
3298    return SelectAtomic(N,
3299                        ARM::ATOMIC_LOAD_OR_I8,
3300                        ARM::ATOMIC_LOAD_OR_I16,
3301                        ARM::ATOMIC_LOAD_OR_I32,
3302                        ARM::ATOMIC_LOAD_OR_I64);
3303  case ISD::ATOMIC_LOAD_XOR:
3304    return SelectAtomic(N,
3305                        ARM::ATOMIC_LOAD_XOR_I8,
3306                        ARM::ATOMIC_LOAD_XOR_I16,
3307                        ARM::ATOMIC_LOAD_XOR_I32,
3308                        ARM::ATOMIC_LOAD_XOR_I64);
3309  case ISD::ATOMIC_LOAD_NAND:
3310    return SelectAtomic(N,
3311                        ARM::ATOMIC_LOAD_NAND_I8,
3312                        ARM::ATOMIC_LOAD_NAND_I16,
3313                        ARM::ATOMIC_LOAD_NAND_I32,
3314                        ARM::ATOMIC_LOAD_NAND_I64);
3315  case ISD::ATOMIC_LOAD_MIN:
3316    return SelectAtomic(N,
3317                        ARM::ATOMIC_LOAD_MIN_I8,
3318                        ARM::ATOMIC_LOAD_MIN_I16,
3319                        ARM::ATOMIC_LOAD_MIN_I32,
3320                        ARM::ATOMIC_LOAD_MIN_I64);
3321  case ISD::ATOMIC_LOAD_MAX:
3322    return SelectAtomic(N,
3323                        ARM::ATOMIC_LOAD_MAX_I8,
3324                        ARM::ATOMIC_LOAD_MAX_I16,
3325                        ARM::ATOMIC_LOAD_MAX_I32,
3326                        ARM::ATOMIC_LOAD_MAX_I64);
3327  case ISD::ATOMIC_LOAD_UMIN:
3328    return SelectAtomic(N,
3329                        ARM::ATOMIC_LOAD_UMIN_I8,
3330                        ARM::ATOMIC_LOAD_UMIN_I16,
3331                        ARM::ATOMIC_LOAD_UMIN_I32,
3332                        ARM::ATOMIC_LOAD_UMIN_I64);
3333  case ISD::ATOMIC_LOAD_UMAX:
3334    return SelectAtomic(N,
3335                        ARM::ATOMIC_LOAD_UMAX_I8,
3336                        ARM::ATOMIC_LOAD_UMAX_I16,
3337                        ARM::ATOMIC_LOAD_UMAX_I32,
3338                        ARM::ATOMIC_LOAD_UMAX_I64);
3339  case ISD::ATOMIC_SWAP:
3340    return SelectAtomic(N,
3341                        ARM::ATOMIC_SWAP_I8,
3342                        ARM::ATOMIC_SWAP_I16,
3343                        ARM::ATOMIC_SWAP_I32,
3344                        ARM::ATOMIC_SWAP_I64);
3345  case ISD::ATOMIC_CMP_SWAP:
3346    return SelectAtomic(N,
3347                        ARM::ATOMIC_CMP_SWAP_I8,
3348                        ARM::ATOMIC_CMP_SWAP_I16,
3349                        ARM::ATOMIC_CMP_SWAP_I32,
3350                        ARM::ATOMIC_CMP_SWAP_I64);
3351  }
3352
3353  return SelectCode(N);
3354}
3355
3356SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
3357  std::vector<SDValue> AsmNodeOperands;
3358  unsigned Flag, Kind;
3359  bool Changed = false;
3360  unsigned NumOps = N->getNumOperands();
3361
3362  // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
3363  // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
3364  // (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
3365  // respectively. Since there is no constraint to explicitly specify a
3366  // reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
3367  // the 64-bit data may be referred by H, Q, R modifiers, so we still pack
3368  // them into a GPRPair.
3369
3370  SDLoc dl(N);
3371  SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1) : SDValue(0,0);
3372
3373  SmallVector<bool, 8> OpChanged;
3374  // Glue node will be appended late.
3375  for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
3376    SDValue op = N->getOperand(i);
3377    AsmNodeOperands.push_back(op);
3378
3379    if (i < InlineAsm::Op_FirstOperand)
3380      continue;
3381
3382    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
3383      Flag = C->getZExtValue();
3384      Kind = InlineAsm::getKind(Flag);
3385    }
3386    else
3387      continue;
3388
3389    // Immediate operands to inline asm in the SelectionDAG are modeled with
3390    // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
3391    // the second is a constant with the value of the immediate. If we get here
3392    // and we have a Kind_Imm, skip the next operand, and continue.
3393    if (Kind == InlineAsm::Kind_Imm) {
3394      SDValue op = N->getOperand(++i);
3395      AsmNodeOperands.push_back(op);
3396      continue;
3397    }
3398
3399    unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
3400    if (NumRegs)
3401      OpChanged.push_back(false);
3402
3403    unsigned DefIdx = 0;
3404    bool IsTiedToChangedOp = false;
3405    // If it's a use that is tied with a previous def, it has no
3406    // reg class constraint.
3407    if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
3408      IsTiedToChangedOp = OpChanged[DefIdx];
3409
3410    if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
3411        && Kind != InlineAsm::Kind_RegDefEarlyClobber)
3412      continue;
3413
3414    unsigned RC;
3415    bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
3416    if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
3417        || NumRegs != 2)
3418      continue;
3419
3420    assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
3421    SDValue V0 = N->getOperand(i+1);
3422    SDValue V1 = N->getOperand(i+2);
3423    unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
3424    unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
3425    SDValue PairedReg;
3426    MachineRegisterInfo &MRI = MF->getRegInfo();
3427
3428    if (Kind == InlineAsm::Kind_RegDef ||
3429        Kind == InlineAsm::Kind_RegDefEarlyClobber) {
3430      // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
3431      // the original GPRs.
3432
3433      unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3434      PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3435      SDValue Chain = SDValue(N,0);
3436
3437      SDNode *GU = N->getGluedUser();
3438      SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
3439                                               Chain.getValue(1));
3440
3441      // Extract values from a GPRPair reg and copy to the original GPR reg.
3442      SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
3443                                                    RegCopy);
3444      SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
3445                                                    RegCopy);
3446      SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
3447                                        RegCopy.getValue(1));
3448      SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
3449
3450      // Update the original glue user.
3451      std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
3452      Ops.push_back(T1.getValue(1));
3453      CurDAG->UpdateNodeOperands(GU, &Ops[0], Ops.size());
3454      GU = T1.getNode();
3455    }
3456    else {
3457      // For Kind  == InlineAsm::Kind_RegUse, we first copy two GPRs into a
3458      // GPRPair and then pass the GPRPair to the inline asm.
3459      SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
3460
3461      // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
3462      SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
3463                                          Chain.getValue(1));
3464      SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
3465                                          T0.getValue(1));
3466      SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
3467
3468      // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
3469      // i32 VRs of inline asm with it.
3470      unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3471      PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3472      Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
3473
3474      AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
3475      Glue = Chain.getValue(1);
3476    }
3477
3478    Changed = true;
3479
3480    if(PairedReg.getNode()) {
3481      OpChanged[OpChanged.size() -1 ] = true;
3482      Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
3483      if (IsTiedToChangedOp)
3484        Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
3485      else
3486        Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
3487      // Replace the current flag.
3488      AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
3489          Flag, MVT::i32);
3490      // Add the new register node and skip the original two GPRs.
3491      AsmNodeOperands.push_back(PairedReg);
3492      // Skip the next two GPRs.
3493      i += 2;
3494    }
3495  }
3496
3497  if (Glue.getNode())
3498    AsmNodeOperands.push_back(Glue);
3499  if (!Changed)
3500    return NULL;
3501
3502  SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
3503      CurDAG->getVTList(MVT::Other, MVT::Glue), &AsmNodeOperands[0],
3504                        AsmNodeOperands.size());
3505  New->setNodeId(-1);
3506  return New.getNode();
3507}
3508
3509
3510bool ARMDAGToDAGISel::
3511SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3512                             std::vector<SDValue> &OutOps) {
3513  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3514  // Require the address to be in a register.  That is safe for all ARM
3515  // variants and it is hard to do anything much smarter without knowing
3516  // how the operand is used.
3517  OutOps.push_back(Op);
3518  return false;
3519}
3520
3521/// createARMISelDag - This pass converts a legalized DAG into a
3522/// ARM-specific DAG, ready for instruction scheduling.
3523///
3524FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3525                                     CodeGenOpt::Level OptLevel) {
3526  return new ARMDAGToDAGISel(TM, OptLevel);
3527}
3528