ARMFeatures.h revision 263508 
1//===-- ARMFeatures.h - Checks for ARM instruction features ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the code shared between ARM CodeGen and ARM MC
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef TARGET_ARM_FEATURES_H
15#define TARGET_ARM_FEATURES_H
16
17#include "ARM.h"
18
19namespace llvm {
20
21template<typename InstrType> // could be MachineInstr or MCInst
22inline bool isV8EligibleForIT(InstrType *Instr, int BLXOperandIndex = 0) {
23  switch (Instr->getOpcode()) {
24  default:
25    return false;
26  case ARM::tADC:
27  case ARM::tADDi3:
28  case ARM::tADDi8:
29  case ARM::tADDrSPi:
30  case ARM::tADDrr:
31  case ARM::tAND:
32  case ARM::tASRri:
33  case ARM::tASRrr:
34  case ARM::tBIC:
35  case ARM::tCMNz:
36  case ARM::tCMPi8:
37  case ARM::tCMPr:
38  case ARM::tEOR:
39  case ARM::tLDRBi:
40  case ARM::tLDRBr:
41  case ARM::tLDRHi:
42  case ARM::tLDRHr:
43  case ARM::tLDRSB:
44  case ARM::tLDRSH:
45  case ARM::tLDRi:
46  case ARM::tLDRr:
47  case ARM::tLDRspi:
48  case ARM::tLSLri:
49  case ARM::tLSLrr:
50  case ARM::tLSRri:
51  case ARM::tLSRrr:
52  case ARM::tMOVi8:
53  case ARM::tMUL:
54  case ARM::tMVN:
55  case ARM::tORR:
56  case ARM::tROR:
57  case ARM::tRSB:
58  case ARM::tSBC:
59  case ARM::tSTRBi:
60  case ARM::tSTRBr:
61  case ARM::tSTRHi:
62  case ARM::tSTRHr:
63  case ARM::tSTRi:
64  case ARM::tSTRr:
65  case ARM::tSTRspi:
66  case ARM::tSUBi3:
67  case ARM::tSUBi8:
68  case ARM::tSUBrr:
69  case ARM::tTST:
70    return true;
71// there are some "conditionally deprecated" opcodes
72  case ARM::tADDspr:
73    return Instr->getOperand(2).getReg() != ARM::PC;
74  // ADD PC, SP and BLX PC were always unpredictable,
75  // now on top of it they're deprecated
76  case ARM::tADDrSP:
77  case ARM::tBX:
78    return Instr->getOperand(0).getReg() != ARM::PC;
79  case ARM::tBLXr:
80    return Instr->getOperand(BLXOperandIndex).getReg() != ARM::PC;
81  case ARM::tADDhirr:
82    return Instr->getOperand(0).getReg() != ARM::PC &&
83           Instr->getOperand(2).getReg() != ARM::PC;
84  case ARM::tCMPhir:
85  case ARM::tMOVr:
86    return Instr->getOperand(0).getReg() != ARM::PC &&
87           Instr->getOperand(1).getReg() != ARM::PC;
88  }
89}
90
91}
92
93#endif
94