ARMBaseInstrInfo.cpp revision 263508 
1//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMFeatures.h"
19#include "ARMHazardRecognizer.h"
20#include "ARMMachineFunctionInfo.h"
21#include "MCTargetDesc/ARMAddressingModes.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/CodeGen/LiveVariables.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineJumpTableInfo.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/SelectionDAGNodes.h"
31#include "llvm/IR/Constants.h"
32#include "llvm/IR/Function.h"
33#include "llvm/IR/GlobalValue.h"
34#include "llvm/MC/MCAsmInfo.h"
35#include "llvm/Support/BranchProbability.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39
40#define GET_INSTRINFO_CTOR_DTOR
41#include "ARMGenInstrInfo.inc"
42
43using namespace llvm;
44
45static cl::opt<bool>
46EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
47               cl::desc("Enable ARM 2-addr to 3-addr conv"));
48
49static cl::opt<bool>
50WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
51           cl::desc("Widen ARM vmovs to vmovd when possible"));
52
53static cl::opt<unsigned>
54SwiftPartialUpdateClearance("swift-partial-update-clearance",
55     cl::Hidden, cl::init(12),
56     cl::desc("Clearance before partial register updates"));
57
58/// ARM_MLxEntry - Record information about MLA / MLS instructions.
59struct ARM_MLxEntry {
60  uint16_t MLxOpc;     // MLA / MLS opcode
61  uint16_t MulOpc;     // Expanded multiplication opcode
62  uint16_t AddSubOpc;  // Expanded add / sub opcode
63  bool NegAcc;         // True if the acc is negated before the add / sub.
64  bool HasLane;        // True if instruction has an extra "lane" operand.
65};
66
67static const ARM_MLxEntry ARM_MLxTable[] = {
68  // MLxOpc,          MulOpc,           AddSubOpc,       NegAcc, HasLane
69  // fp scalar ops
70  { ARM::VMLAS,       ARM::VMULS,       ARM::VADDS,      false,  false },
71  { ARM::VMLSS,       ARM::VMULS,       ARM::VSUBS,      false,  false },
72  { ARM::VMLAD,       ARM::VMULD,       ARM::VADDD,      false,  false },
73  { ARM::VMLSD,       ARM::VMULD,       ARM::VSUBD,      false,  false },
74  { ARM::VNMLAS,      ARM::VNMULS,      ARM::VSUBS,      true,   false },
75  { ARM::VNMLSS,      ARM::VMULS,       ARM::VSUBS,      true,   false },
76  { ARM::VNMLAD,      ARM::VNMULD,      ARM::VSUBD,      true,   false },
77  { ARM::VNMLSD,      ARM::VMULD,       ARM::VSUBD,      true,   false },
78
79  // fp SIMD ops
80  { ARM::VMLAfd,      ARM::VMULfd,      ARM::VADDfd,     false,  false },
81  { ARM::VMLSfd,      ARM::VMULfd,      ARM::VSUBfd,     false,  false },
82  { ARM::VMLAfq,      ARM::VMULfq,      ARM::VADDfq,     false,  false },
83  { ARM::VMLSfq,      ARM::VMULfq,      ARM::VSUBfq,     false,  false },
84  { ARM::VMLAslfd,    ARM::VMULslfd,    ARM::VADDfd,     false,  true  },
85  { ARM::VMLSslfd,    ARM::VMULslfd,    ARM::VSUBfd,     false,  true  },
86  { ARM::VMLAslfq,    ARM::VMULslfq,    ARM::VADDfq,     false,  true  },
87  { ARM::VMLSslfq,    ARM::VMULslfq,    ARM::VSUBfq,     false,  true  },
88};
89
90ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
91  : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
92    Subtarget(STI) {
93  for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
94    if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
95      assert(false && "Duplicated entries?");
96    MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
97    MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
98  }
99}
100
101// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
102// currently defaults to no prepass hazard recognizer.
103ScheduleHazardRecognizer *ARMBaseInstrInfo::
104CreateTargetHazardRecognizer(const TargetMachine *TM,
105                             const ScheduleDAG *DAG) const {
106  if (usePreRAHazardRecognizer()) {
107    const InstrItineraryData *II = TM->getInstrItineraryData();
108    return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
109  }
110  return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
111}
112
113ScheduleHazardRecognizer *ARMBaseInstrInfo::
114CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
115                                   const ScheduleDAG *DAG) const {
116  if (Subtarget.isThumb2() || Subtarget.hasVFP2())
117    return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
118  return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
119}
120
121MachineInstr *
122ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
123                                        MachineBasicBlock::iterator &MBBI,
124                                        LiveVariables *LV) const {
125  // FIXME: Thumb2 support.
126
127  if (!EnableARM3Addr)
128    return NULL;
129
130  MachineInstr *MI = MBBI;
131  MachineFunction &MF = *MI->getParent()->getParent();
132  uint64_t TSFlags = MI->getDesc().TSFlags;
133  bool isPre = false;
134  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
135  default: return NULL;
136  case ARMII::IndexModePre:
137    isPre = true;
138    break;
139  case ARMII::IndexModePost:
140    break;
141  }
142
143  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
144  // operation.
145  unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
146  if (MemOpc == 0)
147    return NULL;
148
149  MachineInstr *UpdateMI = NULL;
150  MachineInstr *MemMI = NULL;
151  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
152  const MCInstrDesc &MCID = MI->getDesc();
153  unsigned NumOps = MCID.getNumOperands();
154  bool isLoad = !MI->mayStore();
155  const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
156  const MachineOperand &Base = MI->getOperand(2);
157  const MachineOperand &Offset = MI->getOperand(NumOps-3);
158  unsigned WBReg = WB.getReg();
159  unsigned BaseReg = Base.getReg();
160  unsigned OffReg = Offset.getReg();
161  unsigned OffImm = MI->getOperand(NumOps-2).getImm();
162  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
163  switch (AddrMode) {
164  default: llvm_unreachable("Unknown indexed op!");
165  case ARMII::AddrMode2: {
166    bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
167    unsigned Amt = ARM_AM::getAM2Offset(OffImm);
168    if (OffReg == 0) {
169      if (ARM_AM::getSOImmVal(Amt) == -1)
170        // Can't encode it in a so_imm operand. This transformation will
171        // add more than 1 instruction. Abandon!
172        return NULL;
173      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
174                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
175        .addReg(BaseReg).addImm(Amt)
176        .addImm(Pred).addReg(0).addReg(0);
177    } else if (Amt != 0) {
178      ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
179      unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
180      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181                         get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
182        .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
183        .addImm(Pred).addReg(0).addReg(0);
184    } else
185      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
186                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
187        .addReg(BaseReg).addReg(OffReg)
188        .addImm(Pred).addReg(0).addReg(0);
189    break;
190  }
191  case ARMII::AddrMode3 : {
192    bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
193    unsigned Amt = ARM_AM::getAM3Offset(OffImm);
194    if (OffReg == 0)
195      // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
196      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
197                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
198        .addReg(BaseReg).addImm(Amt)
199        .addImm(Pred).addReg(0).addReg(0);
200    else
201      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
202                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
203        .addReg(BaseReg).addReg(OffReg)
204        .addImm(Pred).addReg(0).addReg(0);
205    break;
206  }
207  }
208
209  std::vector<MachineInstr*> NewMIs;
210  if (isPre) {
211    if (isLoad)
212      MemMI = BuildMI(MF, MI->getDebugLoc(),
213                      get(MemOpc), MI->getOperand(0).getReg())
214        .addReg(WBReg).addImm(0).addImm(Pred);
215    else
216      MemMI = BuildMI(MF, MI->getDebugLoc(),
217                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
218        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
219    NewMIs.push_back(MemMI);
220    NewMIs.push_back(UpdateMI);
221  } else {
222    if (isLoad)
223      MemMI = BuildMI(MF, MI->getDebugLoc(),
224                      get(MemOpc), MI->getOperand(0).getReg())
225        .addReg(BaseReg).addImm(0).addImm(Pred);
226    else
227      MemMI = BuildMI(MF, MI->getDebugLoc(),
228                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
229        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
230    if (WB.isDead())
231      UpdateMI->getOperand(0).setIsDead();
232    NewMIs.push_back(UpdateMI);
233    NewMIs.push_back(MemMI);
234  }
235
236  // Transfer LiveVariables states, kill / dead info.
237  if (LV) {
238    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
239      MachineOperand &MO = MI->getOperand(i);
240      if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
241        unsigned Reg = MO.getReg();
242
243        LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
244        if (MO.isDef()) {
245          MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
246          if (MO.isDead())
247            LV->addVirtualRegisterDead(Reg, NewMI);
248        }
249        if (MO.isUse() && MO.isKill()) {
250          for (unsigned j = 0; j < 2; ++j) {
251            // Look at the two new MI's in reverse order.
252            MachineInstr *NewMI = NewMIs[j];
253            if (!NewMI->readsRegister(Reg))
254              continue;
255            LV->addVirtualRegisterKilled(Reg, NewMI);
256            if (VI.removeKill(MI))
257              VI.Kills.push_back(NewMI);
258            break;
259          }
260        }
261      }
262    }
263  }
264
265  MFI->insert(MBBI, NewMIs[1]);
266  MFI->insert(MBBI, NewMIs[0]);
267  return NewMIs[0];
268}
269
270// Branch analysis.
271bool
272ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
273                                MachineBasicBlock *&FBB,
274                                SmallVectorImpl<MachineOperand> &Cond,
275                                bool AllowModify) const {
276  TBB = 0;
277  FBB = 0;
278
279  MachineBasicBlock::iterator I = MBB.end();
280  if (I == MBB.begin())
281    return false; // Empty blocks are easy.
282  --I;
283
284  // Walk backwards from the end of the basic block until the branch is
285  // analyzed or we give up.
286  while (isPredicated(I) || I->isTerminator()) {
287
288    // Flag to be raised on unanalyzeable instructions. This is useful in cases
289    // where we want to clean up on the end of the basic block before we bail
290    // out.
291    bool CantAnalyze = false;
292
293    // Skip over DEBUG values and predicated nonterminators.
294    while (I->isDebugValue() || !I->isTerminator()) {
295      if (I == MBB.begin())
296        return false;
297      --I;
298    }
299
300    if (isIndirectBranchOpcode(I->getOpcode()) ||
301        isJumpTableBranchOpcode(I->getOpcode())) {
302      // Indirect branches and jump tables can't be analyzed, but we still want
303      // to clean up any instructions at the tail of the basic block.
304      CantAnalyze = true;
305    } else if (isUncondBranchOpcode(I->getOpcode())) {
306      TBB = I->getOperand(0).getMBB();
307    } else if (isCondBranchOpcode(I->getOpcode())) {
308      // Bail out if we encounter multiple conditional branches.
309      if (!Cond.empty())
310        return true;
311
312      assert(!FBB && "FBB should have been null.");
313      FBB = TBB;
314      TBB = I->getOperand(0).getMBB();
315      Cond.push_back(I->getOperand(1));
316      Cond.push_back(I->getOperand(2));
317    } else if (I->isReturn()) {
318      // Returns can't be analyzed, but we should run cleanup.
319      CantAnalyze = !isPredicated(I);
320    } else {
321      // We encountered other unrecognized terminator. Bail out immediately.
322      return true;
323    }
324
325    // Cleanup code - to be run for unpredicated unconditional branches and
326    //                returns.
327    if (!isPredicated(I) &&
328          (isUncondBranchOpcode(I->getOpcode()) ||
329           isIndirectBranchOpcode(I->getOpcode()) ||
330           isJumpTableBranchOpcode(I->getOpcode()) ||
331           I->isReturn())) {
332      // Forget any previous condition branch information - it no longer applies.
333      Cond.clear();
334      FBB = 0;
335
336      // If we can modify the function, delete everything below this
337      // unconditional branch.
338      if (AllowModify) {
339        MachineBasicBlock::iterator DI = llvm::next(I);
340        while (DI != MBB.end()) {
341          MachineInstr *InstToDelete = DI;
342          ++DI;
343          InstToDelete->eraseFromParent();
344        }
345      }
346    }
347
348    if (CantAnalyze)
349      return true;
350
351    if (I == MBB.begin())
352      return false;
353
354    --I;
355  }
356
357  // We made it past the terminators without bailing out - we must have
358  // analyzed this branch successfully.
359  return false;
360}
361
362
363unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
364  MachineBasicBlock::iterator I = MBB.end();
365  if (I == MBB.begin()) return 0;
366  --I;
367  while (I->isDebugValue()) {
368    if (I == MBB.begin())
369      return 0;
370    --I;
371  }
372  if (!isUncondBranchOpcode(I->getOpcode()) &&
373      !isCondBranchOpcode(I->getOpcode()))
374    return 0;
375
376  // Remove the branch.
377  I->eraseFromParent();
378
379  I = MBB.end();
380
381  if (I == MBB.begin()) return 1;
382  --I;
383  if (!isCondBranchOpcode(I->getOpcode()))
384    return 1;
385
386  // Remove the branch.
387  I->eraseFromParent();
388  return 2;
389}
390
391unsigned
392ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
393                               MachineBasicBlock *FBB,
394                               const SmallVectorImpl<MachineOperand> &Cond,
395                               DebugLoc DL) const {
396  ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
397  int BOpc   = !AFI->isThumbFunction()
398    ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
399  int BccOpc = !AFI->isThumbFunction()
400    ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
401  bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
402
403  // Shouldn't be a fall through.
404  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
405  assert((Cond.size() == 2 || Cond.size() == 0) &&
406         "ARM branch conditions have two components!");
407
408  if (FBB == 0) {
409    if (Cond.empty()) { // Unconditional branch?
410      if (isThumb)
411        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
412      else
413        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
414    } else
415      BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
416        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
417    return 1;
418  }
419
420  // Two-way conditional branch.
421  BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
422    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
423  if (isThumb)
424    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
425  else
426    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
427  return 2;
428}
429
430bool ARMBaseInstrInfo::
431ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
432  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
433  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
434  return false;
435}
436
437bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
438  if (MI->isBundle()) {
439    MachineBasicBlock::const_instr_iterator I = MI;
440    MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
441    while (++I != E && I->isInsideBundle()) {
442      int PIdx = I->findFirstPredOperandIdx();
443      if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
444        return true;
445    }
446    return false;
447  }
448
449  int PIdx = MI->findFirstPredOperandIdx();
450  return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
451}
452
453bool ARMBaseInstrInfo::
454PredicateInstruction(MachineInstr *MI,
455                     const SmallVectorImpl<MachineOperand> &Pred) const {
456  unsigned Opc = MI->getOpcode();
457  if (isUncondBranchOpcode(Opc)) {
458    MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
459    MachineInstrBuilder(*MI->getParent()->getParent(), MI)
460      .addImm(Pred[0].getImm())
461      .addReg(Pred[1].getReg());
462    return true;
463  }
464
465  int PIdx = MI->findFirstPredOperandIdx();
466  if (PIdx != -1) {
467    MachineOperand &PMO = MI->getOperand(PIdx);
468    PMO.setImm(Pred[0].getImm());
469    MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
470    return true;
471  }
472  return false;
473}
474
475bool ARMBaseInstrInfo::
476SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
477                  const SmallVectorImpl<MachineOperand> &Pred2) const {
478  if (Pred1.size() > 2 || Pred2.size() > 2)
479    return false;
480
481  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
482  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
483  if (CC1 == CC2)
484    return true;
485
486  switch (CC1) {
487  default:
488    return false;
489  case ARMCC::AL:
490    return true;
491  case ARMCC::HS:
492    return CC2 == ARMCC::HI;
493  case ARMCC::LS:
494    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
495  case ARMCC::GE:
496    return CC2 == ARMCC::GT;
497  case ARMCC::LE:
498    return CC2 == ARMCC::LT;
499  }
500}
501
502bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
503                                    std::vector<MachineOperand> &Pred) const {
504  bool Found = false;
505  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
506    const MachineOperand &MO = MI->getOperand(i);
507    if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
508        (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
509      Pred.push_back(MO);
510      Found = true;
511    }
512  }
513
514  return Found;
515}
516
517/// isPredicable - Return true if the specified instruction can be predicated.
518/// By default, this returns true for every instruction with a
519/// PredicateOperand.
520bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
521  if (!MI->isPredicable())
522    return false;
523
524  ARMFunctionInfo *AFI =
525    MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
526
527  if (AFI->isThumb2Function()) {
528    if (getSubtarget().restrictIT())
529      return isV8EligibleForIT(MI);
530  } else { // non-Thumb
531    if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
532      return false;
533  }
534
535  return true;
536}
537
538/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
539LLVM_ATTRIBUTE_NOINLINE
540static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
541                                unsigned JTI);
542static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
543                                unsigned JTI) {
544  assert(JTI < JT.size());
545  return JT[JTI].MBBs.size();
546}
547
548/// GetInstSize - Return the size of the specified MachineInstr.
549///
550unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
551  const MachineBasicBlock &MBB = *MI->getParent();
552  const MachineFunction *MF = MBB.getParent();
553  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
554
555  const MCInstrDesc &MCID = MI->getDesc();
556  if (MCID.getSize())
557    return MCID.getSize();
558
559  // If this machine instr is an inline asm, measure it.
560  if (MI->getOpcode() == ARM::INLINEASM)
561    return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
562  if (MI->isLabel())
563    return 0;
564  unsigned Opc = MI->getOpcode();
565  switch (Opc) {
566  case TargetOpcode::IMPLICIT_DEF:
567  case TargetOpcode::KILL:
568  case TargetOpcode::PROLOG_LABEL:
569  case TargetOpcode::EH_LABEL:
570  case TargetOpcode::DBG_VALUE:
571    return 0;
572  case TargetOpcode::BUNDLE:
573    return getInstBundleLength(MI);
574  case ARM::MOVi16_ga_pcrel:
575  case ARM::MOVTi16_ga_pcrel:
576  case ARM::t2MOVi16_ga_pcrel:
577  case ARM::t2MOVTi16_ga_pcrel:
578    return 4;
579  case ARM::MOVi32imm:
580  case ARM::t2MOVi32imm:
581    return 8;
582  case ARM::CONSTPOOL_ENTRY:
583    // If this machine instr is a constant pool entry, its size is recorded as
584    // operand #2.
585    return MI->getOperand(2).getImm();
586  case ARM::Int_eh_sjlj_longjmp:
587    return 16;
588  case ARM::tInt_eh_sjlj_longjmp:
589    return 10;
590  case ARM::Int_eh_sjlj_setjmp:
591  case ARM::Int_eh_sjlj_setjmp_nofp:
592    return 20;
593  case ARM::tInt_eh_sjlj_setjmp:
594  case ARM::t2Int_eh_sjlj_setjmp:
595  case ARM::t2Int_eh_sjlj_setjmp_nofp:
596    return 12;
597  case ARM::BR_JTr:
598  case ARM::BR_JTm:
599  case ARM::BR_JTadd:
600  case ARM::tBR_JTr:
601  case ARM::t2BR_JT:
602  case ARM::t2TBB_JT:
603  case ARM::t2TBH_JT: {
604    // These are jumptable branches, i.e. a branch followed by an inlined
605    // jumptable. The size is 4 + 4 * number of entries. For TBB, each
606    // entry is one byte; TBH two byte each.
607    unsigned EntrySize = (Opc == ARM::t2TBB_JT)
608      ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
609    unsigned NumOps = MCID.getNumOperands();
610    MachineOperand JTOP =
611      MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
612    unsigned JTI = JTOP.getIndex();
613    const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
614    assert(MJTI != 0);
615    const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
616    assert(JTI < JT.size());
617    // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
618    // 4 aligned. The assembler / linker may add 2 byte padding just before
619    // the JT entries.  The size does not include this padding; the
620    // constant islands pass does separate bookkeeping for it.
621    // FIXME: If we know the size of the function is less than (1 << 16) *2
622    // bytes, we can use 16-bit entries instead. Then there won't be an
623    // alignment issue.
624    unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
625    unsigned NumEntries = getNumJTEntries(JT, JTI);
626    if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
627      // Make sure the instruction that follows TBB is 2-byte aligned.
628      // FIXME: Constant island pass should insert an "ALIGN" instruction
629      // instead.
630      ++NumEntries;
631    return NumEntries * EntrySize + InstSize;
632  }
633  default:
634    // Otherwise, pseudo-instruction sizes are zero.
635    return 0;
636  }
637}
638
639unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
640  unsigned Size = 0;
641  MachineBasicBlock::const_instr_iterator I = MI;
642  MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
643  while (++I != E && I->isInsideBundle()) {
644    assert(!I->isBundle() && "No nested bundle!");
645    Size += GetInstSizeInBytes(&*I);
646  }
647  return Size;
648}
649
650void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
651                                   MachineBasicBlock::iterator I, DebugLoc DL,
652                                   unsigned DestReg, unsigned SrcReg,
653                                   bool KillSrc) const {
654  bool GPRDest = ARM::GPRRegClass.contains(DestReg);
655  bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
656
657  if (GPRDest && GPRSrc) {
658    AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
659                                    .addReg(SrcReg, getKillRegState(KillSrc))));
660    return;
661  }
662
663  bool SPRDest = ARM::SPRRegClass.contains(DestReg);
664  bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
665
666  unsigned Opc = 0;
667  if (SPRDest && SPRSrc)
668    Opc = ARM::VMOVS;
669  else if (GPRDest && SPRSrc)
670    Opc = ARM::VMOVRS;
671  else if (SPRDest && GPRSrc)
672    Opc = ARM::VMOVSR;
673  else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
674    Opc = ARM::VMOVD;
675  else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
676    Opc = ARM::VORRq;
677
678  if (Opc) {
679    MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
680    MIB.addReg(SrcReg, getKillRegState(KillSrc));
681    if (Opc == ARM::VORRq)
682      MIB.addReg(SrcReg, getKillRegState(KillSrc));
683    AddDefaultPred(MIB);
684    return;
685  }
686
687  // Handle register classes that require multiple instructions.
688  unsigned BeginIdx = 0;
689  unsigned SubRegs = 0;
690  int Spacing = 1;
691
692  // Use VORRq when possible.
693  if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
694    Opc = ARM::VORRq;
695    BeginIdx = ARM::qsub_0;
696    SubRegs = 2;
697  } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
698    Opc = ARM::VORRq;
699    BeginIdx = ARM::qsub_0;
700    SubRegs = 4;
701  // Fall back to VMOVD.
702  } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
703    Opc = ARM::VMOVD;
704    BeginIdx = ARM::dsub_0;
705    SubRegs = 2;
706  } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
707    Opc = ARM::VMOVD;
708    BeginIdx = ARM::dsub_0;
709    SubRegs = 3;
710  } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
711    Opc = ARM::VMOVD;
712    BeginIdx = ARM::dsub_0;
713    SubRegs = 4;
714  } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
715    Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
716    BeginIdx = ARM::gsub_0;
717    SubRegs = 2;
718  } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
719    Opc = ARM::VMOVD;
720    BeginIdx = ARM::dsub_0;
721    SubRegs = 2;
722    Spacing = 2;
723  } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
724    Opc = ARM::VMOVD;
725    BeginIdx = ARM::dsub_0;
726    SubRegs = 3;
727    Spacing = 2;
728  } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
729    Opc = ARM::VMOVD;
730    BeginIdx = ARM::dsub_0;
731    SubRegs = 4;
732    Spacing = 2;
733  }
734
735  assert(Opc && "Impossible reg-to-reg copy");
736
737  const TargetRegisterInfo *TRI = &getRegisterInfo();
738  MachineInstrBuilder Mov;
739
740  // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
741  if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
742    BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
743    Spacing = -Spacing;
744  }
745#ifndef NDEBUG
746  SmallSet<unsigned, 4> DstRegs;
747#endif
748  for (unsigned i = 0; i != SubRegs; ++i) {
749    unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
750    unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
751    assert(Dst && Src && "Bad sub-register");
752#ifndef NDEBUG
753    assert(!DstRegs.count(Src) && "destructive vector copy");
754    DstRegs.insert(Dst);
755#endif
756    Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
757    // VORR takes two source operands.
758    if (Opc == ARM::VORRq)
759      Mov.addReg(Src);
760    Mov = AddDefaultPred(Mov);
761    // MOVr can set CC.
762    if (Opc == ARM::MOVr)
763      Mov = AddDefaultCC(Mov);
764  }
765  // Add implicit super-register defs and kills to the last instruction.
766  Mov->addRegisterDefined(DestReg, TRI);
767  if (KillSrc)
768    Mov->addRegisterKilled(SrcReg, TRI);
769}
770
771const MachineInstrBuilder &
772ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
773                          unsigned SubIdx, unsigned State,
774                          const TargetRegisterInfo *TRI) const {
775  if (!SubIdx)
776    return MIB.addReg(Reg, State);
777
778  if (TargetRegisterInfo::isPhysicalRegister(Reg))
779    return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
780  return MIB.addReg(Reg, State, SubIdx);
781}
782
783void ARMBaseInstrInfo::
784storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
785                    unsigned SrcReg, bool isKill, int FI,
786                    const TargetRegisterClass *RC,
787                    const TargetRegisterInfo *TRI) const {
788  DebugLoc DL;
789  if (I != MBB.end()) DL = I->getDebugLoc();
790  MachineFunction &MF = *MBB.getParent();
791  MachineFrameInfo &MFI = *MF.getFrameInfo();
792  unsigned Align = MFI.getObjectAlignment(FI);
793
794  MachineMemOperand *MMO =
795    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
796                            MachineMemOperand::MOStore,
797                            MFI.getObjectSize(FI),
798                            Align);
799
800  switch (RC->getSize()) {
801    case 4:
802      if (ARM::GPRRegClass.hasSubClassEq(RC)) {
803        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
804                   .addReg(SrcReg, getKillRegState(isKill))
805                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
806      } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
807        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
808                   .addReg(SrcReg, getKillRegState(isKill))
809                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
810      } else
811        llvm_unreachable("Unknown reg class!");
812      break;
813    case 8:
814      if (ARM::DPRRegClass.hasSubClassEq(RC)) {
815        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
816                   .addReg(SrcReg, getKillRegState(isKill))
817                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
818      } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
819        if (Subtarget.hasV5TEOps()) {
820          MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
821          AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
822          AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
823          MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
824
825          AddDefaultPred(MIB);
826        } else {
827          // Fallback to STM instruction, which has existed since the dawn of
828          // time.
829          MachineInstrBuilder MIB =
830            AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
831                             .addFrameIndex(FI).addMemOperand(MMO));
832          AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
833          AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
834        }
835      } else
836        llvm_unreachable("Unknown reg class!");
837      break;
838    case 16:
839      if (ARM::DPairRegClass.hasSubClassEq(RC)) {
840        // Use aligned spills if the stack can be realigned.
841        if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
842          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
843                     .addFrameIndex(FI).addImm(16)
844                     .addReg(SrcReg, getKillRegState(isKill))
845                     .addMemOperand(MMO));
846        } else {
847          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
848                     .addReg(SrcReg, getKillRegState(isKill))
849                     .addFrameIndex(FI)
850                     .addMemOperand(MMO));
851        }
852      } else
853        llvm_unreachable("Unknown reg class!");
854      break;
855    case 24:
856      if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
857        // Use aligned spills if the stack can be realigned.
858        if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
859          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
860                     .addFrameIndex(FI).addImm(16)
861                     .addReg(SrcReg, getKillRegState(isKill))
862                     .addMemOperand(MMO));
863        } else {
864          MachineInstrBuilder MIB =
865          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
866                       .addFrameIndex(FI))
867                       .addMemOperand(MMO);
868          MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
869          MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
870          AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
871        }
872      } else
873        llvm_unreachable("Unknown reg class!");
874      break;
875    case 32:
876      if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
877        if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
878          // FIXME: It's possible to only store part of the QQ register if the
879          // spilled def has a sub-register index.
880          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
881                     .addFrameIndex(FI).addImm(16)
882                     .addReg(SrcReg, getKillRegState(isKill))
883                     .addMemOperand(MMO));
884        } else {
885          MachineInstrBuilder MIB =
886          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
887                       .addFrameIndex(FI))
888                       .addMemOperand(MMO);
889          MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
890          MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
891          MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
892                AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
893        }
894      } else
895        llvm_unreachable("Unknown reg class!");
896      break;
897    case 64:
898      if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
899        MachineInstrBuilder MIB =
900          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
901                         .addFrameIndex(FI))
902                         .addMemOperand(MMO);
903        MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
904        MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
905        MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
906        MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
907        MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
908        MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
909        MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
910              AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
911      } else
912        llvm_unreachable("Unknown reg class!");
913      break;
914    default:
915      llvm_unreachable("Unknown reg class!");
916  }
917}
918
919unsigned
920ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
921                                     int &FrameIndex) const {
922  switch (MI->getOpcode()) {
923  default: break;
924  case ARM::STRrs:
925  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
926    if (MI->getOperand(1).isFI() &&
927        MI->getOperand(2).isReg() &&
928        MI->getOperand(3).isImm() &&
929        MI->getOperand(2).getReg() == 0 &&
930        MI->getOperand(3).getImm() == 0) {
931      FrameIndex = MI->getOperand(1).getIndex();
932      return MI->getOperand(0).getReg();
933    }
934    break;
935  case ARM::STRi12:
936  case ARM::t2STRi12:
937  case ARM::tSTRspi:
938  case ARM::VSTRD:
939  case ARM::VSTRS:
940    if (MI->getOperand(1).isFI() &&
941        MI->getOperand(2).isImm() &&
942        MI->getOperand(2).getImm() == 0) {
943      FrameIndex = MI->getOperand(1).getIndex();
944      return MI->getOperand(0).getReg();
945    }
946    break;
947  case ARM::VST1q64:
948  case ARM::VST1d64TPseudo:
949  case ARM::VST1d64QPseudo:
950    if (MI->getOperand(0).isFI() &&
951        MI->getOperand(2).getSubReg() == 0) {
952      FrameIndex = MI->getOperand(0).getIndex();
953      return MI->getOperand(2).getReg();
954    }
955    break;
956  case ARM::VSTMQIA:
957    if (MI->getOperand(1).isFI() &&
958        MI->getOperand(0).getSubReg() == 0) {
959      FrameIndex = MI->getOperand(1).getIndex();
960      return MI->getOperand(0).getReg();
961    }
962    break;
963  }
964
965  return 0;
966}
967
968unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
969                                                    int &FrameIndex) const {
970  const MachineMemOperand *Dummy;
971  return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
972}
973
974void ARMBaseInstrInfo::
975loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
976                     unsigned DestReg, int FI,
977                     const TargetRegisterClass *RC,
978                     const TargetRegisterInfo *TRI) const {
979  DebugLoc DL;
980  if (I != MBB.end()) DL = I->getDebugLoc();
981  MachineFunction &MF = *MBB.getParent();
982  MachineFrameInfo &MFI = *MF.getFrameInfo();
983  unsigned Align = MFI.getObjectAlignment(FI);
984  MachineMemOperand *MMO =
985    MF.getMachineMemOperand(
986                    MachinePointerInfo::getFixedStack(FI),
987                            MachineMemOperand::MOLoad,
988                            MFI.getObjectSize(FI),
989                            Align);
990
991  switch (RC->getSize()) {
992  case 4:
993    if (ARM::GPRRegClass.hasSubClassEq(RC)) {
994      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
995                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
996
997    } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
998      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
999                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1000    } else
1001      llvm_unreachable("Unknown reg class!");
1002    break;
1003  case 8:
1004    if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1005      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1006                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1007    } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1008      MachineInstrBuilder MIB;
1009
1010      if (Subtarget.hasV5TEOps()) {
1011        MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1012        AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1013        AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1014        MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1015
1016        AddDefaultPred(MIB);
1017      } else {
1018        // Fallback to LDM instruction, which has existed since the dawn of
1019        // time.
1020        MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1021                                 .addFrameIndex(FI).addMemOperand(MMO));
1022        MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1023        MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1024      }
1025
1026      if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1027        MIB.addReg(DestReg, RegState::ImplicitDefine);
1028    } else
1029      llvm_unreachable("Unknown reg class!");
1030    break;
1031  case 16:
1032    if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1033      if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1034        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1035                     .addFrameIndex(FI).addImm(16)
1036                     .addMemOperand(MMO));
1037      } else {
1038        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1039                       .addFrameIndex(FI)
1040                       .addMemOperand(MMO));
1041      }
1042    } else
1043      llvm_unreachable("Unknown reg class!");
1044    break;
1045  case 24:
1046    if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1047      if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1048        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1049                     .addFrameIndex(FI).addImm(16)
1050                     .addMemOperand(MMO));
1051      } else {
1052        MachineInstrBuilder MIB =
1053          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1054                         .addFrameIndex(FI)
1055                         .addMemOperand(MMO));
1056        MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1057        MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1058        MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1059        if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1060          MIB.addReg(DestReg, RegState::ImplicitDefine);
1061      }
1062    } else
1063      llvm_unreachable("Unknown reg class!");
1064    break;
1065   case 32:
1066    if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1067      if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1068        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1069                     .addFrameIndex(FI).addImm(16)
1070                     .addMemOperand(MMO));
1071      } else {
1072        MachineInstrBuilder MIB =
1073        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1074                       .addFrameIndex(FI))
1075                       .addMemOperand(MMO);
1076        MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1077        MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1078        MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1079        MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1080        if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1081          MIB.addReg(DestReg, RegState::ImplicitDefine);
1082      }
1083    } else
1084      llvm_unreachable("Unknown reg class!");
1085    break;
1086  case 64:
1087    if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1088      MachineInstrBuilder MIB =
1089      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1090                     .addFrameIndex(FI))
1091                     .addMemOperand(MMO);
1092      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1093      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1094      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1095      MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1096      MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1097      MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1098      MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1099      MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1100      if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1101        MIB.addReg(DestReg, RegState::ImplicitDefine);
1102    } else
1103      llvm_unreachable("Unknown reg class!");
1104    break;
1105  default:
1106    llvm_unreachable("Unknown regclass!");
1107  }
1108}
1109
1110unsigned
1111ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1112                                      int &FrameIndex) const {
1113  switch (MI->getOpcode()) {
1114  default: break;
1115  case ARM::LDRrs:
1116  case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
1117    if (MI->getOperand(1).isFI() &&
1118        MI->getOperand(2).isReg() &&
1119        MI->getOperand(3).isImm() &&
1120        MI->getOperand(2).getReg() == 0 &&
1121        MI->getOperand(3).getImm() == 0) {
1122      FrameIndex = MI->getOperand(1).getIndex();
1123      return MI->getOperand(0).getReg();
1124    }
1125    break;
1126  case ARM::LDRi12:
1127  case ARM::t2LDRi12:
1128  case ARM::tLDRspi:
1129  case ARM::VLDRD:
1130  case ARM::VLDRS:
1131    if (MI->getOperand(1).isFI() &&
1132        MI->getOperand(2).isImm() &&
1133        MI->getOperand(2).getImm() == 0) {
1134      FrameIndex = MI->getOperand(1).getIndex();
1135      return MI->getOperand(0).getReg();
1136    }
1137    break;
1138  case ARM::VLD1q64:
1139  case ARM::VLD1d64TPseudo:
1140  case ARM::VLD1d64QPseudo:
1141    if (MI->getOperand(1).isFI() &&
1142        MI->getOperand(0).getSubReg() == 0) {
1143      FrameIndex = MI->getOperand(1).getIndex();
1144      return MI->getOperand(0).getReg();
1145    }
1146    break;
1147  case ARM::VLDMQIA:
1148    if (MI->getOperand(1).isFI() &&
1149        MI->getOperand(0).getSubReg() == 0) {
1150      FrameIndex = MI->getOperand(1).getIndex();
1151      return MI->getOperand(0).getReg();
1152    }
1153    break;
1154  }
1155
1156  return 0;
1157}
1158
1159unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1160                                             int &FrameIndex) const {
1161  const MachineMemOperand *Dummy;
1162  return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1163}
1164
1165bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1166  // This hook gets to expand COPY instructions before they become
1167  // copyPhysReg() calls.  Look for VMOVS instructions that can legally be
1168  // widened to VMOVD.  We prefer the VMOVD when possible because it may be
1169  // changed into a VORR that can go down the NEON pipeline.
1170  if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15())
1171    return false;
1172
1173  // Look for a copy between even S-registers.  That is where we keep floats
1174  // when using NEON v2f32 instructions for f32 arithmetic.
1175  unsigned DstRegS = MI->getOperand(0).getReg();
1176  unsigned SrcRegS = MI->getOperand(1).getReg();
1177  if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1178    return false;
1179
1180  const TargetRegisterInfo *TRI = &getRegisterInfo();
1181  unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1182                                              &ARM::DPRRegClass);
1183  unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1184                                              &ARM::DPRRegClass);
1185  if (!DstRegD || !SrcRegD)
1186    return false;
1187
1188  // We want to widen this into a DstRegD = VMOVD SrcRegD copy.  This is only
1189  // legal if the COPY already defines the full DstRegD, and it isn't a
1190  // sub-register insertion.
1191  if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1192    return false;
1193
1194  // A dead copy shouldn't show up here, but reject it just in case.
1195  if (MI->getOperand(0).isDead())
1196    return false;
1197
1198  // All clear, widen the COPY.
1199  DEBUG(dbgs() << "widening:    " << *MI);
1200  MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1201
1202  // Get rid of the old <imp-def> of DstRegD.  Leave it if it defines a Q-reg
1203  // or some other super-register.
1204  int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1205  if (ImpDefIdx != -1)
1206    MI->RemoveOperand(ImpDefIdx);
1207
1208  // Change the opcode and operands.
1209  MI->setDesc(get(ARM::VMOVD));
1210  MI->getOperand(0).setReg(DstRegD);
1211  MI->getOperand(1).setReg(SrcRegD);
1212  AddDefaultPred(MIB);
1213
1214  // We are now reading SrcRegD instead of SrcRegS.  This may upset the
1215  // register scavenger and machine verifier, so we need to indicate that we
1216  // are reading an undefined value from SrcRegD, but a proper value from
1217  // SrcRegS.
1218  MI->getOperand(1).setIsUndef();
1219  MIB.addReg(SrcRegS, RegState::Implicit);
1220
1221  // SrcRegD may actually contain an unrelated value in the ssub_1
1222  // sub-register.  Don't kill it.  Only kill the ssub_0 sub-register.
1223  if (MI->getOperand(1).isKill()) {
1224    MI->getOperand(1).setIsKill(false);
1225    MI->addRegisterKilled(SrcRegS, TRI, true);
1226  }
1227
1228  DEBUG(dbgs() << "replaced by: " << *MI);
1229  return true;
1230}
1231
1232/// Create a copy of a const pool value. Update CPI to the new index and return
1233/// the label UID.
1234static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1235  MachineConstantPool *MCP = MF.getConstantPool();
1236  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1237
1238  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1239  assert(MCPE.isMachineConstantPoolEntry() &&
1240         "Expecting a machine constantpool entry!");
1241  ARMConstantPoolValue *ACPV =
1242    static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1243
1244  unsigned PCLabelId = AFI->createPICLabelUId();
1245  ARMConstantPoolValue *NewCPV = 0;
1246  // FIXME: The below assumes PIC relocation model and that the function
1247  // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1248  // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1249  // instructions, so that's probably OK, but is PIC always correct when
1250  // we get here?
1251  if (ACPV->isGlobalValue())
1252    NewCPV = ARMConstantPoolConstant::
1253      Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1254             ARMCP::CPValue, 4);
1255  else if (ACPV->isExtSymbol())
1256    NewCPV = ARMConstantPoolSymbol::
1257      Create(MF.getFunction()->getContext(),
1258             cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1259  else if (ACPV->isBlockAddress())
1260    NewCPV = ARMConstantPoolConstant::
1261      Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1262             ARMCP::CPBlockAddress, 4);
1263  else if (ACPV->isLSDA())
1264    NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1265                                             ARMCP::CPLSDA, 4);
1266  else if (ACPV->isMachineBasicBlock())
1267    NewCPV = ARMConstantPoolMBB::
1268      Create(MF.getFunction()->getContext(),
1269             cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1270  else
1271    llvm_unreachable("Unexpected ARM constantpool value type!!");
1272  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1273  return PCLabelId;
1274}
1275
1276void ARMBaseInstrInfo::
1277reMaterialize(MachineBasicBlock &MBB,
1278              MachineBasicBlock::iterator I,
1279              unsigned DestReg, unsigned SubIdx,
1280              const MachineInstr *Orig,
1281              const TargetRegisterInfo &TRI) const {
1282  unsigned Opcode = Orig->getOpcode();
1283  switch (Opcode) {
1284  default: {
1285    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1286    MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1287    MBB.insert(I, MI);
1288    break;
1289  }
1290  case ARM::tLDRpci_pic:
1291  case ARM::t2LDRpci_pic: {
1292    MachineFunction &MF = *MBB.getParent();
1293    unsigned CPI = Orig->getOperand(1).getIndex();
1294    unsigned PCLabelId = duplicateCPV(MF, CPI);
1295    MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1296                                      DestReg)
1297      .addConstantPoolIndex(CPI).addImm(PCLabelId);
1298    MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1299    break;
1300  }
1301  }
1302}
1303
1304MachineInstr *
1305ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1306  MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1307  switch(Orig->getOpcode()) {
1308  case ARM::tLDRpci_pic:
1309  case ARM::t2LDRpci_pic: {
1310    unsigned CPI = Orig->getOperand(1).getIndex();
1311    unsigned PCLabelId = duplicateCPV(MF, CPI);
1312    Orig->getOperand(1).setIndex(CPI);
1313    Orig->getOperand(2).setImm(PCLabelId);
1314    break;
1315  }
1316  }
1317  return MI;
1318}
1319
1320bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1321                                        const MachineInstr *MI1,
1322                                        const MachineRegisterInfo *MRI) const {
1323  int Opcode = MI0->getOpcode();
1324  if (Opcode == ARM::t2LDRpci ||
1325      Opcode == ARM::t2LDRpci_pic ||
1326      Opcode == ARM::tLDRpci ||
1327      Opcode == ARM::tLDRpci_pic ||
1328      Opcode == ARM::MOV_ga_dyn ||
1329      Opcode == ARM::MOV_ga_pcrel ||
1330      Opcode == ARM::MOV_ga_pcrel_ldr ||
1331      Opcode == ARM::t2MOV_ga_dyn ||
1332      Opcode == ARM::t2MOV_ga_pcrel) {
1333    if (MI1->getOpcode() != Opcode)
1334      return false;
1335    if (MI0->getNumOperands() != MI1->getNumOperands())
1336      return false;
1337
1338    const MachineOperand &MO0 = MI0->getOperand(1);
1339    const MachineOperand &MO1 = MI1->getOperand(1);
1340    if (MO0.getOffset() != MO1.getOffset())
1341      return false;
1342
1343    if (Opcode == ARM::MOV_ga_dyn ||
1344        Opcode == ARM::MOV_ga_pcrel ||
1345        Opcode == ARM::MOV_ga_pcrel_ldr ||
1346        Opcode == ARM::t2MOV_ga_dyn ||
1347        Opcode == ARM::t2MOV_ga_pcrel)
1348      // Ignore the PC labels.
1349      return MO0.getGlobal() == MO1.getGlobal();
1350
1351    const MachineFunction *MF = MI0->getParent()->getParent();
1352    const MachineConstantPool *MCP = MF->getConstantPool();
1353    int CPI0 = MO0.getIndex();
1354    int CPI1 = MO1.getIndex();
1355    const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1356    const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1357    bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1358    bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1359    if (isARMCP0 && isARMCP1) {
1360      ARMConstantPoolValue *ACPV0 =
1361        static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1362      ARMConstantPoolValue *ACPV1 =
1363        static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1364      return ACPV0->hasSameValue(ACPV1);
1365    } else if (!isARMCP0 && !isARMCP1) {
1366      return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1367    }
1368    return false;
1369  } else if (Opcode == ARM::PICLDR) {
1370    if (MI1->getOpcode() != Opcode)
1371      return false;
1372    if (MI0->getNumOperands() != MI1->getNumOperands())
1373      return false;
1374
1375    unsigned Addr0 = MI0->getOperand(1).getReg();
1376    unsigned Addr1 = MI1->getOperand(1).getReg();
1377    if (Addr0 != Addr1) {
1378      if (!MRI ||
1379          !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1380          !TargetRegisterInfo::isVirtualRegister(Addr1))
1381        return false;
1382
1383      // This assumes SSA form.
1384      MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1385      MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1386      // Check if the loaded value, e.g. a constantpool of a global address, are
1387      // the same.
1388      if (!produceSameValue(Def0, Def1, MRI))
1389        return false;
1390    }
1391
1392    for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1393      // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1394      const MachineOperand &MO0 = MI0->getOperand(i);
1395      const MachineOperand &MO1 = MI1->getOperand(i);
1396      if (!MO0.isIdenticalTo(MO1))
1397        return false;
1398    }
1399    return true;
1400  }
1401
1402  return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1403}
1404
1405/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1406/// determine if two loads are loading from the same base address. It should
1407/// only return true if the base pointers are the same and the only differences
1408/// between the two addresses is the offset. It also returns the offsets by
1409/// reference.
1410///
1411/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1412/// is permanently disabled.
1413bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1414                                               int64_t &Offset1,
1415                                               int64_t &Offset2) const {
1416  // Don't worry about Thumb: just ARM and Thumb2.
1417  if (Subtarget.isThumb1Only()) return false;
1418
1419  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1420    return false;
1421
1422  switch (Load1->getMachineOpcode()) {
1423  default:
1424    return false;
1425  case ARM::LDRi12:
1426  case ARM::LDRBi12:
1427  case ARM::LDRD:
1428  case ARM::LDRH:
1429  case ARM::LDRSB:
1430  case ARM::LDRSH:
1431  case ARM::VLDRD:
1432  case ARM::VLDRS:
1433  case ARM::t2LDRi8:
1434  case ARM::t2LDRBi8:
1435  case ARM::t2LDRDi8:
1436  case ARM::t2LDRSHi8:
1437  case ARM::t2LDRi12:
1438  case ARM::t2LDRBi12:
1439  case ARM::t2LDRSHi12:
1440    break;
1441  }
1442
1443  switch (Load2->getMachineOpcode()) {
1444  default:
1445    return false;
1446  case ARM::LDRi12:
1447  case ARM::LDRBi12:
1448  case ARM::LDRD:
1449  case ARM::LDRH:
1450  case ARM::LDRSB:
1451  case ARM::LDRSH:
1452  case ARM::VLDRD:
1453  case ARM::VLDRS:
1454  case ARM::t2LDRi8:
1455  case ARM::t2LDRBi8:
1456  case ARM::t2LDRSHi8:
1457  case ARM::t2LDRi12:
1458  case ARM::t2LDRBi12:
1459  case ARM::t2LDRSHi12:
1460    break;
1461  }
1462
1463  // Check if base addresses and chain operands match.
1464  if (Load1->getOperand(0) != Load2->getOperand(0) ||
1465      Load1->getOperand(4) != Load2->getOperand(4))
1466    return false;
1467
1468  // Index should be Reg0.
1469  if (Load1->getOperand(3) != Load2->getOperand(3))
1470    return false;
1471
1472  // Determine the offsets.
1473  if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1474      isa<ConstantSDNode>(Load2->getOperand(1))) {
1475    Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1476    Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1477    return true;
1478  }
1479
1480  return false;
1481}
1482
1483/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1484/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1485/// be scheduled togther. On some targets if two loads are loading from
1486/// addresses in the same cache line, it's better if they are scheduled
1487/// together. This function takes two integers that represent the load offsets
1488/// from the common base address. It returns true if it decides it's desirable
1489/// to schedule the two loads together. "NumLoads" is the number of loads that
1490/// have already been scheduled after Load1.
1491///
1492/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1493/// is permanently disabled.
1494bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1495                                               int64_t Offset1, int64_t Offset2,
1496                                               unsigned NumLoads) const {
1497  // Don't worry about Thumb: just ARM and Thumb2.
1498  if (Subtarget.isThumb1Only()) return false;
1499
1500  assert(Offset2 > Offset1);
1501
1502  if ((Offset2 - Offset1) / 8 > 64)
1503    return false;
1504
1505  // Check if the machine opcodes are different. If they are different
1506  // then we consider them to not be of the same base address,
1507  // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1508  // In this case, they are considered to be the same because they are different
1509  // encoding forms of the same basic instruction.
1510  if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1511      !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1512         Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1513        (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1514         Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1515    return false;  // FIXME: overly conservative?
1516
1517  // Four loads in a row should be sufficient.
1518  if (NumLoads >= 3)
1519    return false;
1520
1521  return true;
1522}
1523
1524bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1525                                            const MachineBasicBlock *MBB,
1526                                            const MachineFunction &MF) const {
1527  // Debug info is never a scheduling boundary. It's necessary to be explicit
1528  // due to the special treatment of IT instructions below, otherwise a
1529  // dbg_value followed by an IT will result in the IT instruction being
1530  // considered a scheduling hazard, which is wrong. It should be the actual
1531  // instruction preceding the dbg_value instruction(s), just like it is
1532  // when debug info is not present.
1533  if (MI->isDebugValue())
1534    return false;
1535
1536  // Terminators and labels can't be scheduled around.
1537  if (MI->isTerminator() || MI->isLabel())
1538    return true;
1539
1540  // Treat the start of the IT block as a scheduling boundary, but schedule
1541  // t2IT along with all instructions following it.
1542  // FIXME: This is a big hammer. But the alternative is to add all potential
1543  // true and anti dependencies to IT block instructions as implicit operands
1544  // to the t2IT instruction. The added compile time and complexity does not
1545  // seem worth it.
1546  MachineBasicBlock::const_iterator I = MI;
1547  // Make sure to skip any dbg_value instructions
1548  while (++I != MBB->end() && I->isDebugValue())
1549    ;
1550  if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1551    return true;
1552
1553  // Don't attempt to schedule around any instruction that defines
1554  // a stack-oriented pointer, as it's unlikely to be profitable. This
1555  // saves compile time, because it doesn't require every single
1556  // stack slot reference to depend on the instruction that does the
1557  // modification.
1558  // Calls don't actually change the stack pointer, even if they have imp-defs.
1559  // No ARM calling conventions change the stack pointer. (X86 calling
1560  // conventions sometimes do).
1561  if (!MI->isCall() && MI->definesRegister(ARM::SP))
1562    return true;
1563
1564  return false;
1565}
1566
1567bool ARMBaseInstrInfo::
1568isProfitableToIfCvt(MachineBasicBlock &MBB,
1569                    unsigned NumCycles, unsigned ExtraPredCycles,
1570                    const BranchProbability &Probability) const {
1571  if (!NumCycles)
1572    return false;
1573
1574  // Attempt to estimate the relative costs of predication versus branching.
1575  unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1576  UnpredCost /= Probability.getDenominator();
1577  UnpredCost += 1; // The branch itself
1578  UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1579
1580  return (NumCycles + ExtraPredCycles) <= UnpredCost;
1581}
1582
1583bool ARMBaseInstrInfo::
1584isProfitableToIfCvt(MachineBasicBlock &TMBB,
1585                    unsigned TCycles, unsigned TExtra,
1586                    MachineBasicBlock &FMBB,
1587                    unsigned FCycles, unsigned FExtra,
1588                    const BranchProbability &Probability) const {
1589  if (!TCycles || !FCycles)
1590    return false;
1591
1592  // Attempt to estimate the relative costs of predication versus branching.
1593  unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1594  TUnpredCost /= Probability.getDenominator();
1595
1596  uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1597  unsigned FUnpredCost = Comp * FCycles;
1598  FUnpredCost /= Probability.getDenominator();
1599
1600  unsigned UnpredCost = TUnpredCost + FUnpredCost;
1601  UnpredCost += 1; // The branch itself
1602  UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1603
1604  return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1605}
1606
1607bool
1608ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1609                                            MachineBasicBlock &FMBB) const {
1610  // Reduce false anti-dependencies to let Swift's out-of-order execution
1611  // engine do its thing.
1612  return Subtarget.isSwift();
1613}
1614
1615/// getInstrPredicate - If instruction is predicated, returns its predicate
1616/// condition, otherwise returns AL. It also returns the condition code
1617/// register by reference.
1618ARMCC::CondCodes
1619llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1620  int PIdx = MI->findFirstPredOperandIdx();
1621  if (PIdx == -1) {
1622    PredReg = 0;
1623    return ARMCC::AL;
1624  }
1625
1626  PredReg = MI->getOperand(PIdx+1).getReg();
1627  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1628}
1629
1630
1631int llvm::getMatchingCondBranchOpcode(int Opc) {
1632  if (Opc == ARM::B)
1633    return ARM::Bcc;
1634  if (Opc == ARM::tB)
1635    return ARM::tBcc;
1636  if (Opc == ARM::t2B)
1637    return ARM::t2Bcc;
1638
1639  llvm_unreachable("Unknown unconditional branch opcode!");
1640}
1641
1642/// commuteInstruction - Handle commutable instructions.
1643MachineInstr *
1644ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1645  switch (MI->getOpcode()) {
1646  case ARM::MOVCCr:
1647  case ARM::t2MOVCCr: {
1648    // MOVCC can be commuted by inverting the condition.
1649    unsigned PredReg = 0;
1650    ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1651    // MOVCC AL can't be inverted. Shouldn't happen.
1652    if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1653      return NULL;
1654    MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1655    if (!MI)
1656      return NULL;
1657    // After swapping the MOVCC operands, also invert the condition.
1658    MI->getOperand(MI->findFirstPredOperandIdx())
1659      .setImm(ARMCC::getOppositeCondition(CC));
1660    return MI;
1661  }
1662  }
1663  return TargetInstrInfo::commuteInstruction(MI, NewMI);
1664}
1665
1666/// Identify instructions that can be folded into a MOVCC instruction, and
1667/// return the defining instruction.
1668static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1669                                      const MachineRegisterInfo &MRI,
1670                                      const TargetInstrInfo *TII) {
1671  if (!TargetRegisterInfo::isVirtualRegister(Reg))
1672    return 0;
1673  if (!MRI.hasOneNonDBGUse(Reg))
1674    return 0;
1675  MachineInstr *MI = MRI.getVRegDef(Reg);
1676  if (!MI)
1677    return 0;
1678  // MI is folded into the MOVCC by predicating it.
1679  if (!MI->isPredicable())
1680    return 0;
1681  // Check if MI has any non-dead defs or physreg uses. This also detects
1682  // predicated instructions which will be reading CPSR.
1683  for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1684    const MachineOperand &MO = MI->getOperand(i);
1685    // Reject frame index operands, PEI can't handle the predicated pseudos.
1686    if (MO.isFI() || MO.isCPI() || MO.isJTI())
1687      return 0;
1688    if (!MO.isReg())
1689      continue;
1690    // MI can't have any tied operands, that would conflict with predication.
1691    if (MO.isTied())
1692      return 0;
1693    if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1694      return 0;
1695    if (MO.isDef() && !MO.isDead())
1696      return 0;
1697  }
1698  bool DontMoveAcrossStores = true;
1699  if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores))
1700    return 0;
1701  return MI;
1702}
1703
1704bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1705                                     SmallVectorImpl<MachineOperand> &Cond,
1706                                     unsigned &TrueOp, unsigned &FalseOp,
1707                                     bool &Optimizable) const {
1708  assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1709         "Unknown select instruction");
1710  // MOVCC operands:
1711  // 0: Def.
1712  // 1: True use.
1713  // 2: False use.
1714  // 3: Condition code.
1715  // 4: CPSR use.
1716  TrueOp = 1;
1717  FalseOp = 2;
1718  Cond.push_back(MI->getOperand(3));
1719  Cond.push_back(MI->getOperand(4));
1720  // We can always fold a def.
1721  Optimizable = true;
1722  return false;
1723}
1724
1725MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1726                                               bool PreferFalse) const {
1727  assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1728         "Unknown select instruction");
1729  MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1730  MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1731  bool Invert = !DefMI;
1732  if (!DefMI)
1733    DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1734  if (!DefMI)
1735    return 0;
1736
1737  // Find new register class to use.
1738  MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1739  unsigned       DestReg  = MI->getOperand(0).getReg();
1740  const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1741  if (!MRI.constrainRegClass(DestReg, PreviousClass))
1742    return 0;
1743
1744  // Create a new predicated version of DefMI.
1745  // Rfalse is the first use.
1746  MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1747                                      DefMI->getDesc(), DestReg);
1748
1749  // Copy all the DefMI operands, excluding its (null) predicate.
1750  const MCInstrDesc &DefDesc = DefMI->getDesc();
1751  for (unsigned i = 1, e = DefDesc.getNumOperands();
1752       i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1753    NewMI.addOperand(DefMI->getOperand(i));
1754
1755  unsigned CondCode = MI->getOperand(3).getImm();
1756  if (Invert)
1757    NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1758  else
1759    NewMI.addImm(CondCode);
1760  NewMI.addOperand(MI->getOperand(4));
1761
1762  // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1763  if (NewMI->hasOptionalDef())
1764    AddDefaultCC(NewMI);
1765
1766  // The output register value when the predicate is false is an implicit
1767  // register operand tied to the first def.
1768  // The tie makes the register allocator ensure the FalseReg is allocated the
1769  // same register as operand 0.
1770  FalseReg.setImplicit();
1771  NewMI.addOperand(FalseReg);
1772  NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1773
1774  // The caller will erase MI, but not DefMI.
1775  DefMI->eraseFromParent();
1776  return NewMI;
1777}
1778
1779/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1780/// instruction is encoded with an 'S' bit is determined by the optional CPSR
1781/// def operand.
1782///
1783/// This will go away once we can teach tblgen how to set the optional CPSR def
1784/// operand itself.
1785struct AddSubFlagsOpcodePair {
1786  uint16_t PseudoOpc;
1787  uint16_t MachineOpc;
1788};
1789
1790static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1791  {ARM::ADDSri, ARM::ADDri},
1792  {ARM::ADDSrr, ARM::ADDrr},
1793  {ARM::ADDSrsi, ARM::ADDrsi},
1794  {ARM::ADDSrsr, ARM::ADDrsr},
1795
1796  {ARM::SUBSri, ARM::SUBri},
1797  {ARM::SUBSrr, ARM::SUBrr},
1798  {ARM::SUBSrsi, ARM::SUBrsi},
1799  {ARM::SUBSrsr, ARM::SUBrsr},
1800
1801  {ARM::RSBSri, ARM::RSBri},
1802  {ARM::RSBSrsi, ARM::RSBrsi},
1803  {ARM::RSBSrsr, ARM::RSBrsr},
1804
1805  {ARM::t2ADDSri, ARM::t2ADDri},
1806  {ARM::t2ADDSrr, ARM::t2ADDrr},
1807  {ARM::t2ADDSrs, ARM::t2ADDrs},
1808
1809  {ARM::t2SUBSri, ARM::t2SUBri},
1810  {ARM::t2SUBSrr, ARM::t2SUBrr},
1811  {ARM::t2SUBSrs, ARM::t2SUBrs},
1812
1813  {ARM::t2RSBSri, ARM::t2RSBri},
1814  {ARM::t2RSBSrs, ARM::t2RSBrs},
1815};
1816
1817unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1818  for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1819    if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1820      return AddSubFlagsOpcodeMap[i].MachineOpc;
1821  return 0;
1822}
1823
1824void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1825                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1826                               unsigned DestReg, unsigned BaseReg, int NumBytes,
1827                               ARMCC::CondCodes Pred, unsigned PredReg,
1828                               const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1829  if (NumBytes == 0 && DestReg != BaseReg) {
1830    BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
1831      .addReg(BaseReg, RegState::Kill)
1832      .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1833      .setMIFlags(MIFlags);
1834    return;
1835  }
1836
1837  bool isSub = NumBytes < 0;
1838  if (isSub) NumBytes = -NumBytes;
1839
1840  while (NumBytes) {
1841    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1842    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1843    assert(ThisVal && "Didn't extract field correctly");
1844
1845    // We will handle these bits from offset, clear them.
1846    NumBytes &= ~ThisVal;
1847
1848    assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1849
1850    // Build the new ADD / SUB.
1851    unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1852    BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1853      .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1854      .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1855      .setMIFlags(MIFlags);
1856    BaseReg = DestReg;
1857  }
1858}
1859
1860bool llvm::tryFoldSPUpdateIntoPushPop(MachineFunction &MF,
1861                                      MachineInstr *MI,
1862                                      unsigned NumBytes) {
1863  // This optimisation potentially adds lots of load and store
1864  // micro-operations, it's only really a great benefit to code-size.
1865  if (!MF.getFunction()->hasFnAttribute(Attribute::MinSize))
1866    return false;
1867
1868  // If only one register is pushed/popped, LLVM can use an LDR/STR
1869  // instead. We can't modify those so make sure we're dealing with an
1870  // instruction we understand.
1871  bool IsPop = isPopOpcode(MI->getOpcode());
1872  bool IsPush = isPushOpcode(MI->getOpcode());
1873  if (!IsPush && !IsPop)
1874    return false;
1875
1876  bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
1877                      MI->getOpcode() == ARM::VLDMDIA_UPD;
1878  bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
1879                     MI->getOpcode() == ARM::tPOP ||
1880                     MI->getOpcode() == ARM::tPOP_RET;
1881
1882  assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
1883                          MI->getOperand(1).getReg() == ARM::SP)) &&
1884         "trying to fold sp update into non-sp-updating push/pop");
1885
1886  // The VFP push & pop act on D-registers, so we can only fold an adjustment
1887  // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
1888  // if this is violated.
1889  if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
1890    return false;
1891
1892  // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
1893  // pred) so the list starts at 4. Thumb1 starts after the predicate.
1894  int RegListIdx = IsT1PushPop ? 2 : 4;
1895
1896  // Calculate the space we'll need in terms of registers.
1897  unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
1898  unsigned RD0Reg, RegsNeeded;
1899  if (IsVFPPushPop) {
1900    RD0Reg = ARM::D0;
1901    RegsNeeded = NumBytes / 8;
1902  } else {
1903    RD0Reg = ARM::R0;
1904    RegsNeeded = NumBytes / 4;
1905  }
1906
1907  // We're going to have to strip all list operands off before
1908  // re-adding them since the order matters, so save the existing ones
1909  // for later.
1910  SmallVector<MachineOperand, 4> RegList;
1911  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
1912    RegList.push_back(MI->getOperand(i));
1913
1914  MachineBasicBlock *MBB = MI->getParent();
1915  const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
1916  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
1917
1918  // Now try to find enough space in the reglist to allocate NumBytes.
1919  for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
1920       --CurReg) {
1921    if (!IsPop) {
1922      // Pushing any register is completely harmless, mark the
1923      // register involved as undef since we don't care about it in
1924      // the slightest.
1925      RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
1926                                                  false, false, true));
1927      --RegsNeeded;
1928      continue;
1929    }
1930
1931    // However, we can only pop an extra register if it's not live. For
1932    // registers live within the function we might clobber a return value
1933    // register; the other way a register can be live here is if it's
1934    // callee-saved.
1935    if (isCalleeSavedRegister(CurReg, CSRegs) ||
1936        MBB->computeRegisterLiveness(TRI, CurReg, MI) !=
1937            MachineBasicBlock::LQR_Dead) {
1938      // VFP pops don't allow holes in the register list, so any skip is fatal
1939      // for our transformation. GPR pops do, so we should just keep looking.
1940      if (IsVFPPushPop)
1941        return false;
1942      else
1943        continue;
1944    }
1945
1946    // Mark the unimportant registers as <def,dead> in the POP.
1947    RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
1948                                                true));
1949    --RegsNeeded;
1950  }
1951
1952  if (RegsNeeded > 0)
1953    return false;
1954
1955  // Finally we know we can profitably perform the optimisation so go
1956  // ahead: strip all existing registers off and add them back again
1957  // in the right order.
1958  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
1959    MI->RemoveOperand(i);
1960
1961  // Add the complete list back in.
1962  MachineInstrBuilder MIB(MF, &*MI);
1963  for (int i = RegList.size() - 1; i >= 0; --i)
1964    MIB.addOperand(RegList[i]);
1965
1966  return true;
1967}
1968
1969bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1970                                unsigned FrameReg, int &Offset,
1971                                const ARMBaseInstrInfo &TII) {
1972  unsigned Opcode = MI.getOpcode();
1973  const MCInstrDesc &Desc = MI.getDesc();
1974  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1975  bool isSub = false;
1976
1977  // Memory operands in inline assembly always use AddrMode2.
1978  if (Opcode == ARM::INLINEASM)
1979    AddrMode = ARMII::AddrMode2;
1980
1981  if (Opcode == ARM::ADDri) {
1982    Offset += MI.getOperand(FrameRegIdx+1).getImm();
1983    if (Offset == 0) {
1984      // Turn it into a move.
1985      MI.setDesc(TII.get(ARM::MOVr));
1986      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1987      MI.RemoveOperand(FrameRegIdx+1);
1988      Offset = 0;
1989      return true;
1990    } else if (Offset < 0) {
1991      Offset = -Offset;
1992      isSub = true;
1993      MI.setDesc(TII.get(ARM::SUBri));
1994    }
1995
1996    // Common case: small offset, fits into instruction.
1997    if (ARM_AM::getSOImmVal(Offset) != -1) {
1998      // Replace the FrameIndex with sp / fp
1999      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2000      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2001      Offset = 0;
2002      return true;
2003    }
2004
2005    // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2006    // as possible.
2007    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2008    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2009
2010    // We will handle these bits from offset, clear them.
2011    Offset &= ~ThisImmVal;
2012
2013    // Get the properly encoded SOImmVal field.
2014    assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2015           "Bit extraction didn't work?");
2016    MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2017 } else {
2018    unsigned ImmIdx = 0;
2019    int InstrOffs = 0;
2020    unsigned NumBits = 0;
2021    unsigned Scale = 1;
2022    switch (AddrMode) {
2023    case ARMII::AddrMode_i12: {
2024      ImmIdx = FrameRegIdx + 1;
2025      InstrOffs = MI.getOperand(ImmIdx).getImm();
2026      NumBits = 12;
2027      break;
2028    }
2029    case ARMII::AddrMode2: {
2030      ImmIdx = FrameRegIdx+2;
2031      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2032      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2033        InstrOffs *= -1;
2034      NumBits = 12;
2035      break;
2036    }
2037    case ARMII::AddrMode3: {
2038      ImmIdx = FrameRegIdx+2;
2039      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2040      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2041        InstrOffs *= -1;
2042      NumBits = 8;
2043      break;
2044    }
2045    case ARMII::AddrMode4:
2046    case ARMII::AddrMode6:
2047      // Can't fold any offset even if it's zero.
2048      return false;
2049    case ARMII::AddrMode5: {
2050      ImmIdx = FrameRegIdx+1;
2051      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2052      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2053        InstrOffs *= -1;
2054      NumBits = 8;
2055      Scale = 4;
2056      break;
2057    }
2058    default:
2059      llvm_unreachable("Unsupported addressing mode!");
2060    }
2061
2062    Offset += InstrOffs * Scale;
2063    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2064    if (Offset < 0) {
2065      Offset = -Offset;
2066      isSub = true;
2067    }
2068
2069    // Attempt to fold address comp. if opcode has offset bits
2070    if (NumBits > 0) {
2071      // Common case: small offset, fits into instruction.
2072      MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2073      int ImmedOffset = Offset / Scale;
2074      unsigned Mask = (1 << NumBits) - 1;
2075      if ((unsigned)Offset <= Mask * Scale) {
2076        // Replace the FrameIndex with sp
2077        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2078        // FIXME: When addrmode2 goes away, this will simplify (like the
2079        // T2 version), as the LDR.i12 versions don't need the encoding
2080        // tricks for the offset value.
2081        if (isSub) {
2082          if (AddrMode == ARMII::AddrMode_i12)
2083            ImmedOffset = -ImmedOffset;
2084          else
2085            ImmedOffset |= 1 << NumBits;
2086        }
2087        ImmOp.ChangeToImmediate(ImmedOffset);
2088        Offset = 0;
2089        return true;
2090      }
2091
2092      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2093      ImmedOffset = ImmedOffset & Mask;
2094      if (isSub) {
2095        if (AddrMode == ARMII::AddrMode_i12)
2096          ImmedOffset = -ImmedOffset;
2097        else
2098          ImmedOffset |= 1 << NumBits;
2099      }
2100      ImmOp.ChangeToImmediate(ImmedOffset);
2101      Offset &= ~(Mask*Scale);
2102    }
2103  }
2104
2105  Offset = (isSub) ? -Offset : Offset;
2106  return Offset == 0;
2107}
2108
2109/// analyzeCompare - For a comparison instruction, return the source registers
2110/// in SrcReg and SrcReg2 if having two register operands, and the value it
2111/// compares against in CmpValue. Return true if the comparison instruction
2112/// can be analyzed.
2113bool ARMBaseInstrInfo::
2114analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2115               int &CmpMask, int &CmpValue) const {
2116  switch (MI->getOpcode()) {
2117  default: break;
2118  case ARM::CMPri:
2119  case ARM::t2CMPri:
2120    SrcReg = MI->getOperand(0).getReg();
2121    SrcReg2 = 0;
2122    CmpMask = ~0;
2123    CmpValue = MI->getOperand(1).getImm();
2124    return true;
2125  case ARM::CMPrr:
2126  case ARM::t2CMPrr:
2127    SrcReg = MI->getOperand(0).getReg();
2128    SrcReg2 = MI->getOperand(1).getReg();
2129    CmpMask = ~0;
2130    CmpValue = 0;
2131    return true;
2132  case ARM::TSTri:
2133  case ARM::t2TSTri:
2134    SrcReg = MI->getOperand(0).getReg();
2135    SrcReg2 = 0;
2136    CmpMask = MI->getOperand(1).getImm();
2137    CmpValue = 0;
2138    return true;
2139  }
2140
2141  return false;
2142}
2143
2144/// isSuitableForMask - Identify a suitable 'and' instruction that
2145/// operates on the given source register and applies the same mask
2146/// as a 'tst' instruction. Provide a limited look-through for copies.
2147/// When successful, MI will hold the found instruction.
2148static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2149                              int CmpMask, bool CommonUse) {
2150  switch (MI->getOpcode()) {
2151    case ARM::ANDri:
2152    case ARM::t2ANDri:
2153      if (CmpMask != MI->getOperand(2).getImm())
2154        return false;
2155      if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2156        return true;
2157      break;
2158    case ARM::COPY: {
2159      // Walk down one instruction which is potentially an 'and'.
2160      const MachineInstr &Copy = *MI;
2161      MachineBasicBlock::iterator AND(
2162        llvm::next(MachineBasicBlock::iterator(MI)));
2163      if (AND == MI->getParent()->end()) return false;
2164      MI = AND;
2165      return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
2166                               CmpMask, true);
2167    }
2168  }
2169
2170  return false;
2171}
2172
2173/// getSwappedCondition - assume the flags are set by MI(a,b), return
2174/// the condition code if we modify the instructions such that flags are
2175/// set by MI(b,a).
2176inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2177  switch (CC) {
2178  default: return ARMCC::AL;
2179  case ARMCC::EQ: return ARMCC::EQ;
2180  case ARMCC::NE: return ARMCC::NE;
2181  case ARMCC::HS: return ARMCC::LS;
2182  case ARMCC::LO: return ARMCC::HI;
2183  case ARMCC::HI: return ARMCC::LO;
2184  case ARMCC::LS: return ARMCC::HS;
2185  case ARMCC::GE: return ARMCC::LE;
2186  case ARMCC::LT: return ARMCC::GT;
2187  case ARMCC::GT: return ARMCC::LT;
2188  case ARMCC::LE: return ARMCC::GE;
2189  }
2190}
2191
2192/// isRedundantFlagInstr - check whether the first instruction, whose only
2193/// purpose is to update flags, can be made redundant.
2194/// CMPrr can be made redundant by SUBrr if the operands are the same.
2195/// CMPri can be made redundant by SUBri if the operands are the same.
2196/// This function can be extended later on.
2197inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2198                                        unsigned SrcReg2, int ImmValue,
2199                                        MachineInstr *OI) {
2200  if ((CmpI->getOpcode() == ARM::CMPrr ||
2201       CmpI->getOpcode() == ARM::t2CMPrr) &&
2202      (OI->getOpcode() == ARM::SUBrr ||
2203       OI->getOpcode() == ARM::t2SUBrr) &&
2204      ((OI->getOperand(1).getReg() == SrcReg &&
2205        OI->getOperand(2).getReg() == SrcReg2) ||
2206       (OI->getOperand(1).getReg() == SrcReg2 &&
2207        OI->getOperand(2).getReg() == SrcReg)))
2208    return true;
2209
2210  if ((CmpI->getOpcode() == ARM::CMPri ||
2211       CmpI->getOpcode() == ARM::t2CMPri) &&
2212      (OI->getOpcode() == ARM::SUBri ||
2213       OI->getOpcode() == ARM::t2SUBri) &&
2214      OI->getOperand(1).getReg() == SrcReg &&
2215      OI->getOperand(2).getImm() == ImmValue)
2216    return true;
2217  return false;
2218}
2219
2220/// optimizeCompareInstr - Convert the instruction supplying the argument to the
2221/// comparison into one that sets the zero bit in the flags register;
2222/// Remove a redundant Compare instruction if an earlier instruction can set the
2223/// flags in the same way as Compare.
2224/// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2225/// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2226/// condition code of instructions which use the flags.
2227bool ARMBaseInstrInfo::
2228optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2229                     int CmpMask, int CmpValue,
2230                     const MachineRegisterInfo *MRI) const {
2231  // Get the unique definition of SrcReg.
2232  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2233  if (!MI) return false;
2234
2235  // Masked compares sometimes use the same register as the corresponding 'and'.
2236  if (CmpMask != ~0) {
2237    if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2238      MI = 0;
2239      for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
2240           UE = MRI->use_end(); UI != UE; ++UI) {
2241        if (UI->getParent() != CmpInstr->getParent()) continue;
2242        MachineInstr *PotentialAND = &*UI;
2243        if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2244            isPredicated(PotentialAND))
2245          continue;
2246        MI = PotentialAND;
2247        break;
2248      }
2249      if (!MI) return false;
2250    }
2251  }
2252
2253  // Get ready to iterate backward from CmpInstr.
2254  MachineBasicBlock::iterator I = CmpInstr, E = MI,
2255                              B = CmpInstr->getParent()->begin();
2256
2257  // Early exit if CmpInstr is at the beginning of the BB.
2258  if (I == B) return false;
2259
2260  // There are two possible candidates which can be changed to set CPSR:
2261  // One is MI, the other is a SUB instruction.
2262  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2263  // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2264  MachineInstr *Sub = NULL;
2265  if (SrcReg2 != 0)
2266    // MI is not a candidate for CMPrr.
2267    MI = NULL;
2268  else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2269    // Conservatively refuse to convert an instruction which isn't in the same
2270    // BB as the comparison.
2271    // For CMPri, we need to check Sub, thus we can't return here.
2272    if (CmpInstr->getOpcode() == ARM::CMPri ||
2273       CmpInstr->getOpcode() == ARM::t2CMPri)
2274      MI = NULL;
2275    else
2276      return false;
2277  }
2278
2279  // Check that CPSR isn't set between the comparison instruction and the one we
2280  // want to change. At the same time, search for Sub.
2281  const TargetRegisterInfo *TRI = &getRegisterInfo();
2282  --I;
2283  for (; I != E; --I) {
2284    const MachineInstr &Instr = *I;
2285
2286    if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2287        Instr.readsRegister(ARM::CPSR, TRI))
2288      // This instruction modifies or uses CPSR after the one we want to
2289      // change. We can't do this transformation.
2290      return false;
2291
2292    // Check whether CmpInstr can be made redundant by the current instruction.
2293    if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2294      Sub = &*I;
2295      break;
2296    }
2297
2298    if (I == B)
2299      // The 'and' is below the comparison instruction.
2300      return false;
2301  }
2302
2303  // Return false if no candidates exist.
2304  if (!MI && !Sub)
2305    return false;
2306
2307  // The single candidate is called MI.
2308  if (!MI) MI = Sub;
2309
2310  // We can't use a predicated instruction - it doesn't always write the flags.
2311  if (isPredicated(MI))
2312    return false;
2313
2314  switch (MI->getOpcode()) {
2315  default: break;
2316  case ARM::RSBrr:
2317  case ARM::RSBri:
2318  case ARM::RSCrr:
2319  case ARM::RSCri:
2320  case ARM::ADDrr:
2321  case ARM::ADDri:
2322  case ARM::ADCrr:
2323  case ARM::ADCri:
2324  case ARM::SUBrr:
2325  case ARM::SUBri:
2326  case ARM::SBCrr:
2327  case ARM::SBCri:
2328  case ARM::t2RSBri:
2329  case ARM::t2ADDrr:
2330  case ARM::t2ADDri:
2331  case ARM::t2ADCrr:
2332  case ARM::t2ADCri:
2333  case ARM::t2SUBrr:
2334  case ARM::t2SUBri:
2335  case ARM::t2SBCrr:
2336  case ARM::t2SBCri:
2337  case ARM::ANDrr:
2338  case ARM::ANDri:
2339  case ARM::t2ANDrr:
2340  case ARM::t2ANDri:
2341  case ARM::ORRrr:
2342  case ARM::ORRri:
2343  case ARM::t2ORRrr:
2344  case ARM::t2ORRri:
2345  case ARM::EORrr:
2346  case ARM::EORri:
2347  case ARM::t2EORrr:
2348  case ARM::t2EORri: {
2349    // Scan forward for the use of CPSR
2350    // When checking against MI: if it's a conditional code requires
2351    // checking of V bit, then this is not safe to do.
2352    // It is safe to remove CmpInstr if CPSR is redefined or killed.
2353    // If we are done with the basic block, we need to check whether CPSR is
2354    // live-out.
2355    SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2356        OperandsToUpdate;
2357    bool isSafe = false;
2358    I = CmpInstr;
2359    E = CmpInstr->getParent()->end();
2360    while (!isSafe && ++I != E) {
2361      const MachineInstr &Instr = *I;
2362      for (unsigned IO = 0, EO = Instr.getNumOperands();
2363           !isSafe && IO != EO; ++IO) {
2364        const MachineOperand &MO = Instr.getOperand(IO);
2365        if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2366          isSafe = true;
2367          break;
2368        }
2369        if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2370          continue;
2371        if (MO.isDef()) {
2372          isSafe = true;
2373          break;
2374        }
2375        // Condition code is after the operand before CPSR except for VSELs.
2376        ARMCC::CondCodes CC;
2377        bool IsInstrVSel = true;
2378        switch (Instr.getOpcode()) {
2379        default:
2380          IsInstrVSel = false;
2381          CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2382          break;
2383        case ARM::VSELEQD:
2384        case ARM::VSELEQS:
2385          CC = ARMCC::EQ;
2386          break;
2387        case ARM::VSELGTD:
2388        case ARM::VSELGTS:
2389          CC = ARMCC::GT;
2390          break;
2391        case ARM::VSELGED:
2392        case ARM::VSELGES:
2393          CC = ARMCC::GE;
2394          break;
2395        case ARM::VSELVSS:
2396        case ARM::VSELVSD:
2397          CC = ARMCC::VS;
2398          break;
2399        }
2400
2401        if (Sub) {
2402          ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2403          if (NewCC == ARMCC::AL)
2404            return false;
2405          // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2406          // on CMP needs to be updated to be based on SUB.
2407          // Push the condition code operands to OperandsToUpdate.
2408          // If it is safe to remove CmpInstr, the condition code of these
2409          // operands will be modified.
2410          if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2411              Sub->getOperand(2).getReg() == SrcReg) {
2412            // VSel doesn't support condition code update.
2413            if (IsInstrVSel)
2414              return false;
2415            OperandsToUpdate.push_back(
2416                std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2417          }
2418        } else
2419          switch (CC) {
2420          default:
2421            // CPSR can be used multiple times, we should continue.
2422            break;
2423          case ARMCC::VS:
2424          case ARMCC::VC:
2425          case ARMCC::GE:
2426          case ARMCC::LT:
2427          case ARMCC::GT:
2428          case ARMCC::LE:
2429            return false;
2430          }
2431      }
2432    }
2433
2434    // If CPSR is not killed nor re-defined, we should check whether it is
2435    // live-out. If it is live-out, do not optimize.
2436    if (!isSafe) {
2437      MachineBasicBlock *MBB = CmpInstr->getParent();
2438      for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2439               SE = MBB->succ_end(); SI != SE; ++SI)
2440        if ((*SI)->isLiveIn(ARM::CPSR))
2441          return false;
2442    }
2443
2444    // Toggle the optional operand to CPSR.
2445    MI->getOperand(5).setReg(ARM::CPSR);
2446    MI->getOperand(5).setIsDef(true);
2447    assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2448    CmpInstr->eraseFromParent();
2449
2450    // Modify the condition code of operands in OperandsToUpdate.
2451    // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2452    // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2453    for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2454      OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2455    return true;
2456  }
2457  }
2458
2459  return false;
2460}
2461
2462bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2463                                     MachineInstr *DefMI, unsigned Reg,
2464                                     MachineRegisterInfo *MRI) const {
2465  // Fold large immediates into add, sub, or, xor.
2466  unsigned DefOpc = DefMI->getOpcode();
2467  if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2468    return false;
2469  if (!DefMI->getOperand(1).isImm())
2470    // Could be t2MOVi32imm <ga:xx>
2471    return false;
2472
2473  if (!MRI->hasOneNonDBGUse(Reg))
2474    return false;
2475
2476  const MCInstrDesc &DefMCID = DefMI->getDesc();
2477  if (DefMCID.hasOptionalDef()) {
2478    unsigned NumOps = DefMCID.getNumOperands();
2479    const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2480    if (MO.getReg() == ARM::CPSR && !MO.isDead())
2481      // If DefMI defines CPSR and it is not dead, it's obviously not safe
2482      // to delete DefMI.
2483      return false;
2484  }
2485
2486  const MCInstrDesc &UseMCID = UseMI->getDesc();
2487  if (UseMCID.hasOptionalDef()) {
2488    unsigned NumOps = UseMCID.getNumOperands();
2489    if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2490      // If the instruction sets the flag, do not attempt this optimization
2491      // since it may change the semantics of the code.
2492      return false;
2493  }
2494
2495  unsigned UseOpc = UseMI->getOpcode();
2496  unsigned NewUseOpc = 0;
2497  uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2498  uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2499  bool Commute = false;
2500  switch (UseOpc) {
2501  default: return false;
2502  case ARM::SUBrr:
2503  case ARM::ADDrr:
2504  case ARM::ORRrr:
2505  case ARM::EORrr:
2506  case ARM::t2SUBrr:
2507  case ARM::t2ADDrr:
2508  case ARM::t2ORRrr:
2509  case ARM::t2EORrr: {
2510    Commute = UseMI->getOperand(2).getReg() != Reg;
2511    switch (UseOpc) {
2512    default: break;
2513    case ARM::SUBrr: {
2514      if (Commute)
2515        return false;
2516      ImmVal = -ImmVal;
2517      NewUseOpc = ARM::SUBri;
2518      // Fallthrough
2519    }
2520    case ARM::ADDrr:
2521    case ARM::ORRrr:
2522    case ARM::EORrr: {
2523      if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2524        return false;
2525      SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2526      SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2527      switch (UseOpc) {
2528      default: break;
2529      case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2530      case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2531      case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2532      }
2533      break;
2534    }
2535    case ARM::t2SUBrr: {
2536      if (Commute)
2537        return false;
2538      ImmVal = -ImmVal;
2539      NewUseOpc = ARM::t2SUBri;
2540      // Fallthrough
2541    }
2542    case ARM::t2ADDrr:
2543    case ARM::t2ORRrr:
2544    case ARM::t2EORrr: {
2545      if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2546        return false;
2547      SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2548      SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2549      switch (UseOpc) {
2550      default: break;
2551      case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2552      case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2553      case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2554      }
2555      break;
2556    }
2557    }
2558  }
2559  }
2560
2561  unsigned OpIdx = Commute ? 2 : 1;
2562  unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2563  bool isKill = UseMI->getOperand(OpIdx).isKill();
2564  unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2565  AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2566                                      UseMI, UseMI->getDebugLoc(),
2567                                      get(NewUseOpc), NewReg)
2568                              .addReg(Reg1, getKillRegState(isKill))
2569                              .addImm(SOImmValV1)));
2570  UseMI->setDesc(get(NewUseOpc));
2571  UseMI->getOperand(1).setReg(NewReg);
2572  UseMI->getOperand(1).setIsKill();
2573  UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2574  DefMI->eraseFromParent();
2575  return true;
2576}
2577
2578static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2579                                        const MachineInstr *MI) {
2580  switch (MI->getOpcode()) {
2581  default: {
2582    const MCInstrDesc &Desc = MI->getDesc();
2583    int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2584    assert(UOps >= 0 && "bad # UOps");
2585    return UOps;
2586  }
2587
2588  case ARM::LDRrs:
2589  case ARM::LDRBrs:
2590  case ARM::STRrs:
2591  case ARM::STRBrs: {
2592    unsigned ShOpVal = MI->getOperand(3).getImm();
2593    bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2594    unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2595    if (!isSub &&
2596        (ShImm == 0 ||
2597         ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2598          ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2599      return 1;
2600    return 2;
2601  }
2602
2603  case ARM::LDRH:
2604  case ARM::STRH: {
2605    if (!MI->getOperand(2).getReg())
2606      return 1;
2607
2608    unsigned ShOpVal = MI->getOperand(3).getImm();
2609    bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2610    unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2611    if (!isSub &&
2612        (ShImm == 0 ||
2613         ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2614          ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2615      return 1;
2616    return 2;
2617  }
2618
2619  case ARM::LDRSB:
2620  case ARM::LDRSH:
2621    return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2622
2623  case ARM::LDRSB_POST:
2624  case ARM::LDRSH_POST: {
2625    unsigned Rt = MI->getOperand(0).getReg();
2626    unsigned Rm = MI->getOperand(3).getReg();
2627    return (Rt == Rm) ? 4 : 3;
2628  }
2629
2630  case ARM::LDR_PRE_REG:
2631  case ARM::LDRB_PRE_REG: {
2632    unsigned Rt = MI->getOperand(0).getReg();
2633    unsigned Rm = MI->getOperand(3).getReg();
2634    if (Rt == Rm)
2635      return 3;
2636    unsigned ShOpVal = MI->getOperand(4).getImm();
2637    bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2638    unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2639    if (!isSub &&
2640        (ShImm == 0 ||
2641         ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2642          ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2643      return 2;
2644    return 3;
2645  }
2646
2647  case ARM::STR_PRE_REG:
2648  case ARM::STRB_PRE_REG: {
2649    unsigned ShOpVal = MI->getOperand(4).getImm();
2650    bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2651    unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2652    if (!isSub &&
2653        (ShImm == 0 ||
2654         ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2655          ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2656      return 2;
2657    return 3;
2658  }
2659
2660  case ARM::LDRH_PRE:
2661  case ARM::STRH_PRE: {
2662    unsigned Rt = MI->getOperand(0).getReg();
2663    unsigned Rm = MI->getOperand(3).getReg();
2664    if (!Rm)
2665      return 2;
2666    if (Rt == Rm)
2667      return 3;
2668    return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2669      ? 3 : 2;
2670  }
2671
2672  case ARM::LDR_POST_REG:
2673  case ARM::LDRB_POST_REG:
2674  case ARM::LDRH_POST: {
2675    unsigned Rt = MI->getOperand(0).getReg();
2676    unsigned Rm = MI->getOperand(3).getReg();
2677    return (Rt == Rm) ? 3 : 2;
2678  }
2679
2680  case ARM::LDR_PRE_IMM:
2681  case ARM::LDRB_PRE_IMM:
2682  case ARM::LDR_POST_IMM:
2683  case ARM::LDRB_POST_IMM:
2684  case ARM::STRB_POST_IMM:
2685  case ARM::STRB_POST_REG:
2686  case ARM::STRB_PRE_IMM:
2687  case ARM::STRH_POST:
2688  case ARM::STR_POST_IMM:
2689  case ARM::STR_POST_REG:
2690  case ARM::STR_PRE_IMM:
2691    return 2;
2692
2693  case ARM::LDRSB_PRE:
2694  case ARM::LDRSH_PRE: {
2695    unsigned Rm = MI->getOperand(3).getReg();
2696    if (Rm == 0)
2697      return 3;
2698    unsigned Rt = MI->getOperand(0).getReg();
2699    if (Rt == Rm)
2700      return 4;
2701    unsigned ShOpVal = MI->getOperand(4).getImm();
2702    bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2703    unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2704    if (!isSub &&
2705        (ShImm == 0 ||
2706         ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2707          ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2708      return 3;
2709    return 4;
2710  }
2711
2712  case ARM::LDRD: {
2713    unsigned Rt = MI->getOperand(0).getReg();
2714    unsigned Rn = MI->getOperand(2).getReg();
2715    unsigned Rm = MI->getOperand(3).getReg();
2716    if (Rm)
2717      return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2718    return (Rt == Rn) ? 3 : 2;
2719  }
2720
2721  case ARM::STRD: {
2722    unsigned Rm = MI->getOperand(3).getReg();
2723    if (Rm)
2724      return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2725    return 2;
2726  }
2727
2728  case ARM::LDRD_POST:
2729  case ARM::t2LDRD_POST:
2730    return 3;
2731
2732  case ARM::STRD_POST:
2733  case ARM::t2STRD_POST:
2734    return 4;
2735
2736  case ARM::LDRD_PRE: {
2737    unsigned Rt = MI->getOperand(0).getReg();
2738    unsigned Rn = MI->getOperand(3).getReg();
2739    unsigned Rm = MI->getOperand(4).getReg();
2740    if (Rm)
2741      return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2742    return (Rt == Rn) ? 4 : 3;
2743  }
2744
2745  case ARM::t2LDRD_PRE: {
2746    unsigned Rt = MI->getOperand(0).getReg();
2747    unsigned Rn = MI->getOperand(3).getReg();
2748    return (Rt == Rn) ? 4 : 3;
2749  }
2750
2751  case ARM::STRD_PRE: {
2752    unsigned Rm = MI->getOperand(4).getReg();
2753    if (Rm)
2754      return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2755    return 3;
2756  }
2757
2758  case ARM::t2STRD_PRE:
2759    return 3;
2760
2761  case ARM::t2LDR_POST:
2762  case ARM::t2LDRB_POST:
2763  case ARM::t2LDRB_PRE:
2764  case ARM::t2LDRSBi12:
2765  case ARM::t2LDRSBi8:
2766  case ARM::t2LDRSBpci:
2767  case ARM::t2LDRSBs:
2768  case ARM::t2LDRH_POST:
2769  case ARM::t2LDRH_PRE:
2770  case ARM::t2LDRSBT:
2771  case ARM::t2LDRSB_POST:
2772  case ARM::t2LDRSB_PRE:
2773  case ARM::t2LDRSH_POST:
2774  case ARM::t2LDRSH_PRE:
2775  case ARM::t2LDRSHi12:
2776  case ARM::t2LDRSHi8:
2777  case ARM::t2LDRSHpci:
2778  case ARM::t2LDRSHs:
2779    return 2;
2780
2781  case ARM::t2LDRDi8: {
2782    unsigned Rt = MI->getOperand(0).getReg();
2783    unsigned Rn = MI->getOperand(2).getReg();
2784    return (Rt == Rn) ? 3 : 2;
2785  }
2786
2787  case ARM::t2STRB_POST:
2788  case ARM::t2STRB_PRE:
2789  case ARM::t2STRBs:
2790  case ARM::t2STRDi8:
2791  case ARM::t2STRH_POST:
2792  case ARM::t2STRH_PRE:
2793  case ARM::t2STRHs:
2794  case ARM::t2STR_POST:
2795  case ARM::t2STR_PRE:
2796  case ARM::t2STRs:
2797    return 2;
2798  }
2799}
2800
2801// Return the number of 32-bit words loaded by LDM or stored by STM. If this
2802// can't be easily determined return 0 (missing MachineMemOperand).
2803//
2804// FIXME: The current MachineInstr design does not support relying on machine
2805// mem operands to determine the width of a memory access. Instead, we expect
2806// the target to provide this information based on the instruction opcode and
2807// operands. However, using MachineMemOperand is a the best solution now for
2808// two reasons:
2809//
2810// 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2811// operands. This is much more dangerous than using the MachineMemOperand
2812// sizes because CodeGen passes can insert/remove optional machine operands. In
2813// fact, it's totally incorrect for preRA passes and appears to be wrong for
2814// postRA passes as well.
2815//
2816// 2) getNumLDMAddresses is only used by the scheduling machine model and any
2817// machine model that calls this should handle the unknown (zero size) case.
2818//
2819// Long term, we should require a target hook that verifies MachineMemOperand
2820// sizes during MC lowering. That target hook should be local to MC lowering
2821// because we can't ensure that it is aware of other MI forms. Doing this will
2822// ensure that MachineMemOperands are correctly propagated through all passes.
2823unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2824  unsigned Size = 0;
2825  for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2826         E = MI->memoperands_end(); I != E; ++I) {
2827    Size += (*I)->getSize();
2828  }
2829  return Size / 4;
2830}
2831
2832unsigned
2833ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2834                                 const MachineInstr *MI) const {
2835  if (!ItinData || ItinData->isEmpty())
2836    return 1;
2837
2838  const MCInstrDesc &Desc = MI->getDesc();
2839  unsigned Class = Desc.getSchedClass();
2840  int ItinUOps = ItinData->getNumMicroOps(Class);
2841  if (ItinUOps >= 0) {
2842    if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2843      return getNumMicroOpsSwiftLdSt(ItinData, MI);
2844
2845    return ItinUOps;
2846  }
2847
2848  unsigned Opc = MI->getOpcode();
2849  switch (Opc) {
2850  default:
2851    llvm_unreachable("Unexpected multi-uops instruction!");
2852  case ARM::VLDMQIA:
2853  case ARM::VSTMQIA:
2854    return 2;
2855
2856  // The number of uOps for load / store multiple are determined by the number
2857  // registers.
2858  //
2859  // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2860  // same cycle. The scheduling for the first load / store must be done
2861  // separately by assuming the address is not 64-bit aligned.
2862  //
2863  // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2864  // is not 64-bit aligned, then AGU would take an extra cycle.  For VFP / NEON
2865  // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2866  case ARM::VLDMDIA:
2867  case ARM::VLDMDIA_UPD:
2868  case ARM::VLDMDDB_UPD:
2869  case ARM::VLDMSIA:
2870  case ARM::VLDMSIA_UPD:
2871  case ARM::VLDMSDB_UPD:
2872  case ARM::VSTMDIA:
2873  case ARM::VSTMDIA_UPD:
2874  case ARM::VSTMDDB_UPD:
2875  case ARM::VSTMSIA:
2876  case ARM::VSTMSIA_UPD:
2877  case ARM::VSTMSDB_UPD: {
2878    unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2879    return (NumRegs / 2) + (NumRegs % 2) + 1;
2880  }
2881
2882  case ARM::LDMIA_RET:
2883  case ARM::LDMIA:
2884  case ARM::LDMDA:
2885  case ARM::LDMDB:
2886  case ARM::LDMIB:
2887  case ARM::LDMIA_UPD:
2888  case ARM::LDMDA_UPD:
2889  case ARM::LDMDB_UPD:
2890  case ARM::LDMIB_UPD:
2891  case ARM::STMIA:
2892  case ARM::STMDA:
2893  case ARM::STMDB:
2894  case ARM::STMIB:
2895  case ARM::STMIA_UPD:
2896  case ARM::STMDA_UPD:
2897  case ARM::STMDB_UPD:
2898  case ARM::STMIB_UPD:
2899  case ARM::tLDMIA:
2900  case ARM::tLDMIA_UPD:
2901  case ARM::tSTMIA_UPD:
2902  case ARM::tPOP_RET:
2903  case ARM::tPOP:
2904  case ARM::tPUSH:
2905  case ARM::t2LDMIA_RET:
2906  case ARM::t2LDMIA:
2907  case ARM::t2LDMDB:
2908  case ARM::t2LDMIA_UPD:
2909  case ARM::t2LDMDB_UPD:
2910  case ARM::t2STMIA:
2911  case ARM::t2STMDB:
2912  case ARM::t2STMIA_UPD:
2913  case ARM::t2STMDB_UPD: {
2914    unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2915    if (Subtarget.isSwift()) {
2916      int UOps = 1 + NumRegs;  // One for address computation, one for each ld / st.
2917      switch (Opc) {
2918      default: break;
2919      case ARM::VLDMDIA_UPD:
2920      case ARM::VLDMDDB_UPD:
2921      case ARM::VLDMSIA_UPD:
2922      case ARM::VLDMSDB_UPD:
2923      case ARM::VSTMDIA_UPD:
2924      case ARM::VSTMDDB_UPD:
2925      case ARM::VSTMSIA_UPD:
2926      case ARM::VSTMSDB_UPD:
2927      case ARM::LDMIA_UPD:
2928      case ARM::LDMDA_UPD:
2929      case ARM::LDMDB_UPD:
2930      case ARM::LDMIB_UPD:
2931      case ARM::STMIA_UPD:
2932      case ARM::STMDA_UPD:
2933      case ARM::STMDB_UPD:
2934      case ARM::STMIB_UPD:
2935      case ARM::tLDMIA_UPD:
2936      case ARM::tSTMIA_UPD:
2937      case ARM::t2LDMIA_UPD:
2938      case ARM::t2LDMDB_UPD:
2939      case ARM::t2STMIA_UPD:
2940      case ARM::t2STMDB_UPD:
2941        ++UOps; // One for base register writeback.
2942        break;
2943      case ARM::LDMIA_RET:
2944      case ARM::tPOP_RET:
2945      case ARM::t2LDMIA_RET:
2946        UOps += 2; // One for base reg wb, one for write to pc.
2947        break;
2948      }
2949      return UOps;
2950    } else if (Subtarget.isCortexA8()) {
2951      if (NumRegs < 4)
2952        return 2;
2953      // 4 registers would be issued: 2, 2.
2954      // 5 registers would be issued: 2, 2, 1.
2955      int A8UOps = (NumRegs / 2);
2956      if (NumRegs % 2)
2957        ++A8UOps;
2958      return A8UOps;
2959    } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2960      int A9UOps = (NumRegs / 2);
2961      // If there are odd number of registers or if it's not 64-bit aligned,
2962      // then it takes an extra AGU (Address Generation Unit) cycle.
2963      if ((NumRegs % 2) ||
2964          !MI->hasOneMemOperand() ||
2965          (*MI->memoperands_begin())->getAlignment() < 8)
2966        ++A9UOps;
2967      return A9UOps;
2968    } else {
2969      // Assume the worst.
2970      return NumRegs;
2971    }
2972  }
2973  }
2974}
2975
2976int
2977ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2978                                  const MCInstrDesc &DefMCID,
2979                                  unsigned DefClass,
2980                                  unsigned DefIdx, unsigned DefAlign) const {
2981  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2982  if (RegNo <= 0)
2983    // Def is the address writeback.
2984    return ItinData->getOperandCycle(DefClass, DefIdx);
2985
2986  int DefCycle;
2987  if (Subtarget.isCortexA8()) {
2988    // (regno / 2) + (regno % 2) + 1
2989    DefCycle = RegNo / 2 + 1;
2990    if (RegNo % 2)
2991      ++DefCycle;
2992  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2993    DefCycle = RegNo;
2994    bool isSLoad = false;
2995
2996    switch (DefMCID.getOpcode()) {
2997    default: break;
2998    case ARM::VLDMSIA:
2999    case ARM::VLDMSIA_UPD:
3000    case ARM::VLDMSDB_UPD:
3001      isSLoad = true;
3002      break;
3003    }
3004
3005    // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3006    // then it takes an extra cycle.
3007    if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3008      ++DefCycle;
3009  } else {
3010    // Assume the worst.
3011    DefCycle = RegNo + 2;
3012  }
3013
3014  return DefCycle;
3015}
3016
3017int
3018ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3019                                 const MCInstrDesc &DefMCID,
3020                                 unsigned DefClass,
3021                                 unsigned DefIdx, unsigned DefAlign) const {
3022  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3023  if (RegNo <= 0)
3024    // Def is the address writeback.
3025    return ItinData->getOperandCycle(DefClass, DefIdx);
3026
3027  int DefCycle;
3028  if (Subtarget.isCortexA8()) {
3029    // 4 registers would be issued: 1, 2, 1.
3030    // 5 registers would be issued: 1, 2, 2.
3031    DefCycle = RegNo / 2;
3032    if (DefCycle < 1)
3033      DefCycle = 1;
3034    // Result latency is issue cycle + 2: E2.
3035    DefCycle += 2;
3036  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3037    DefCycle = (RegNo / 2);
3038    // If there are odd number of registers or if it's not 64-bit aligned,
3039    // then it takes an extra AGU (Address Generation Unit) cycle.
3040    if ((RegNo % 2) || DefAlign < 8)
3041      ++DefCycle;
3042    // Result latency is AGU cycles + 2.
3043    DefCycle += 2;
3044  } else {
3045    // Assume the worst.
3046    DefCycle = RegNo + 2;
3047  }
3048
3049  return DefCycle;
3050}
3051
3052int
3053ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3054                                  const MCInstrDesc &UseMCID,
3055                                  unsigned UseClass,
3056                                  unsigned UseIdx, unsigned UseAlign) const {
3057  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3058  if (RegNo <= 0)
3059    return ItinData->getOperandCycle(UseClass, UseIdx);
3060
3061  int UseCycle;
3062  if (Subtarget.isCortexA8()) {
3063    // (regno / 2) + (regno % 2) + 1
3064    UseCycle = RegNo / 2 + 1;
3065    if (RegNo % 2)
3066      ++UseCycle;
3067  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3068    UseCycle = RegNo;
3069    bool isSStore = false;
3070
3071    switch (UseMCID.getOpcode()) {
3072    default: break;
3073    case ARM::VSTMSIA:
3074    case ARM::VSTMSIA_UPD:
3075    case ARM::VSTMSDB_UPD:
3076      isSStore = true;
3077      break;
3078    }
3079
3080    // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3081    // then it takes an extra cycle.
3082    if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3083      ++UseCycle;
3084  } else {
3085    // Assume the worst.
3086    UseCycle = RegNo + 2;
3087  }
3088
3089  return UseCycle;
3090}
3091
3092int
3093ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3094                                 const MCInstrDesc &UseMCID,
3095                                 unsigned UseClass,
3096                                 unsigned UseIdx, unsigned UseAlign) const {
3097  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3098  if (RegNo <= 0)
3099    return ItinData->getOperandCycle(UseClass, UseIdx);
3100
3101  int UseCycle;
3102  if (Subtarget.isCortexA8()) {
3103    UseCycle = RegNo / 2;
3104    if (UseCycle < 2)
3105      UseCycle = 2;
3106    // Read in E3.
3107    UseCycle += 2;
3108  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3109    UseCycle = (RegNo / 2);
3110    // If there are odd number of registers or if it's not 64-bit aligned,
3111    // then it takes an extra AGU (Address Generation Unit) cycle.
3112    if ((RegNo % 2) || UseAlign < 8)
3113      ++UseCycle;
3114  } else {
3115    // Assume the worst.
3116    UseCycle = 1;
3117  }
3118  return UseCycle;
3119}
3120
3121int
3122ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3123                                    const MCInstrDesc &DefMCID,
3124                                    unsigned DefIdx, unsigned DefAlign,
3125                                    const MCInstrDesc &UseMCID,
3126                                    unsigned UseIdx, unsigned UseAlign) const {
3127  unsigned DefClass = DefMCID.getSchedClass();
3128  unsigned UseClass = UseMCID.getSchedClass();
3129
3130  if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3131    return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3132
3133  // This may be a def / use of a variable_ops instruction, the operand
3134  // latency might be determinable dynamically. Let the target try to
3135  // figure it out.
3136  int DefCycle = -1;
3137  bool LdmBypass = false;
3138  switch (DefMCID.getOpcode()) {
3139  default:
3140    DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3141    break;
3142
3143  case ARM::VLDMDIA:
3144  case ARM::VLDMDIA_UPD:
3145  case ARM::VLDMDDB_UPD:
3146  case ARM::VLDMSIA:
3147  case ARM::VLDMSIA_UPD:
3148  case ARM::VLDMSDB_UPD:
3149    DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3150    break;
3151
3152  case ARM::LDMIA_RET:
3153  case ARM::LDMIA:
3154  case ARM::LDMDA:
3155  case ARM::LDMDB:
3156  case ARM::LDMIB:
3157  case ARM::LDMIA_UPD:
3158  case ARM::LDMDA_UPD:
3159  case ARM::LDMDB_UPD:
3160  case ARM::LDMIB_UPD:
3161  case ARM::tLDMIA:
3162  case ARM::tLDMIA_UPD:
3163  case ARM::tPUSH:
3164  case ARM::t2LDMIA_RET:
3165  case ARM::t2LDMIA:
3166  case ARM::t2LDMDB:
3167  case ARM::t2LDMIA_UPD:
3168  case ARM::t2LDMDB_UPD:
3169    LdmBypass = 1;
3170    DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3171    break;
3172  }
3173
3174  if (DefCycle == -1)
3175    // We can't seem to determine the result latency of the def, assume it's 2.
3176    DefCycle = 2;
3177
3178  int UseCycle = -1;
3179  switch (UseMCID.getOpcode()) {
3180  default:
3181    UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3182    break;
3183
3184  case ARM::VSTMDIA:
3185  case ARM::VSTMDIA_UPD:
3186  case ARM::VSTMDDB_UPD:
3187  case ARM::VSTMSIA:
3188  case ARM::VSTMSIA_UPD:
3189  case ARM::VSTMSDB_UPD:
3190    UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3191    break;
3192
3193  case ARM::STMIA:
3194  case ARM::STMDA:
3195  case ARM::STMDB:
3196  case ARM::STMIB:
3197  case ARM::STMIA_UPD:
3198  case ARM::STMDA_UPD:
3199  case ARM::STMDB_UPD:
3200  case ARM::STMIB_UPD:
3201  case ARM::tSTMIA_UPD:
3202  case ARM::tPOP_RET:
3203  case ARM::tPOP:
3204  case ARM::t2STMIA:
3205  case ARM::t2STMDB:
3206  case ARM::t2STMIA_UPD:
3207  case ARM::t2STMDB_UPD:
3208    UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3209    break;
3210  }
3211
3212  if (UseCycle == -1)
3213    // Assume it's read in the first stage.
3214    UseCycle = 1;
3215
3216  UseCycle = DefCycle - UseCycle + 1;
3217  if (UseCycle > 0) {
3218    if (LdmBypass) {
3219      // It's a variable_ops instruction so we can't use DefIdx here. Just use
3220      // first def operand.
3221      if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3222                                          UseClass, UseIdx))
3223        --UseCycle;
3224    } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3225                                               UseClass, UseIdx)) {
3226      --UseCycle;
3227    }
3228  }
3229
3230  return UseCycle;
3231}
3232
3233static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3234                                           const MachineInstr *MI, unsigned Reg,
3235                                           unsigned &DefIdx, unsigned &Dist) {
3236  Dist = 0;
3237
3238  MachineBasicBlock::const_iterator I = MI; ++I;
3239  MachineBasicBlock::const_instr_iterator II =
3240    llvm::prior(I.getInstrIterator());
3241  assert(II->isInsideBundle() && "Empty bundle?");
3242
3243  int Idx = -1;
3244  while (II->isInsideBundle()) {
3245    Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3246    if (Idx != -1)
3247      break;
3248    --II;
3249    ++Dist;
3250  }
3251
3252  assert(Idx != -1 && "Cannot find bundled definition!");
3253  DefIdx = Idx;
3254  return II;
3255}
3256
3257static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3258                                           const MachineInstr *MI, unsigned Reg,
3259                                           unsigned &UseIdx, unsigned &Dist) {
3260  Dist = 0;
3261
3262  MachineBasicBlock::const_instr_iterator II = MI; ++II;
3263  assert(II->isInsideBundle() && "Empty bundle?");
3264  MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3265
3266  // FIXME: This doesn't properly handle multiple uses.
3267  int Idx = -1;
3268  while (II != E && II->isInsideBundle()) {
3269    Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3270    if (Idx != -1)
3271      break;
3272    if (II->getOpcode() != ARM::t2IT)
3273      ++Dist;
3274    ++II;
3275  }
3276
3277  if (Idx == -1) {
3278    Dist = 0;
3279    return 0;
3280  }
3281
3282  UseIdx = Idx;
3283  return II;
3284}
3285
3286/// Return the number of cycles to add to (or subtract from) the static
3287/// itinerary based on the def opcode and alignment. The caller will ensure that
3288/// adjusted latency is at least one cycle.
3289static int adjustDefLatency(const ARMSubtarget &Subtarget,
3290                            const MachineInstr *DefMI,
3291                            const MCInstrDesc *DefMCID, unsigned DefAlign) {
3292  int Adjust = 0;
3293  if (Subtarget.isCortexA8() || Subtarget.isLikeA9()) {
3294    // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3295    // variants are one cycle cheaper.
3296    switch (DefMCID->getOpcode()) {
3297    default: break;
3298    case ARM::LDRrs:
3299    case ARM::LDRBrs: {
3300      unsigned ShOpVal = DefMI->getOperand(3).getImm();
3301      unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3302      if (ShImm == 0 ||
3303          (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3304        --Adjust;
3305      break;
3306    }
3307    case ARM::t2LDRs:
3308    case ARM::t2LDRBs:
3309    case ARM::t2LDRHs:
3310    case ARM::t2LDRSHs: {
3311      // Thumb2 mode: lsl only.
3312      unsigned ShAmt = DefMI->getOperand(3).getImm();
3313      if (ShAmt == 0 || ShAmt == 2)
3314        --Adjust;
3315      break;
3316    }
3317    }
3318  } else if (Subtarget.isSwift()) {
3319    // FIXME: Properly handle all of the latency adjustments for address
3320    // writeback.
3321    switch (DefMCID->getOpcode()) {
3322    default: break;
3323    case ARM::LDRrs:
3324    case ARM::LDRBrs: {
3325      unsigned ShOpVal = DefMI->getOperand(3).getImm();
3326      bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3327      unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3328      if (!isSub &&
3329          (ShImm == 0 ||
3330           ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3331            ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3332        Adjust -= 2;
3333      else if (!isSub &&
3334               ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3335        --Adjust;
3336      break;
3337    }
3338    case ARM::t2LDRs:
3339    case ARM::t2LDRBs:
3340    case ARM::t2LDRHs:
3341    case ARM::t2LDRSHs: {
3342      // Thumb2 mode: lsl only.
3343      unsigned ShAmt = DefMI->getOperand(3).getImm();
3344      if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3345        Adjust -= 2;
3346      break;
3347    }
3348    }
3349  }
3350
3351  if (DefAlign < 8 && Subtarget.isLikeA9()) {
3352    switch (DefMCID->getOpcode()) {
3353    default: break;
3354    case ARM::VLD1q8:
3355    case ARM::VLD1q16:
3356    case ARM::VLD1q32:
3357    case ARM::VLD1q64:
3358    case ARM::VLD1q8wb_fixed:
3359    case ARM::VLD1q16wb_fixed:
3360    case ARM::VLD1q32wb_fixed:
3361    case ARM::VLD1q64wb_fixed:
3362    case ARM::VLD1q8wb_register:
3363    case ARM::VLD1q16wb_register:
3364    case ARM::VLD1q32wb_register:
3365    case ARM::VLD1q64wb_register:
3366    case ARM::VLD2d8:
3367    case ARM::VLD2d16:
3368    case ARM::VLD2d32:
3369    case ARM::VLD2q8:
3370    case ARM::VLD2q16:
3371    case ARM::VLD2q32:
3372    case ARM::VLD2d8wb_fixed:
3373    case ARM::VLD2d16wb_fixed:
3374    case ARM::VLD2d32wb_fixed:
3375    case ARM::VLD2q8wb_fixed:
3376    case ARM::VLD2q16wb_fixed:
3377    case ARM::VLD2q32wb_fixed:
3378    case ARM::VLD2d8wb_register:
3379    case ARM::VLD2d16wb_register:
3380    case ARM::VLD2d32wb_register:
3381    case ARM::VLD2q8wb_register:
3382    case ARM::VLD2q16wb_register:
3383    case ARM::VLD2q32wb_register:
3384    case ARM::VLD3d8:
3385    case ARM::VLD3d16:
3386    case ARM::VLD3d32:
3387    case ARM::VLD1d64T:
3388    case ARM::VLD3d8_UPD:
3389    case ARM::VLD3d16_UPD:
3390    case ARM::VLD3d32_UPD:
3391    case ARM::VLD1d64Twb_fixed:
3392    case ARM::VLD1d64Twb_register:
3393    case ARM::VLD3q8_UPD:
3394    case ARM::VLD3q16_UPD:
3395    case ARM::VLD3q32_UPD:
3396    case ARM::VLD4d8:
3397    case ARM::VLD4d16:
3398    case ARM::VLD4d32:
3399    case ARM::VLD1d64Q:
3400    case ARM::VLD4d8_UPD:
3401    case ARM::VLD4d16_UPD:
3402    case ARM::VLD4d32_UPD:
3403    case ARM::VLD1d64Qwb_fixed:
3404    case ARM::VLD1d64Qwb_register:
3405    case ARM::VLD4q8_UPD:
3406    case ARM::VLD4q16_UPD:
3407    case ARM::VLD4q32_UPD:
3408    case ARM::VLD1DUPq8:
3409    case ARM::VLD1DUPq16:
3410    case ARM::VLD1DUPq32:
3411    case ARM::VLD1DUPq8wb_fixed:
3412    case ARM::VLD1DUPq16wb_fixed:
3413    case ARM::VLD1DUPq32wb_fixed:
3414    case ARM::VLD1DUPq8wb_register:
3415    case ARM::VLD1DUPq16wb_register:
3416    case ARM::VLD1DUPq32wb_register:
3417    case ARM::VLD2DUPd8:
3418    case ARM::VLD2DUPd16:
3419    case ARM::VLD2DUPd32:
3420    case ARM::VLD2DUPd8wb_fixed:
3421    case ARM::VLD2DUPd16wb_fixed:
3422    case ARM::VLD2DUPd32wb_fixed:
3423    case ARM::VLD2DUPd8wb_register:
3424    case ARM::VLD2DUPd16wb_register:
3425    case ARM::VLD2DUPd32wb_register:
3426    case ARM::VLD4DUPd8:
3427    case ARM::VLD4DUPd16:
3428    case ARM::VLD4DUPd32:
3429    case ARM::VLD4DUPd8_UPD:
3430    case ARM::VLD4DUPd16_UPD:
3431    case ARM::VLD4DUPd32_UPD:
3432    case ARM::VLD1LNd8:
3433    case ARM::VLD1LNd16:
3434    case ARM::VLD1LNd32:
3435    case ARM::VLD1LNd8_UPD:
3436    case ARM::VLD1LNd16_UPD:
3437    case ARM::VLD1LNd32_UPD:
3438    case ARM::VLD2LNd8:
3439    case ARM::VLD2LNd16:
3440    case ARM::VLD2LNd32:
3441    case ARM::VLD2LNq16:
3442    case ARM::VLD2LNq32:
3443    case ARM::VLD2LNd8_UPD:
3444    case ARM::VLD2LNd16_UPD:
3445    case ARM::VLD2LNd32_UPD:
3446    case ARM::VLD2LNq16_UPD:
3447    case ARM::VLD2LNq32_UPD:
3448    case ARM::VLD4LNd8:
3449    case ARM::VLD4LNd16:
3450    case ARM::VLD4LNd32:
3451    case ARM::VLD4LNq16:
3452    case ARM::VLD4LNq32:
3453    case ARM::VLD4LNd8_UPD:
3454    case ARM::VLD4LNd16_UPD:
3455    case ARM::VLD4LNd32_UPD:
3456    case ARM::VLD4LNq16_UPD:
3457    case ARM::VLD4LNq32_UPD:
3458      // If the address is not 64-bit aligned, the latencies of these
3459      // instructions increases by one.
3460      ++Adjust;
3461      break;
3462    }
3463  }
3464  return Adjust;
3465}
3466
3467
3468
3469int
3470ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3471                                    const MachineInstr *DefMI, unsigned DefIdx,
3472                                    const MachineInstr *UseMI,
3473                                    unsigned UseIdx) const {
3474  // No operand latency. The caller may fall back to getInstrLatency.
3475  if (!ItinData || ItinData->isEmpty())
3476    return -1;
3477
3478  const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3479  unsigned Reg = DefMO.getReg();
3480  const MCInstrDesc *DefMCID = &DefMI->getDesc();
3481  const MCInstrDesc *UseMCID = &UseMI->getDesc();
3482
3483  unsigned DefAdj = 0;
3484  if (DefMI->isBundle()) {
3485    DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3486    DefMCID = &DefMI->getDesc();
3487  }
3488  if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3489      DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3490    return 1;
3491  }
3492
3493  unsigned UseAdj = 0;
3494  if (UseMI->isBundle()) {
3495    unsigned NewUseIdx;
3496    const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3497                                                   Reg, NewUseIdx, UseAdj);
3498    if (!NewUseMI)
3499      return -1;
3500
3501    UseMI = NewUseMI;
3502    UseIdx = NewUseIdx;
3503    UseMCID = &UseMI->getDesc();
3504  }
3505
3506  if (Reg == ARM::CPSR) {
3507    if (DefMI->getOpcode() == ARM::FMSTAT) {
3508      // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3509      return Subtarget.isLikeA9() ? 1 : 20;
3510    }
3511
3512    // CPSR set and branch can be paired in the same cycle.
3513    if (UseMI->isBranch())
3514      return 0;
3515
3516    // Otherwise it takes the instruction latency (generally one).
3517    unsigned Latency = getInstrLatency(ItinData, DefMI);
3518
3519    // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3520    // its uses. Instructions which are otherwise scheduled between them may
3521    // incur a code size penalty (not able to use the CPSR setting 16-bit
3522    // instructions).
3523    if (Latency > 0 && Subtarget.isThumb2()) {
3524      const MachineFunction *MF = DefMI->getParent()->getParent();
3525      if (MF->getFunction()->getAttributes().
3526            hasAttribute(AttributeSet::FunctionIndex,
3527                         Attribute::OptimizeForSize))
3528        --Latency;
3529    }
3530    return Latency;
3531  }
3532
3533  if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3534    return -1;
3535
3536  unsigned DefAlign = DefMI->hasOneMemOperand()
3537    ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3538  unsigned UseAlign = UseMI->hasOneMemOperand()
3539    ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3540
3541  // Get the itinerary's latency if possible, and handle variable_ops.
3542  int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3543                                  *UseMCID, UseIdx, UseAlign);
3544  // Unable to find operand latency. The caller may resort to getInstrLatency.
3545  if (Latency < 0)
3546    return Latency;
3547
3548  // Adjust for IT block position.
3549  int Adj = DefAdj + UseAdj;
3550
3551  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3552  Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3553  if (Adj >= 0 || (int)Latency > -Adj) {
3554    return Latency + Adj;
3555  }
3556  // Return the itinerary latency, which may be zero but not less than zero.
3557  return Latency;
3558}
3559
3560int
3561ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3562                                    SDNode *DefNode, unsigned DefIdx,
3563                                    SDNode *UseNode, unsigned UseIdx) const {
3564  if (!DefNode->isMachineOpcode())
3565    return 1;
3566
3567  const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3568
3569  if (isZeroCost(DefMCID.Opcode))
3570    return 0;
3571
3572  if (!ItinData || ItinData->isEmpty())
3573    return DefMCID.mayLoad() ? 3 : 1;
3574
3575  if (!UseNode->isMachineOpcode()) {
3576    int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3577    if (Subtarget.isLikeA9() || Subtarget.isSwift())
3578      return Latency <= 2 ? 1 : Latency - 1;
3579    else
3580      return Latency <= 3 ? 1 : Latency - 2;
3581  }
3582
3583  const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3584  const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3585  unsigned DefAlign = !DefMN->memoperands_empty()
3586    ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3587  const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3588  unsigned UseAlign = !UseMN->memoperands_empty()
3589    ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3590  int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3591                                  UseMCID, UseIdx, UseAlign);
3592
3593  if (Latency > 1 &&
3594      (Subtarget.isCortexA8() || Subtarget.isLikeA9())) {
3595    // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3596    // variants are one cycle cheaper.
3597    switch (DefMCID.getOpcode()) {
3598    default: break;
3599    case ARM::LDRrs:
3600    case ARM::LDRBrs: {
3601      unsigned ShOpVal =
3602        cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3603      unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3604      if (ShImm == 0 ||
3605          (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3606        --Latency;
3607      break;
3608    }
3609    case ARM::t2LDRs:
3610    case ARM::t2LDRBs:
3611    case ARM::t2LDRHs:
3612    case ARM::t2LDRSHs: {
3613      // Thumb2 mode: lsl only.
3614      unsigned ShAmt =
3615        cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3616      if (ShAmt == 0 || ShAmt == 2)
3617        --Latency;
3618      break;
3619    }
3620    }
3621  } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3622    // FIXME: Properly handle all of the latency adjustments for address
3623    // writeback.
3624    switch (DefMCID.getOpcode()) {
3625    default: break;
3626    case ARM::LDRrs:
3627    case ARM::LDRBrs: {
3628      unsigned ShOpVal =
3629        cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3630      unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3631      if (ShImm == 0 ||
3632          ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3633           ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3634        Latency -= 2;
3635      else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3636        --Latency;
3637      break;
3638    }
3639    case ARM::t2LDRs:
3640    case ARM::t2LDRBs:
3641    case ARM::t2LDRHs:
3642    case ARM::t2LDRSHs: {
3643      // Thumb2 mode: lsl 0-3 only.
3644      Latency -= 2;
3645      break;
3646    }
3647    }
3648  }
3649
3650  if (DefAlign < 8 && Subtarget.isLikeA9())
3651    switch (DefMCID.getOpcode()) {
3652    default: break;
3653    case ARM::VLD1q8:
3654    case ARM::VLD1q16:
3655    case ARM::VLD1q32:
3656    case ARM::VLD1q64:
3657    case ARM::VLD1q8wb_register:
3658    case ARM::VLD1q16wb_register:
3659    case ARM::VLD1q32wb_register:
3660    case ARM::VLD1q64wb_register:
3661    case ARM::VLD1q8wb_fixed:
3662    case ARM::VLD1q16wb_fixed:
3663    case ARM::VLD1q32wb_fixed:
3664    case ARM::VLD1q64wb_fixed:
3665    case ARM::VLD2d8:
3666    case ARM::VLD2d16:
3667    case ARM::VLD2d32:
3668    case ARM::VLD2q8Pseudo:
3669    case ARM::VLD2q16Pseudo:
3670    case ARM::VLD2q32Pseudo:
3671    case ARM::VLD2d8wb_fixed:
3672    case ARM::VLD2d16wb_fixed:
3673    case ARM::VLD2d32wb_fixed:
3674    case ARM::VLD2q8PseudoWB_fixed:
3675    case ARM::VLD2q16PseudoWB_fixed:
3676    case ARM::VLD2q32PseudoWB_fixed:
3677    case ARM::VLD2d8wb_register:
3678    case ARM::VLD2d16wb_register:
3679    case ARM::VLD2d32wb_register:
3680    case ARM::VLD2q8PseudoWB_register:
3681    case ARM::VLD2q16PseudoWB_register:
3682    case ARM::VLD2q32PseudoWB_register:
3683    case ARM::VLD3d8Pseudo:
3684    case ARM::VLD3d16Pseudo:
3685    case ARM::VLD3d32Pseudo:
3686    case ARM::VLD1d64TPseudo:
3687    case ARM::VLD3d8Pseudo_UPD:
3688    case ARM::VLD3d16Pseudo_UPD:
3689    case ARM::VLD3d32Pseudo_UPD:
3690    case ARM::VLD3q8Pseudo_UPD:
3691    case ARM::VLD3q16Pseudo_UPD:
3692    case ARM::VLD3q32Pseudo_UPD:
3693    case ARM::VLD3q8oddPseudo:
3694    case ARM::VLD3q16oddPseudo:
3695    case ARM::VLD3q32oddPseudo:
3696    case ARM::VLD3q8oddPseudo_UPD:
3697    case ARM::VLD3q16oddPseudo_UPD:
3698    case ARM::VLD3q32oddPseudo_UPD:
3699    case ARM::VLD4d8Pseudo:
3700    case ARM::VLD4d16Pseudo:
3701    case ARM::VLD4d32Pseudo:
3702    case ARM::VLD1d64QPseudo:
3703    case ARM::VLD4d8Pseudo_UPD:
3704    case ARM::VLD4d16Pseudo_UPD:
3705    case ARM::VLD4d32Pseudo_UPD:
3706    case ARM::VLD4q8Pseudo_UPD:
3707    case ARM::VLD4q16Pseudo_UPD:
3708    case ARM::VLD4q32Pseudo_UPD:
3709    case ARM::VLD4q8oddPseudo:
3710    case ARM::VLD4q16oddPseudo:
3711    case ARM::VLD4q32oddPseudo:
3712    case ARM::VLD4q8oddPseudo_UPD:
3713    case ARM::VLD4q16oddPseudo_UPD:
3714    case ARM::VLD4q32oddPseudo_UPD:
3715    case ARM::VLD1DUPq8:
3716    case ARM::VLD1DUPq16:
3717    case ARM::VLD1DUPq32:
3718    case ARM::VLD1DUPq8wb_fixed:
3719    case ARM::VLD1DUPq16wb_fixed:
3720    case ARM::VLD1DUPq32wb_fixed:
3721    case ARM::VLD1DUPq8wb_register:
3722    case ARM::VLD1DUPq16wb_register:
3723    case ARM::VLD1DUPq32wb_register:
3724    case ARM::VLD2DUPd8:
3725    case ARM::VLD2DUPd16:
3726    case ARM::VLD2DUPd32:
3727    case ARM::VLD2DUPd8wb_fixed:
3728    case ARM::VLD2DUPd16wb_fixed:
3729    case ARM::VLD2DUPd32wb_fixed:
3730    case ARM::VLD2DUPd8wb_register:
3731    case ARM::VLD2DUPd16wb_register:
3732    case ARM::VLD2DUPd32wb_register:
3733    case ARM::VLD4DUPd8Pseudo:
3734    case ARM::VLD4DUPd16Pseudo:
3735    case ARM::VLD4DUPd32Pseudo:
3736    case ARM::VLD4DUPd8Pseudo_UPD:
3737    case ARM::VLD4DUPd16Pseudo_UPD:
3738    case ARM::VLD4DUPd32Pseudo_UPD:
3739    case ARM::VLD1LNq8Pseudo:
3740    case ARM::VLD1LNq16Pseudo:
3741    case ARM::VLD1LNq32Pseudo:
3742    case ARM::VLD1LNq8Pseudo_UPD:
3743    case ARM::VLD1LNq16Pseudo_UPD:
3744    case ARM::VLD1LNq32Pseudo_UPD:
3745    case ARM::VLD2LNd8Pseudo:
3746    case ARM::VLD2LNd16Pseudo:
3747    case ARM::VLD2LNd32Pseudo:
3748    case ARM::VLD2LNq16Pseudo:
3749    case ARM::VLD2LNq32Pseudo:
3750    case ARM::VLD2LNd8Pseudo_UPD:
3751    case ARM::VLD2LNd16Pseudo_UPD:
3752    case ARM::VLD2LNd32Pseudo_UPD:
3753    case ARM::VLD2LNq16Pseudo_UPD:
3754    case ARM::VLD2LNq32Pseudo_UPD:
3755    case ARM::VLD4LNd8Pseudo:
3756    case ARM::VLD4LNd16Pseudo:
3757    case ARM::VLD4LNd32Pseudo:
3758    case ARM::VLD4LNq16Pseudo:
3759    case ARM::VLD4LNq32Pseudo:
3760    case ARM::VLD4LNd8Pseudo_UPD:
3761    case ARM::VLD4LNd16Pseudo_UPD:
3762    case ARM::VLD4LNd32Pseudo_UPD:
3763    case ARM::VLD4LNq16Pseudo_UPD:
3764    case ARM::VLD4LNq32Pseudo_UPD:
3765      // If the address is not 64-bit aligned, the latencies of these
3766      // instructions increases by one.
3767      ++Latency;
3768      break;
3769    }
3770
3771  return Latency;
3772}
3773
3774unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3775   if (MI->isCopyLike() || MI->isInsertSubreg() ||
3776      MI->isRegSequence() || MI->isImplicitDef())
3777    return 0;
3778
3779  if (MI->isBundle())
3780    return 0;
3781
3782  const MCInstrDesc &MCID = MI->getDesc();
3783
3784  if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3785    // When predicated, CPSR is an additional source operand for CPSR updating
3786    // instructions, this apparently increases their latencies.
3787    return 1;
3788  }
3789  return 0;
3790}
3791
3792unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3793                                           const MachineInstr *MI,
3794                                           unsigned *PredCost) const {
3795  if (MI->isCopyLike() || MI->isInsertSubreg() ||
3796      MI->isRegSequence() || MI->isImplicitDef())
3797    return 1;
3798
3799  // An instruction scheduler typically runs on unbundled instructions, however
3800  // other passes may query the latency of a bundled instruction.
3801  if (MI->isBundle()) {
3802    unsigned Latency = 0;
3803    MachineBasicBlock::const_instr_iterator I = MI;
3804    MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3805    while (++I != E && I->isInsideBundle()) {
3806      if (I->getOpcode() != ARM::t2IT)
3807        Latency += getInstrLatency(ItinData, I, PredCost);
3808    }
3809    return Latency;
3810  }
3811
3812  const MCInstrDesc &MCID = MI->getDesc();
3813  if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3814    // When predicated, CPSR is an additional source operand for CPSR updating
3815    // instructions, this apparently increases their latencies.
3816    *PredCost = 1;
3817  }
3818  // Be sure to call getStageLatency for an empty itinerary in case it has a
3819  // valid MinLatency property.
3820  if (!ItinData)
3821    return MI->mayLoad() ? 3 : 1;
3822
3823  unsigned Class = MCID.getSchedClass();
3824
3825  // For instructions with variable uops, use uops as latency.
3826  if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3827    return getNumMicroOps(ItinData, MI);
3828
3829  // For the common case, fall back on the itinerary's latency.
3830  unsigned Latency = ItinData->getStageLatency(Class);
3831
3832  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3833  unsigned DefAlign = MI->hasOneMemOperand()
3834    ? (*MI->memoperands_begin())->getAlignment() : 0;
3835  int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3836  if (Adj >= 0 || (int)Latency > -Adj) {
3837    return Latency + Adj;
3838  }
3839  return Latency;
3840}
3841
3842int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3843                                      SDNode *Node) const {
3844  if (!Node->isMachineOpcode())
3845    return 1;
3846
3847  if (!ItinData || ItinData->isEmpty())
3848    return 1;
3849
3850  unsigned Opcode = Node->getMachineOpcode();
3851  switch (Opcode) {
3852  default:
3853    return ItinData->getStageLatency(get(Opcode).getSchedClass());
3854  case ARM::VLDMQIA:
3855  case ARM::VSTMQIA:
3856    return 2;
3857  }
3858}
3859
3860bool ARMBaseInstrInfo::
3861hasHighOperandLatency(const InstrItineraryData *ItinData,
3862                      const MachineRegisterInfo *MRI,
3863                      const MachineInstr *DefMI, unsigned DefIdx,
3864                      const MachineInstr *UseMI, unsigned UseIdx) const {
3865  unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3866  unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3867  if (Subtarget.isCortexA8() &&
3868      (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3869    // CortexA8 VFP instructions are not pipelined.
3870    return true;
3871
3872  // Hoist VFP / NEON instructions with 4 or higher latency.
3873  int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
3874  if (Latency < 0)
3875    Latency = getInstrLatency(ItinData, DefMI);
3876  if (Latency <= 3)
3877    return false;
3878  return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
3879         UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
3880}
3881
3882bool ARMBaseInstrInfo::
3883hasLowDefLatency(const InstrItineraryData *ItinData,
3884                 const MachineInstr *DefMI, unsigned DefIdx) const {
3885  if (!ItinData || ItinData->isEmpty())
3886    return false;
3887
3888  unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3889  if (DDomain == ARMII::DomainGeneral) {
3890    unsigned DefClass = DefMI->getDesc().getSchedClass();
3891    int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3892    return (DefCycle != -1 && DefCycle <= 2);
3893  }
3894  return false;
3895}
3896
3897bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3898                                         StringRef &ErrInfo) const {
3899  if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3900    ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
3901    return false;
3902  }
3903  return true;
3904}
3905
3906bool
3907ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3908                                     unsigned &AddSubOpc,
3909                                     bool &NegAcc, bool &HasLane) const {
3910  DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3911  if (I == MLxEntryMap.end())
3912    return false;
3913
3914  const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
3915  MulOpc = Entry.MulOpc;
3916  AddSubOpc = Entry.AddSubOpc;
3917  NegAcc = Entry.NegAcc;
3918  HasLane = Entry.HasLane;
3919  return true;
3920}
3921
3922//===----------------------------------------------------------------------===//
3923// Execution domains.
3924//===----------------------------------------------------------------------===//
3925//
3926// Some instructions go down the NEON pipeline, some go down the VFP pipeline,
3927// and some can go down both.  The vmov instructions go down the VFP pipeline,
3928// but they can be changed to vorr equivalents that are executed by the NEON
3929// pipeline.
3930//
3931// We use the following execution domain numbering:
3932//
3933enum ARMExeDomain {
3934  ExeGeneric = 0,
3935  ExeVFP = 1,
3936  ExeNEON = 2
3937};
3938//
3939// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
3940//
3941std::pair<uint16_t, uint16_t>
3942ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3943  // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
3944  // if they are not predicated.
3945  if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3946    return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3947
3948  // CortexA9 is particularly picky about mixing the two and wants these
3949  // converted.
3950  if (Subtarget.isCortexA9() && !isPredicated(MI) &&
3951      (MI->getOpcode() == ARM::VMOVRS ||
3952       MI->getOpcode() == ARM::VMOVSR ||
3953       MI->getOpcode() == ARM::VMOVS))
3954    return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3955
3956  // No other instructions can be swizzled, so just determine their domain.
3957  unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
3958
3959  if (Domain & ARMII::DomainNEON)
3960    return std::make_pair(ExeNEON, 0);
3961
3962  // Certain instructions can go either way on Cortex-A8.
3963  // Treat them as NEON instructions.
3964  if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
3965    return std::make_pair(ExeNEON, 0);
3966
3967  if (Domain & ARMII::DomainVFP)
3968    return std::make_pair(ExeVFP, 0);
3969
3970  return std::make_pair(ExeGeneric, 0);
3971}
3972
3973static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
3974                                            unsigned SReg, unsigned &Lane) {
3975  unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
3976  Lane = 0;
3977
3978  if (DReg != ARM::NoRegister)
3979   return DReg;
3980
3981  Lane = 1;
3982  DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
3983
3984  assert(DReg && "S-register with no D super-register?");
3985  return DReg;
3986}
3987
3988/// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
3989/// set ImplicitSReg to a register number that must be marked as implicit-use or
3990/// zero if no register needs to be defined as implicit-use.
3991///
3992/// If the function cannot determine if an SPR should be marked implicit use or
3993/// not, it returns false.
3994///
3995/// This function handles cases where an instruction is being modified from taking
3996/// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
3997/// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
3998/// lane of the DPR).
3999///
4000/// If the other SPR is defined, an implicit-use of it should be added. Else,
4001/// (including the case where the DPR itself is defined), it should not.
4002///
4003static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4004                                       MachineInstr *MI,
4005                                       unsigned DReg, unsigned Lane,
4006                                       unsigned &ImplicitSReg) {
4007  // If the DPR is defined or used already, the other SPR lane will be chained
4008  // correctly, so there is nothing to be done.
4009  if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4010    ImplicitSReg = 0;
4011    return true;
4012  }
4013
4014  // Otherwise we need to go searching to see if the SPR is set explicitly.
4015  ImplicitSReg = TRI->getSubReg(DReg,
4016                                (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4017  MachineBasicBlock::LivenessQueryResult LQR =
4018    MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4019
4020  if (LQR == MachineBasicBlock::LQR_Live)
4021    return true;
4022  else if (LQR == MachineBasicBlock::LQR_Unknown)
4023    return false;
4024
4025  // If the register is known not to be live, there is no need to add an
4026  // implicit-use.
4027  ImplicitSReg = 0;
4028  return true;
4029}
4030
4031void
4032ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4033  unsigned DstReg, SrcReg, DReg;
4034  unsigned Lane;
4035  MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4036  const TargetRegisterInfo *TRI = &getRegisterInfo();
4037  switch (MI->getOpcode()) {
4038    default:
4039      llvm_unreachable("cannot handle opcode!");
4040      break;
4041    case ARM::VMOVD:
4042      if (Domain != ExeNEON)
4043        break;
4044
4045      // Zap the predicate operands.
4046      assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4047
4048      // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4049      DstReg = MI->getOperand(0).getReg();
4050      SrcReg = MI->getOperand(1).getReg();
4051
4052      for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4053        MI->RemoveOperand(i-1);
4054
4055      // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4056      MI->setDesc(get(ARM::VORRd));
4057      AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4058                        .addReg(SrcReg)
4059                        .addReg(SrcReg));
4060      break;
4061    case ARM::VMOVRS:
4062      if (Domain != ExeNEON)
4063        break;
4064      assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4065
4066      // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4067      DstReg = MI->getOperand(0).getReg();
4068      SrcReg = MI->getOperand(1).getReg();
4069
4070      for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4071        MI->RemoveOperand(i-1);
4072
4073      DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4074
4075      // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4076      // Note that DSrc has been widened and the other lane may be undef, which
4077      // contaminates the entire register.
4078      MI->setDesc(get(ARM::VGETLNi32));
4079      AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4080                        .addReg(DReg, RegState::Undef)
4081                        .addImm(Lane));
4082
4083      // The old source should be an implicit use, otherwise we might think it
4084      // was dead before here.
4085      MIB.addReg(SrcReg, RegState::Implicit);
4086      break;
4087    case ARM::VMOVSR: {
4088      if (Domain != ExeNEON)
4089        break;
4090      assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4091
4092      // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4093      DstReg = MI->getOperand(0).getReg();
4094      SrcReg = MI->getOperand(1).getReg();
4095
4096      DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4097
4098      unsigned ImplicitSReg;
4099      if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4100        break;
4101
4102      for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4103        MI->RemoveOperand(i-1);
4104
4105      // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4106      // Again DDst may be undefined at the beginning of this instruction.
4107      MI->setDesc(get(ARM::VSETLNi32));
4108      MIB.addReg(DReg, RegState::Define)
4109         .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4110         .addReg(SrcReg)
4111         .addImm(Lane);
4112      AddDefaultPred(MIB);
4113
4114      // The narrower destination must be marked as set to keep previous chains
4115      // in place.
4116      MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4117      if (ImplicitSReg != 0)
4118        MIB.addReg(ImplicitSReg, RegState::Implicit);
4119      break;
4120    }
4121    case ARM::VMOVS: {
4122      if (Domain != ExeNEON)
4123        break;
4124
4125      // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4126      DstReg = MI->getOperand(0).getReg();
4127      SrcReg = MI->getOperand(1).getReg();
4128
4129      unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4130      DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4131      DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4132
4133      unsigned ImplicitSReg;
4134      if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4135        break;
4136
4137      for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4138        MI->RemoveOperand(i-1);
4139
4140      if (DSrc == DDst) {
4141        // Destination can be:
4142        //     %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4143        MI->setDesc(get(ARM::VDUPLN32d));
4144        MIB.addReg(DDst, RegState::Define)
4145           .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4146           .addImm(SrcLane);
4147        AddDefaultPred(MIB);
4148
4149        // Neither the source or the destination are naturally represented any
4150        // more, so add them in manually.
4151        MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4152        MIB.addReg(SrcReg, RegState::Implicit);
4153        if (ImplicitSReg != 0)
4154          MIB.addReg(ImplicitSReg, RegState::Implicit);
4155        break;
4156      }
4157
4158      // In general there's no single instruction that can perform an S <-> S
4159      // move in NEON space, but a pair of VEXT instructions *can* do the
4160      // job. It turns out that the VEXTs needed will only use DSrc once, with
4161      // the position based purely on the combination of lane-0 and lane-1
4162      // involved. For example
4163      //     vmov s0, s2 -> vext.32 d0, d0, d1, #1  vext.32 d0, d0, d0, #1
4164      //     vmov s1, s3 -> vext.32 d0, d1, d0, #1  vext.32 d0, d0, d0, #1
4165      //     vmov s0, s3 -> vext.32 d0, d0, d0, #1  vext.32 d0, d1, d0, #1
4166      //     vmov s1, s2 -> vext.32 d0, d0, d0, #1  vext.32 d0, d0, d1, #1
4167      //
4168      // Pattern of the MachineInstrs is:
4169      //     %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4170      MachineInstrBuilder NewMIB;
4171      NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4172                       get(ARM::VEXTd32), DDst);
4173
4174      // On the first instruction, both DSrc and DDst may be <undef> if present.
4175      // Specifically when the original instruction didn't have them as an
4176      // <imp-use>.
4177      unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4178      bool CurUndef = !MI->readsRegister(CurReg, TRI);
4179      NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4180
4181      CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4182      CurUndef = !MI->readsRegister(CurReg, TRI);
4183      NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4184
4185      NewMIB.addImm(1);
4186      AddDefaultPred(NewMIB);
4187
4188      if (SrcLane == DstLane)
4189        NewMIB.addReg(SrcReg, RegState::Implicit);
4190
4191      MI->setDesc(get(ARM::VEXTd32));
4192      MIB.addReg(DDst, RegState::Define);
4193
4194      // On the second instruction, DDst has definitely been defined above, so
4195      // it is not <undef>. DSrc, if present, can be <undef> as above.
4196      CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4197      CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4198      MIB.addReg(CurReg, getUndefRegState(CurUndef));
4199
4200      CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4201      CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4202      MIB.addReg(CurReg, getUndefRegState(CurUndef));
4203
4204      MIB.addImm(1);
4205      AddDefaultPred(MIB);
4206
4207      if (SrcLane != DstLane)
4208        MIB.addReg(SrcReg, RegState::Implicit);
4209
4210      // As before, the original destination is no longer represented, add it
4211      // implicitly.
4212      MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4213      if (ImplicitSReg != 0)
4214        MIB.addReg(ImplicitSReg, RegState::Implicit);
4215      break;
4216    }
4217  }
4218
4219}
4220
4221//===----------------------------------------------------------------------===//
4222// Partial register updates
4223//===----------------------------------------------------------------------===//
4224//
4225// Swift renames NEON registers with 64-bit granularity.  That means any
4226// instruction writing an S-reg implicitly reads the containing D-reg.  The
4227// problem is mostly avoided by translating f32 operations to v2f32 operations
4228// on D-registers, but f32 loads are still a problem.
4229//
4230// These instructions can load an f32 into a NEON register:
4231//
4232// VLDRS - Only writes S, partial D update.
4233// VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4234// VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4235//
4236// FCONSTD can be used as a dependency-breaking instruction.
4237unsigned ARMBaseInstrInfo::
4238getPartialRegUpdateClearance(const MachineInstr *MI,
4239                             unsigned OpNum,
4240                             const TargetRegisterInfo *TRI) const {
4241  if (!SwiftPartialUpdateClearance ||
4242      !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4243    return 0;
4244
4245  assert(TRI && "Need TRI instance");
4246
4247  const MachineOperand &MO = MI->getOperand(OpNum);
4248  if (MO.readsReg())
4249    return 0;
4250  unsigned Reg = MO.getReg();
4251  int UseOp = -1;
4252
4253  switch(MI->getOpcode()) {
4254    // Normal instructions writing only an S-register.
4255  case ARM::VLDRS:
4256  case ARM::FCONSTS:
4257  case ARM::VMOVSR:
4258  case ARM::VMOVv8i8:
4259  case ARM::VMOVv4i16:
4260  case ARM::VMOVv2i32:
4261  case ARM::VMOVv2f32:
4262  case ARM::VMOVv1i64:
4263    UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4264    break;
4265
4266    // Explicitly reads the dependency.
4267  case ARM::VLD1LNd32:
4268    UseOp = 3;
4269    break;
4270  default:
4271    return 0;
4272  }
4273
4274  // If this instruction actually reads a value from Reg, there is no unwanted
4275  // dependency.
4276  if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4277    return 0;
4278
4279  // We must be able to clobber the whole D-reg.
4280  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4281    // Virtual register must be a foo:ssub_0<def,undef> operand.
4282    if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4283      return 0;
4284  } else if (ARM::SPRRegClass.contains(Reg)) {
4285    // Physical register: MI must define the full D-reg.
4286    unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4287                                             &ARM::DPRRegClass);
4288    if (!DReg || !MI->definesRegister(DReg, TRI))
4289      return 0;
4290  }
4291
4292  // MI has an unwanted D-register dependency.
4293  // Avoid defs in the previous N instructrions.
4294  return SwiftPartialUpdateClearance;
4295}
4296
4297// Break a partial register dependency after getPartialRegUpdateClearance
4298// returned non-zero.
4299void ARMBaseInstrInfo::
4300breakPartialRegDependency(MachineBasicBlock::iterator MI,
4301                          unsigned OpNum,
4302                          const TargetRegisterInfo *TRI) const {
4303  assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4304  assert(TRI && "Need TRI instance");
4305
4306  const MachineOperand &MO = MI->getOperand(OpNum);
4307  unsigned Reg = MO.getReg();
4308  assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4309         "Can't break virtual register dependencies.");
4310  unsigned DReg = Reg;
4311
4312  // If MI defines an S-reg, find the corresponding D super-register.
4313  if (ARM::SPRRegClass.contains(Reg)) {
4314    DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4315    assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4316  }
4317
4318  assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4319  assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4320
4321  // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4322  // the full D-register by loading the same value to both lanes.  The
4323  // instruction is micro-coded with 2 uops, so don't do this until we can
4324  // properly schedule micro-coded instructions.  The dispatcher stalls cause
4325  // too big regressions.
4326
4327  // Insert the dependency-breaking FCONSTD before MI.
4328  // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4329  AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4330                         get(ARM::FCONSTD), DReg).addImm(96));
4331  MI->addRegisterKilled(DReg, TRI, true);
4332}
4333
4334bool ARMBaseInstrInfo::hasNOP() const {
4335  return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
4336}
4337
4338bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4339  if (MI->getNumOperands() < 4)
4340    return true;
4341  unsigned ShOpVal = MI->getOperand(3).getImm();
4342  unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4343  // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4344  if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4345      ((ShImm == 1 || ShImm == 2) &&
4346       ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4347    return true;
4348
4349  return false;
4350}
4351