ARM.td revision 263508 
1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// ARM Subtarget state.
21//
22
23def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
24                                  "Thumb mode">;
25
26//===----------------------------------------------------------------------===//
27// ARM Subtarget features.
28//
29
30def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31                                   "Enable VFP2 instructions">;
32def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33                                   "Enable VFP3 instructions",
34                                   [FeatureVFP2]>;
35def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36                                   "Enable NEON instructions",
37                                   [FeatureVFP3]>;
38def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39                                     "Enable Thumb2 instructions">;
40def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
41                                     "Does not support ARM mode execution",
42                                     [ModeThumb]>;
43def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
44                                     "Enable half-precision floating point">;
45def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
46                                     "Enable VFP4 instructions",
47                                     [FeatureVFP3, FeatureFP16]>;
48def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
49                                   "true", "Enable ARMv8 FP",
50                                   [FeatureVFP4]>;
51def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
52                                     "Restrict VFP3 to 16 double registers">;
53def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
54                                     "Enable divide instructions">;
55def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
56                                        "HasHardwareDivideInARM", "true",
57                                      "Enable divide instructions in ARM mode">;
58def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
59                                 "Enable Thumb2 extract and pack instructions">;
60def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
61                                   "Has data barrier (dmb / dsb) instructions">;
62def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
63                                         "FP compare + branch is slow">;
64def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
65                          "Floating point unit supports single precision only">;
66def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
67                           "Enable support for Performance Monitor extensions">;
68def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
69                          "Enable support for TrustZone security extensions">;
70def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
71                          "Enable support for Cryptography extensions",
72                          [FeatureNEON]>;
73def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
74                          "Enable support for CRC instructions">;
75
76// Some processors have FP multiply-accumulate instructions that don't
77// play nicely with other VFP / NEON instructions, and it's generally better
78// to just not use them.
79def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
80                                         "Disable VFP / NEON MAC instructions">;
81
82// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
83def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
84                                       "HasVMLxForwarding", "true",
85                                       "Has multiplier accumulator forwarding">;
86
87// Some processors benefit from using NEON instructions for scalar
88// single-precision FP operations.
89def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
90                                        "true",
91                                        "Use NEON for single precision FP">;
92
93// Disable 32-bit to 16-bit narrowing for experimentation.
94def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
95                                             "Prefer 32-bit Thumb instrs">;
96
97/// Some instructions update CPSR partially, which can add false dependency for
98/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
99/// mapped to a separate physical register. Avoid partial CPSR update for these
100/// processors.
101def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
102                                               "AvoidCPSRPartialUpdate", "true",
103                                 "Avoid CPSR partial update for OOO execution">;
104
105def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
106                                            "AvoidMOVsShifterOperand", "true",
107                                "Avoid movs instructions with shifter operand">;
108
109// Some processors perform return stack prediction. CodeGen should avoid issue
110// "normal" call instructions to callees which do not return.
111def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
112                                     "Has return address stack">;
113
114/// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
115def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
116                                 "Supports v7 DSP instructions in Thumb2">;
117
118// Multiprocessing extension.
119def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
120                                 "Supports Multiprocessing extension">;
121
122// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
123def FeatureVirtualization : SubtargetFeature<"virtualization",
124                                 "HasVirtualization", "true",
125                                 "Supports Virtualization extension",
126                                 [FeatureHWDiv, FeatureHWDivARM]>;
127
128// M-series ISA
129def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
130                                     "Is microcontroller profile ('M' series)">;
131
132// R-series ISA
133def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
134                                     "Is realtime profile ('R' series)">;
135
136// A-series ISA
137def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
138                                     "Is application profile ('A' series)">;
139
140// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
141// See ARMInstrInfo.td for details.
142def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
143                                       "NaCl trap">;
144
145// ARM ISAs.
146def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
147                                   "Support ARM v4T instructions">;
148def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
149                                   "Support ARM v5T instructions",
150                                   [HasV4TOps]>;
151def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
152                             "Support ARM v5TE, v5TEj, and v5TExp instructions",
153                                   [HasV5TOps]>;
154def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
155                                   "Support ARM v6 instructions",
156                                   [HasV5TEOps]>;
157def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
158                                   "Support ARM v6M instructions",
159                                   [HasV6Ops]>;
160def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
161                                   "Support ARM v6t2 instructions",
162                                   [HasV6MOps, FeatureThumb2]>;
163def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
164                                   "Support ARM v7 instructions",
165                                   [HasV6T2Ops, FeaturePerfMon]>;
166def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
167                                   "Support ARM v8 instructions",
168                                   [HasV7Ops, FeatureVirtualization,
169                                    FeatureMP]>;
170
171//===----------------------------------------------------------------------===//
172// ARM Processors supported.
173//
174
175include "ARMSchedule.td"
176
177// ARM processor families.
178def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
179                                   "Cortex-A5 ARM processors",
180                                   [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
181                                    FeatureVMLxForwarding, FeatureT2XtPk,
182                                    FeatureTrustZone]>;
183def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
184                                   "Cortex-A8 ARM processors",
185                                   [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
186                                    FeatureVMLxForwarding, FeatureT2XtPk,
187                                    FeatureTrustZone]>;
188def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
189                                   "Cortex-A9 ARM processors",
190                                   [FeatureVMLxForwarding,
191                                    FeatureT2XtPk, FeatureFP16,
192                                    FeatureAvoidPartialCPSR,
193                                    FeatureTrustZone]>;
194def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
195                                   "Swift ARM processors",
196                                   [FeatureNEONForFP, FeatureT2XtPk,
197                                    FeatureVFP4, FeatureMP, FeatureHWDiv,
198                                    FeatureHWDivARM, FeatureAvoidPartialCPSR,
199                                    FeatureAvoidMOVsShOp,
200                                    FeatureHasSlowFPVMLx, FeatureTrustZone]>;
201
202// FIXME: It has not been determined if A15 has these features.
203def ProcA15      : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
204                                   "Cortex-A15 ARM processors",
205                                   [FeatureT2XtPk, FeatureVFP4,
206                                    FeatureMP, FeatureHWDiv, FeatureHWDivARM,
207                                    FeatureAvoidPartialCPSR,
208                                    FeatureTrustZone, FeatureVirtualization]>;
209
210def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
211                                   "Cortex-A53 ARM processors",
212                                   [FeatureHWDiv, FeatureHWDivARM,
213                                    FeatureTrustZone, FeatureT2XtPk,
214                                    FeatureCrypto, FeatureCRC]>;
215
216def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
217                                   "Cortex-A57 ARM processors",
218                                   [FeatureHWDiv, FeatureHWDivARM,
219                                    FeatureTrustZone, FeatureT2XtPk,
220                                    FeatureCrypto, FeatureCRC]>;
221
222def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
223                                   "Cortex-R5 ARM processors",
224                                   [FeatureSlowFPBrcc,
225                                    FeatureHWDiv, FeatureHWDivARM,
226                                    FeatureHasSlowFPVMLx,
227                                    FeatureAvoidPartialCPSR,
228                                    FeatureT2XtPk]>;
229
230class ProcNoItin<string Name, list<SubtargetFeature> Features>
231 : Processor<Name, NoItineraries, Features>;
232
233// V4 Processors.
234def : ProcNoItin<"generic",         []>;
235def : ProcNoItin<"arm8",            []>;
236def : ProcNoItin<"arm810",          []>;
237def : ProcNoItin<"strongarm",       []>;
238def : ProcNoItin<"strongarm110",    []>;
239def : ProcNoItin<"strongarm1100",   []>;
240def : ProcNoItin<"strongarm1110",   []>;
241
242// V4T Processors.
243def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
244def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
245def : ProcNoItin<"arm710t",         [HasV4TOps]>;
246def : ProcNoItin<"arm720t",         [HasV4TOps]>;
247def : ProcNoItin<"arm9",            [HasV4TOps]>;
248def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
249def : ProcNoItin<"arm920",          [HasV4TOps]>;
250def : ProcNoItin<"arm920t",         [HasV4TOps]>;
251def : ProcNoItin<"arm922t",         [HasV4TOps]>;
252def : ProcNoItin<"arm940t",         [HasV4TOps]>;
253def : ProcNoItin<"ep9312",          [HasV4TOps]>;
254
255// V5T Processors.
256def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
257def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
258
259// V5TE Processors.
260def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
261def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
262def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
263def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
264def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
265def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
266def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
267def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
268def : ProcNoItin<"xscale",          [HasV5TEOps]>;
269def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
270
271// V6 Processors.
272def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
273def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
274                                                       FeatureHasSlowFPVMLx]>;
275def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
276def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
277                                                       FeatureHasSlowFPVMLx]>;
278def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
279def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
280                                                       FeatureHasSlowFPVMLx]>;
281
282// V6M Processors.
283def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
284                                                       FeatureDB, FeatureMClass]>;
285
286// V6T2 Processors.
287def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
288                                                       FeatureDSPThumb2]>;
289def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
290                                                       FeatureHasSlowFPVMLx,
291                                                       FeatureDSPThumb2]>;
292
293// V7a Processors.
294// FIXME: A5 has currently the same Schedule model as A8
295def : ProcessorModel<"cortex-a5",   CortexA8Model,
296                                    [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
297                                     FeatureVFP4, FeatureDSPThumb2,
298                                     FeatureHasRAS, FeatureAClass]>;
299def : ProcessorModel<"cortex-a8",   CortexA8Model,
300                                    [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
301                                     FeatureDSPThumb2, FeatureHasRAS,
302                                     FeatureAClass]>;
303def : ProcessorModel<"cortex-a9",   CortexA9Model,
304                                    [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
305                                     FeatureDSPThumb2, FeatureHasRAS,
306                                     FeatureAClass]>;
307def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
308                                    [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
309                                     FeatureDSPThumb2, FeatureMP,
310                                     FeatureHasRAS, FeatureAClass]>;
311// FIXME: A15 has currently the same ProcessorModel as A9.
312def : ProcessorModel<"cortex-a15",   CortexA9Model,
313                                    [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
314                                     FeatureDSPThumb2, FeatureHasRAS,
315                                     FeatureAClass]>;
316// FIXME: R5 has currently the same ProcessorModel as A8.
317def : ProcessorModel<"cortex-r5",   CortexA8Model,
318                                    [ProcR5, HasV7Ops, FeatureDB,
319                                     FeatureVFP3, FeatureDSPThumb2,
320                                     FeatureHasRAS, FeatureVFPOnlySP,
321                                     FeatureD16, FeatureRClass]>;
322
323// V7M Processors.
324def : ProcNoItin<"cortex-m3",       [HasV7Ops,
325                                     FeatureThumb2, FeatureNoARM, FeatureDB,
326                                     FeatureHWDiv, FeatureMClass]>;
327
328// V7EM Processors.
329def : ProcNoItin<"cortex-m4",       [HasV7Ops,
330                                     FeatureThumb2, FeatureNoARM, FeatureDB,
331                                     FeatureHWDiv, FeatureDSPThumb2,
332                                     FeatureT2XtPk, FeatureVFP4,
333                                     FeatureVFPOnlySP, FeatureD16,
334                                     FeatureMClass]>;
335
336// Swift uArch Processors.
337def : ProcessorModel<"swift",       SwiftModel,
338                                    [ProcSwift, HasV7Ops, FeatureNEON,
339                                     FeatureDB, FeatureDSPThumb2,
340                                     FeatureHasRAS, FeatureAClass]>;
341
342// V8 Processors
343def : ProcNoItin<"cortex-a53",      [ProcA53, HasV8Ops, FeatureAClass,
344                                    FeatureDB, FeatureFPARMv8,
345                                    FeatureNEON, FeatureDSPThumb2]>;
346def : ProcNoItin<"cortex-a57",      [ProcA57, HasV8Ops, FeatureAClass,
347                                    FeatureDB, FeatureFPARMv8,
348                                    FeatureNEON, FeatureDSPThumb2]>;
349
350//===----------------------------------------------------------------------===//
351// Register File Description
352//===----------------------------------------------------------------------===//
353
354include "ARMRegisterInfo.td"
355
356include "ARMCallingConv.td"
357
358//===----------------------------------------------------------------------===//
359// Instruction Descriptions
360//===----------------------------------------------------------------------===//
361
362include "ARMInstrInfo.td"
363
364def ARMInstrInfo : InstrInfo;
365
366
367//===----------------------------------------------------------------------===//
368// Assembly printer
369//===----------------------------------------------------------------------===//
370// ARM Uses the MC printer for asm output, so make sure the TableGen
371// AsmWriter bits get associated with the correct class.
372def ARMAsmWriter : AsmWriter {
373  string AsmWriterClassName  = "InstPrinter";
374  bit isMCAsmWriter = 1;
375}
376
377//===----------------------------------------------------------------------===//
378// Declare the target which we are implementing
379//===----------------------------------------------------------------------===//
380
381def ARM : Target {
382  // Pull in Instruction Info:
383  let InstructionSet = ARMInstrInfo;
384
385  let AssemblyWriters = [ARMAsmWriter];
386}
387