A15SDOptimizer.cpp revision 263508
11590Srgrimes//=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==// 21590Srgrimes// 31590Srgrimes// The LLVM Compiler Infrastructure 41590Srgrimes// 51590Srgrimes// This file is distributed under the University of Illinois Open Source 61590Srgrimes// License. See LICENSE.TXT for details. 71590Srgrimes// 81590Srgrimes//===----------------------------------------------------------------------===// 91590Srgrimes// 101590Srgrimes// The Cortex-A15 processor employs a tracking scheme in its register renaming 111590Srgrimes// in order to process each instruction's micro-ops speculatively and 121590Srgrimes// out-of-order with appropriate forwarding. The ARM architecture allows VFP 131590Srgrimes// instructions to read and write 32-bit S-registers. Each S-register 141590Srgrimes// corresponds to one half (upper or lower) of an overlaid 64-bit D-register. 151590Srgrimes// 161590Srgrimes// There are several instruction patterns which can be used to provide this 171590Srgrimes// capability which can provide higher performance than other, potentially more 181590Srgrimes// direct patterns, specifically around when one micro-op reads a D-register 191590Srgrimes// operand that has recently been written as one or more S-register results. 201590Srgrimes// 211590Srgrimes// This file defines a pre-regalloc pass which looks for SPR producers which 221590Srgrimes// are going to be used by a DPR (or QPR) consumers and creates the more 231590Srgrimes// optimized access pattern. 241590Srgrimes// 251590Srgrimes//===----------------------------------------------------------------------===// 261590Srgrimes 271590Srgrimes#define DEBUG_TYPE "a15-sd-optimizer" 281590Srgrimes#include "ARM.h" 291590Srgrimes#include "ARMBaseInstrInfo.h" 301590Srgrimes#include "ARMSubtarget.h" 3128203Scharnier#include "ARMISelLowering.h" 321590Srgrimes#include "ARMTargetMachine.h" 331590Srgrimes 341590Srgrimes#include "llvm/ADT/SmallPtrSet.h" 351590Srgrimes#include "llvm/ADT/Statistic.h" 361590Srgrimes#include "llvm/CodeGen/MachineFunctionPass.h" 3728203Scharnier#include "llvm/CodeGen/MachineInstr.h" 381590Srgrimes#include "llvm/CodeGen/MachineInstrBuilder.h" 3928203Scharnier#include "llvm/CodeGen/MachineRegisterInfo.h" 4028203Scharnier#include "llvm/Support/CommandLine.h" 4150477Speter#include "llvm/Support/Debug.h" 421590Srgrimes#include "llvm/Support/raw_ostream.h" 431590Srgrimes#include "llvm/Target/TargetRegisterInfo.h" 441590Srgrimes 451590Srgrimes#include <set> 461590Srgrimes 4717351Sjdpusing namespace llvm; 48120747Syar 4918889Sjkhnamespace { 5017351Sjdp struct A15SDOptimizer : public MachineFunctionPass { 5117351Sjdp static char ID; 5244640Sroberto A15SDOptimizer() : MachineFunctionPass(ID) {} 5372338Sache 54120747Syar virtual bool runOnMachineFunction(MachineFunction &Fn); 55120747Syar 56120747Syar virtual const char *getPassName() const { 57169346Sdwmalone return "ARM A15 S->D optimizer"; 58200462Sdelphij } 5928203Scharnier 601590Srgrimes private: 6192922Simp const ARMBaseInstrInfo *TII; 6292922Simp const TargetRegisterInfo *TRI; 63158560Spjd MachineRegisterInfo *MRI; 64158560Spjd 65158560Spjd bool runOnInstruction(MachineInstr *MI); 6692922Simp 6717351Sjdp // 6872338Sache // Instruction builder helpers 69169346Sdwmalone // 70158560Spjd unsigned createDupLane(MachineBasicBlock &MBB, 7172338Sache MachineBasicBlock::iterator InsertBefore, 7228203Scharnier DebugLoc DL, 73102944Sdwmalone unsigned Reg, unsigned Lane, 741590Srgrimes bool QPR=false); 75158560Spjd 76120747Syar unsigned createExtractSubreg(MachineBasicBlock &MBB, 77120747Syar MachineBasicBlock::iterator InsertBefore, 78120744Syar DebugLoc DL, 791590Srgrimes unsigned DReg, unsigned Lane, 80158560Spjd const TargetRegisterClass *TRC); 81120747Syar 8237888Sdes unsigned createVExt(MachineBasicBlock &MBB, 831590Srgrimes MachineBasicBlock::iterator InsertBefore, 8472338Sache DebugLoc DL, 8572338Sache unsigned Ssub0, unsigned Ssub1); 8672338Sache 8767813Sobrien unsigned createRegSequence(MachineBasicBlock &MBB, 8867813Sobrien MachineBasicBlock::iterator InsertBefore, 891590Srgrimes DebugLoc DL, 9037855Sphk unsigned Reg1, unsigned Reg2); 9137888Sdes 9237855Sphk unsigned createInsertSubreg(MachineBasicBlock &MBB, 9367813Sobrien MachineBasicBlock::iterator InsertBefore, 9467813Sobrien DebugLoc DL, unsigned DReg, unsigned Lane, 9567813Sobrien unsigned ToInsert); 9637913Sdes 9737913Sdes unsigned createImplicitDef(MachineBasicBlock &MBB, 9837913Sdes MachineBasicBlock::iterator InsertBefore, 9937888Sdes DebugLoc DL); 10037888Sdes 10137855Sphk // 10244640Sroberto // Various property checkers 10344640Sroberto // 10444640Sroberto bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC); 1051590Srgrimes bool hasPartialWrite(MachineInstr *MI); 1061590Srgrimes SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI); 10728203Scharnier unsigned getDPRLaneFromSPR(unsigned SReg); 1081590Srgrimes 1091590Srgrimes // 1101590Srgrimes // Methods used for getting the definitions of partial registers 1111590Srgrimes // 1121590Srgrimes 1131590Srgrimes MachineInstr *elideCopies(MachineInstr *MI); 11437888Sdes void elideCopiesAndPHIs(MachineInstr *MI, 115244034Sjilles SmallVectorImpl<MachineInstr*> &Outs); 11637913Sdes 11737913Sdes // 11837888Sdes // Pattern optimization methods 11937855Sphk // 120239991Sed unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg); 12140301Sdes unsigned optimizeSDPattern(MachineInstr *MI); 1221590Srgrimes unsigned getPrefSPRLane(unsigned SReg); 12328203Scharnier 1241590Srgrimes // 1251590Srgrimes // Sanitizing method - used to make sure if don't leave dead code around. 1261590Srgrimes // 12797268Stjr void eraseInstrWithNoUses(MachineInstr *MI); 1281590Srgrimes 1291590Srgrimes // 1301590Srgrimes // A map used to track the changes done by this pass. 1311590Srgrimes // 1321590Srgrimes std::map<MachineInstr*, unsigned> Replacements; 133158560Spjd std::set<MachineInstr *> DeadInstr; 134121153Sseanc }; 135239991Sed char A15SDOptimizer::ID = 0; 13638520Scracauer} // end anonymous namespace 13728203Scharnier 138120747Syar// Returns true if this is a use of a SPR register. 139169346Sdwmalonebool A15SDOptimizer::usesRegClass(MachineOperand &MO, 1401590Srgrimes const TargetRegisterClass *TRC) { 14117351Sjdp if (!MO.isReg()) 14211873Spst return false; 1431590Srgrimes unsigned Reg = MO.getReg(); 1441590Srgrimes 1451590Srgrimes if (TargetRegisterInfo::isVirtualRegister(Reg)) 14611873Spst return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); 14711873Spst else 14811873Spst return TRC->contains(Reg); 14911873Spst} 15011873Spst 15111873Spstunsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { 15211873Spst unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, 15311873Spst &ARM::DPRRegClass); 15437855Sphk if (DReg != ARM::NoRegister) return ARM::ssub_1; 1551590Srgrimes return ARM::ssub_0; 15637855Sphk} 1571590Srgrimes 15837855Sphk// Get the subreg type that is most likely to be coalesced 1591590Srgrimes// for an SPR register that will be used in VDUP32d pseudo. 16037855Sphkunsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { 1611590Srgrimes if (!TRI->isVirtualRegister(SReg)) 16237855Sphk return getDPRLaneFromSPR(SReg); 1631590Srgrimes 16437855Sphk MachineInstr *MI = MRI->getVRegDef(SReg); 1651590Srgrimes if (!MI) return ARM::ssub_0; 16637855Sphk MachineOperand *MO = MI->findRegisterDefOperand(SReg); 1671590Srgrimes 16837855Sphk assert(MO->isReg() && "Non register operand found!"); 1691590Srgrimes if (!MO) return ARM::ssub_0; 17037855Sphk 1711590Srgrimes if (MI->isCopy() && usesRegClass(MI->getOperand(1), 17237855Sphk &ARM::SPRRegClass)) { 1731590Srgrimes SReg = MI->getOperand(1).getReg(); 17437855Sphk } 1751590Srgrimes 17637855Sphk if (TargetRegisterInfo::isVirtualRegister(SReg)) { 1771590Srgrimes if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1; 17837855Sphk return ARM::ssub_0; 1791590Srgrimes } 18037855Sphk return getDPRLaneFromSPR(SReg); 1811590Srgrimes} 1821590Srgrimes 183120747Syar// MI is known to be dead. Figure out what instructions 184120747Syar// are also made dead by this and mark them for removal. 185120747Syarvoid A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) { 186120747Syar SmallVector<MachineInstr *, 8> Front; 187120747Syar DeadInstr.insert(MI); 18838520Scracauer 18987300Sdwmalone DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n"); 190120747Syar Front.push_back(MI); 191120744Syar 192120744Syar while (Front.size() != 0) { 193120744Syar MI = Front.back(); 194120744Syar Front.pop_back(); 19538520Scracauer 196120744Syar // MI is already known to be dead. We need to see 19738520Scracauer // if other instructions can also be removed. 19818889Sjkh for (unsigned int i = 0; i < MI->getNumOperands(); ++i) { 1991590Srgrimes MachineOperand &MO = MI->getOperand(i); 20017351Sjdp if ((!MO.isReg()) || (!MO.isUse())) 20128203Scharnier continue; 202102944Sdwmalone unsigned Reg = MO.getReg(); 20328203Scharnier if (!TRI->isVirtualRegister(Reg)) 20498476Stjr continue; 205146466Sru MachineOperand *Op = MI->findRegisterDefOperand(Reg); 20637913Sdes 20728203Scharnier if (!Op) 20828203Scharnier continue; 20917351Sjdp 21017351Sjdp MachineInstr *Def = Op->getParent(); 21117351Sjdp 21217351Sjdp // We don't need to do anything if we have already marked 213102944Sdwmalone // this instruction as being dead. 21417351Sjdp if (DeadInstr.find(Def) != DeadInstr.end()) 21517351Sjdp continue; 21617351Sjdp 217120747Syar // Check if all the uses of this instruction are marked as 21817351Sjdp // dead. If so, we can also mark this instruction as being 21917351Sjdp // dead. 22017351Sjdp bool IsDead = true; 22117351Sjdp for (unsigned int j = 0; j < Def->getNumOperands(); ++j) { 22217351Sjdp MachineOperand &MODef = Def->getOperand(j); 22317351Sjdp if ((!MODef.isReg()) || (!MODef.isDef())) 22417351Sjdp continue; 22517351Sjdp unsigned DefReg = MODef.getReg(); 22667813Sobrien if (!TRI->isVirtualRegister(DefReg)) { 22767813Sobrien IsDead = false; 228102944Sdwmalone break; 22967813Sobrien } 23067813Sobrien for (MachineRegisterInfo::use_iterator II = MRI->use_begin(Reg), 23167813Sobrien EE = MRI->use_end(); 23267813Sobrien II != EE; ++II) { 23367813Sobrien // We don't care about self references. 23467813Sobrien if (&*II == Def) 23567813Sobrien continue; 23667813Sobrien if (DeadInstr.find(&*II) == DeadInstr.end()) { 23767813Sobrien IsDead = false; 23867813Sobrien break; 23967813Sobrien } 24067813Sobrien } 24167813Sobrien } 24267813Sobrien 24367813Sobrien if (!IsDead) continue; 24467813Sobrien 24567813Sobrien DEBUG(dbgs() << "Deleting instruction " << *Def << "\n"); 24672338Sache DeadInstr.insert(Def); 24767813Sobrien } 248158560Spjd } 249158560Spjd} 250158560Spjd 251158560Spjd// Creates the more optimized patterns and generally does all the code 252158560Spjd// transformations in this pass. 253158560Spjdunsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) { 254158560Spjd if (MI->isCopy()) { 255158560Spjd return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg()); 256158560Spjd } 257158560Spjd 258158560Spjd if (MI->isInsertSubreg()) { 259158560Spjd unsigned DPRReg = MI->getOperand(1).getReg(); 260158560Spjd unsigned SPRReg = MI->getOperand(2).getReg(); 261158560Spjd 262158560Spjd if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) { 263169346Sdwmalone MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); 264169346Sdwmalone MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); 265158560Spjd 266169346Sdwmalone if (DPRMI && SPRMI) { 267169346Sdwmalone // See if the first operand of this insert_subreg is IMPLICIT_DEF 268158560Spjd MachineInstr *ECDef = elideCopies(DPRMI); 269169346Sdwmalone if (ECDef != 0 && ECDef->isImplicitDef()) { 270169346Sdwmalone // Another corner case - if we're inserting something that is purely 271158560Spjd // a subreg copy of a DPR, just use that DPR. 272158560Spjd 273158560Spjd MachineInstr *EC = elideCopies(SPRMI); 274158560Spjd // Is it a subreg copy of ssub_0? 275158560Spjd if (EC && EC->isCopy() && 276158560Spjd EC->getOperand(1).getSubReg() == ARM::ssub_0) { 277158560Spjd DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI); 278158560Spjd 279158560Spjd // Find the thing we're subreg copying out of - is it of the same 280169346Sdwmalone // regclass as DPRMI? (i.e. a DPR or QPR). 281169346Sdwmalone unsigned FullReg = SPRMI->getOperand(1).getReg(); 282158560Spjd const TargetRegisterClass *TRC = 283169346Sdwmalone MRI->getRegClass(MI->getOperand(1).getReg()); 284169346Sdwmalone if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { 285158560Spjd DEBUG(dbgs() << "Subreg copy is compatible - returning "); 286169346Sdwmalone DEBUG(dbgs() << PrintReg(FullReg) << "\n"); 287169346Sdwmalone eraseInstrWithNoUses(MI); 288158560Spjd return FullReg; 289158560Spjd } 290158560Spjd } 291158560Spjd 292158560Spjd return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg()); 293158560Spjd } 294158560Spjd } 295158560Spjd } 296158560Spjd return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg()); 297158560Spjd } 298239991Sed 299158560Spjd if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), 300169346Sdwmalone &ARM::SPRRegClass)) { 301158560Spjd // See if all bar one of the operands are IMPLICIT_DEF and insert the 302 // optimizer pattern accordingly. 303 unsigned NumImplicit = 0, NumTotal = 0; 304 unsigned NonImplicitReg = ~0U; 305 306 for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) { 307 if (!MI->getOperand(I).isReg()) 308 continue; 309 ++NumTotal; 310 unsigned OpReg = MI->getOperand(I).getReg(); 311 312 if (!TRI->isVirtualRegister(OpReg)) 313 break; 314 315 MachineInstr *Def = MRI->getVRegDef(OpReg); 316 if (!Def) 317 break; 318 if (Def->isImplicitDef()) 319 ++NumImplicit; 320 else 321 NonImplicitReg = MI->getOperand(I).getReg(); 322 } 323 324 if (NumImplicit == NumTotal - 1) 325 return optimizeAllLanesPattern(MI, NonImplicitReg); 326 else 327 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg()); 328 } 329 330 assert(0 && "Unhandled update pattern!"); 331 return 0; 332} 333 334// Return true if this MachineInstr inserts a scalar (SPR) value into 335// a D or Q register. 336bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) { 337 // The only way we can do a partial register update is through a COPY, 338 // INSERT_SUBREG or REG_SEQUENCE. 339 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass)) 340 return true; 341 342 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2), 343 &ARM::SPRRegClass)) 344 return true; 345 346 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass)) 347 return true; 348 349 return false; 350} 351 352// Looks through full copies to get the instruction that defines the input 353// operand for MI. 354MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) { 355 if (!MI->isFullCopy()) 356 return MI; 357 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg())) 358 return NULL; 359 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg()); 360 if (!Def) 361 return NULL; 362 return elideCopies(Def); 363} 364 365// Look through full copies and PHIs to get the set of non-copy MachineInstrs 366// that can produce MI. 367void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI, 368 SmallVectorImpl<MachineInstr*> &Outs) { 369 // Looking through PHIs may create loops so we need to track what 370 // instructions we have visited before. 371 std::set<MachineInstr *> Reached; 372 SmallVector<MachineInstr *, 8> Front; 373 Front.push_back(MI); 374 while (Front.size() != 0) { 375 MI = Front.back(); 376 Front.pop_back(); 377 378 // If we have already explored this MachineInstr, ignore it. 379 if (Reached.find(MI) != Reached.end()) 380 continue; 381 Reached.insert(MI); 382 if (MI->isPHI()) { 383 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) { 384 unsigned Reg = MI->getOperand(I).getReg(); 385 if (!TRI->isVirtualRegister(Reg)) { 386 continue; 387 } 388 MachineInstr *NewMI = MRI->getVRegDef(Reg); 389 if (!NewMI) 390 continue; 391 Front.push_back(NewMI); 392 } 393 } else if (MI->isFullCopy()) { 394 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg())) 395 continue; 396 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg()); 397 if (!NewMI) 398 continue; 399 Front.push_back(NewMI); 400 } else { 401 DEBUG(dbgs() << "Found partial copy" << *MI <<"\n"); 402 Outs.push_back(MI); 403 } 404 } 405} 406 407// Return the DPR virtual registers that are read by this machine instruction 408// (if any). 409SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) { 410 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || 411 MI->isKill()) 412 return SmallVector<unsigned, 8>(); 413 414 SmallVector<unsigned, 8> Defs; 415 for (unsigned i = 0; i < MI->getNumOperands(); ++i) { 416 MachineOperand &MO = MI->getOperand(i); 417 418 if (!MO.isReg() || !MO.isUse()) 419 continue; 420 if (!usesRegClass(MO, &ARM::DPRRegClass) && 421 !usesRegClass(MO, &ARM::QPRRegClass)) 422 continue; 423 424 Defs.push_back(MO.getReg()); 425 } 426 return Defs; 427} 428 429// Creates a DPR register from an SPR one by using a VDUP. 430unsigned 431A15SDOptimizer::createDupLane(MachineBasicBlock &MBB, 432 MachineBasicBlock::iterator InsertBefore, 433 DebugLoc DL, 434 unsigned Reg, unsigned Lane, bool QPR) { 435 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : 436 &ARM::DPRRegClass); 437 AddDefaultPred(BuildMI(MBB, 438 InsertBefore, 439 DL, 440 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), 441 Out) 442 .addReg(Reg) 443 .addImm(Lane)); 444 445 return Out; 446} 447 448// Creates a SPR register from a DPR by copying the value in lane 0. 449unsigned 450A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB, 451 MachineBasicBlock::iterator InsertBefore, 452 DebugLoc DL, 453 unsigned DReg, unsigned Lane, 454 const TargetRegisterClass *TRC) { 455 unsigned Out = MRI->createVirtualRegister(TRC); 456 BuildMI(MBB, 457 InsertBefore, 458 DL, 459 TII->get(TargetOpcode::COPY), Out) 460 .addReg(DReg, 0, Lane); 461 462 return Out; 463} 464 465// Takes two SPR registers and creates a DPR by using a REG_SEQUENCE. 466unsigned 467A15SDOptimizer::createRegSequence(MachineBasicBlock &MBB, 468 MachineBasicBlock::iterator InsertBefore, 469 DebugLoc DL, 470 unsigned Reg1, unsigned Reg2) { 471 unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass); 472 BuildMI(MBB, 473 InsertBefore, 474 DL, 475 TII->get(TargetOpcode::REG_SEQUENCE), Out) 476 .addReg(Reg1) 477 .addImm(ARM::dsub_0) 478 .addReg(Reg2) 479 .addImm(ARM::dsub_1); 480 return Out; 481} 482 483// Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1) 484// and merges them into one DPR register. 485unsigned 486A15SDOptimizer::createVExt(MachineBasicBlock &MBB, 487 MachineBasicBlock::iterator InsertBefore, 488 DebugLoc DL, 489 unsigned Ssub0, unsigned Ssub1) { 490 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass); 491 AddDefaultPred(BuildMI(MBB, 492 InsertBefore, 493 DL, 494 TII->get(ARM::VEXTd32), Out) 495 .addReg(Ssub0) 496 .addReg(Ssub1) 497 .addImm(1)); 498 return Out; 499} 500 501unsigned 502A15SDOptimizer::createInsertSubreg(MachineBasicBlock &MBB, 503 MachineBasicBlock::iterator InsertBefore, 504 DebugLoc DL, unsigned DReg, unsigned Lane, 505 unsigned ToInsert) { 506 unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass); 507 BuildMI(MBB, 508 InsertBefore, 509 DL, 510 TII->get(TargetOpcode::INSERT_SUBREG), Out) 511 .addReg(DReg) 512 .addReg(ToInsert) 513 .addImm(Lane); 514 515 return Out; 516} 517 518unsigned 519A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB, 520 MachineBasicBlock::iterator InsertBefore, 521 DebugLoc DL) { 522 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass); 523 BuildMI(MBB, 524 InsertBefore, 525 DL, 526 TII->get(TargetOpcode::IMPLICIT_DEF), Out); 527 return Out; 528} 529 530// This function inserts instructions in order to optimize interactions between 531// SPR registers and DPR/QPR registers. It does so by performing VDUPs on all 532// lanes, and the using VEXT instructions to recompose the result. 533unsigned 534A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) { 535 MachineBasicBlock::iterator InsertPt(MI); 536 DebugLoc DL = MI->getDebugLoc(); 537 MachineBasicBlock &MBB = *MI->getParent(); 538 InsertPt++; 539 unsigned Out; 540 541 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) { 542 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg, 543 ARM::dsub_0, &ARM::DPRRegClass); 544 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg, 545 ARM::dsub_1, &ARM::DPRRegClass); 546 547 unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0); 548 unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1); 549 Out = createVExt(MBB, InsertPt, DL, Out1, Out2); 550 551 unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0); 552 unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1); 553 Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4); 554 555 Out = createRegSequence(MBB, InsertPt, DL, Out, Out2); 556 557 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { 558 unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0); 559 unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1); 560 Out = createVExt(MBB, InsertPt, DL, Out1, Out2); 561 562 } else { 563 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && 564 "Found unexpected regclass!"); 565 566 unsigned PrefLane = getPrefSPRLane(Reg); 567 unsigned Lane; 568 switch (PrefLane) { 569 case ARM::ssub_0: Lane = 0; break; 570 case ARM::ssub_1: Lane = 1; break; 571 default: llvm_unreachable("Unknown preferred lane!"); 572 } 573 574 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass); 575 576 Out = createImplicitDef(MBB, InsertPt, DL); 577 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg); 578 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR); 579 eraseInstrWithNoUses(MI); 580 } 581 return Out; 582} 583 584bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) { 585 // We look for instructions that write S registers that are then read as 586 // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and 587 // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or 588 // merge two SPR values to form a DPR register. In order avoid false 589 // positives we make sure that there is an SPR producer so we look past 590 // COPY and PHI nodes to find it. 591 // 592 // The best code pattern for when an SPR producer is going to be used by a 593 // DPR or QPR consumer depends on whether the other lanes of the 594 // corresponding DPR/QPR are currently defined. 595 // 596 // We can handle these efficiently, depending on the type of 597 // pseudo-instruction that is producing the pattern 598 // 599 // * COPY: * VDUP all lanes and merge the results together 600 // using VEXTs. 601 // 602 // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR 603 // lane, and the other lane(s) of the DPR/QPR register 604 // that we are inserting in are undefined, use the 605 // original DPR/QPR value. 606 // * Otherwise, fall back on the same stategy as COPY. 607 // 608 // * REG_SEQUENCE: * If all except one of the input operands are 609 // IMPLICIT_DEFs, insert the VDUP pattern for just the 610 // defined input operand 611 // * Otherwise, fall back on the same stategy as COPY. 612 // 613 614 // First, get all the reads of D-registers done by this instruction. 615 SmallVector<unsigned, 8> Defs = getReadDPRs(MI); 616 bool Modified = false; 617 618 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end(); 619 I != E; ++I) { 620 // Follow the def-use chain for this DPR through COPYs, and also through 621 // PHIs (which are essentially multi-way COPYs). It is because of PHIs that 622 // we can end up with multiple defs of this DPR. 623 624 SmallVector<MachineInstr *, 8> DefSrcs; 625 if (!TRI->isVirtualRegister(*I)) 626 continue; 627 MachineInstr *Def = MRI->getVRegDef(*I); 628 if (!Def) 629 continue; 630 631 elideCopiesAndPHIs(Def, DefSrcs); 632 633 for (SmallVectorImpl<MachineInstr *>::iterator II = DefSrcs.begin(), 634 EE = DefSrcs.end(); II != EE; ++II) { 635 MachineInstr *MI = *II; 636 637 // If we've already analyzed and replaced this operand, don't do 638 // anything. 639 if (Replacements.find(MI) != Replacements.end()) 640 continue; 641 642 // Now, work out if the instruction causes a SPR->DPR dependency. 643 if (!hasPartialWrite(MI)) 644 continue; 645 646 // Collect all the uses of this MI's DPR def for updating later. 647 SmallVector<MachineOperand*, 8> Uses; 648 unsigned DPRDefReg = MI->getOperand(0).getReg(); 649 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg), 650 E = MRI->use_end(); I != E; ++I) 651 Uses.push_back(&I.getOperand()); 652 653 // We can optimize this. 654 unsigned NewReg = optimizeSDPattern(MI); 655 656 if (NewReg != 0) { 657 Modified = true; 658 for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(), 659 E = Uses.end(); I != E; ++I) { 660 // Make sure to constrain the register class of the new register to 661 // match what we're replacing. Otherwise we can optimize a DPR_VFP2 662 // reference into a plain DPR, and that will end poorly. NewReg is 663 // always virtual here, so there will always be a matching subclass 664 // to find. 665 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); 666 667 DEBUG(dbgs() << "Replacing operand " 668 << **I << " with " 669 << PrintReg(NewReg) << "\n"); 670 (*I)->substVirtReg(NewReg, 0, *TRI); 671 } 672 } 673 Replacements[MI] = NewReg; 674 } 675 } 676 return Modified; 677} 678 679bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) { 680 TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo()); 681 TRI = Fn.getTarget().getRegisterInfo(); 682 MRI = &Fn.getRegInfo(); 683 bool Modified = false; 684 685 DEBUG(dbgs() << "Running on function " << Fn.getName()<< "\n"); 686 687 DeadInstr.clear(); 688 Replacements.clear(); 689 690 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; 691 ++MFI) { 692 693 for (MachineBasicBlock::iterator MI = MFI->begin(), ME = MFI->end(); 694 MI != ME;) { 695 Modified |= runOnInstruction(MI++); 696 } 697 698 } 699 700 for (std::set<MachineInstr *>::iterator I = DeadInstr.begin(), 701 E = DeadInstr.end(); 702 I != E; ++I) { 703 (*I)->eraseFromParent(); 704 } 705 706 return Modified; 707} 708 709FunctionPass *llvm::createA15SDOptimizerPass() { 710 return new A15SDOptimizer(); 711} 712