AArch64InstrInfo.td revision 266715
1//===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the AArch64 scalar instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM Instruction Predicate Definitions. 16// 17def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">; 19def HasNEON : Predicate<"Subtarget->hasNEON()">, 20 AssemblerPredicate<"FeatureNEON", "neon">; 21def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 22 AssemblerPredicate<"FeatureCrypto","crypto">; 23 24// Use fused MAC if more precision in FP computation is allowed. 25def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 26 " FPOpFusion::Fast)">; 27include "AArch64InstrFormats.td" 28 29//===----------------------------------------------------------------------===// 30// Target-specific ISD nodes and profiles 31//===----------------------------------------------------------------------===// 32 33def SDT_A64ret : SDTypeProfile<0, 0, []>; 34def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain, 35 SDNPOptInGlue, 36 SDNPVariadic]>; 37 38// (ins NZCV, Condition, Dest) 39def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>; 40def A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>; 41 42// (outs Result), (ins NZCV, IfTrue, IfFalse, Condition) 43def SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>, 44 SDTCisSameAs<0, 2>, 45 SDTCisSameAs<2, 3>]>; 46def A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>; 47 48// (outs NZCV), (ins LHS, RHS, Condition) 49def SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, 50 SDTCisSameAs<1, 2>]>; 51def A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>; 52 53 54// (outs GPR64), (ins) 55def A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>; 56 57// A64 compares don't care about the cond really (they set all flags) so a 58// simple binary operator is useful. 59def A64cmp : PatFrag<(ops node:$lhs, node:$rhs), 60 (A64setcc node:$lhs, node:$rhs, cond)>; 61 62 63// When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN 64// instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C 65// and V flags can be set differently by this operation. It comes down to 66// whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are 67// then everything is fine. If not then the optimization is wrong. Thus general 68// comparisons are only valid if op2 != 0. 69 70// So, finally, the only LLVM-native comparisons that don't mention C and V are 71// SETEQ and SETNE. They're the only ones we can safely use CMN for in the 72// absence of information about op2. 73def equality_cond : PatLeaf<(cond), [{ 74 return N->get() == ISD::SETEQ || N->get() == ISD::SETNE; 75}]>; 76 77def A64cmn : PatFrag<(ops node:$lhs, node:$rhs), 78 (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>; 79 80// There are two layers of indirection here, driven by the following 81// considerations. 82// + TableGen does not know CodeModel or Reloc so that decision should be 83// made for a variable/address at ISelLowering. 84// + The output of ISelLowering should be selectable (hence the Wrapper, 85// rather than a bare target opcode) 86def SDTAArch64WrapperLarge : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 87 SDTCisSameAs<0, 2>, 88 SDTCisSameAs<0, 3>, 89 SDTCisSameAs<0, 4>, 90 SDTCisPtrTy<0>]>; 91 92def A64WrapperLarge :SDNode<"AArch64ISD::WrapperLarge", SDTAArch64WrapperLarge>; 93 94def SDTAArch64WrapperSmall : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 95 SDTCisSameAs<1, 2>, 96 SDTCisVT<3, i32>, 97 SDTCisPtrTy<0>]>; 98 99def A64WrapperSmall :SDNode<"AArch64ISD::WrapperSmall", SDTAArch64WrapperSmall>; 100 101 102def SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 103def A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad, 104 [SDNPHasChain]>; 105 106 107// (A64BFI LHS, RHS, LSB, Width) 108def SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 109 SDTCisSameAs<1, 2>, 110 SDTCisVT<3, i64>, 111 SDTCisVT<4, i64>]>; 112 113def A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>; 114 115// (A64EXTR HiReg, LoReg, LSB) 116def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 117 SDTCisVT<3, i64>]>; 118def A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>; 119 120// (A64[SU]BFX Field, ImmR, ImmS). 121// 122// Note that ImmR and ImmS are already encoded for the actual instructions. The 123// more natural LSB and Width mix together to form ImmR and ImmS, something 124// which TableGen can't handle. 125def SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>; 126def A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>; 127 128def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>; 129 130class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 131 132//===----------------------------------------------------------------------===// 133// Call sequence pseudo-instructions 134//===----------------------------------------------------------------------===// 135 136 137def SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 138def AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call, 139 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 140 141def AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call, 142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 143 144// The TLSDESCCALL node is a variant call which goes to an indirectly calculated 145// destination but needs a relocation against a fixed symbol. As such it has two 146// certain operands: the callee and the relocated variable. 147// 148// The TLS ABI only allows it to be selected to a BLR instructin (with 149// appropriate relocation). 150def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 151 152def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall, 153 [SDNPInGlue, SDNPOutGlue, SDNPHasChain, 154 SDNPVariadic]>; 155 156 157def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>; 158def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart, 159 [SDNPHasChain, SDNPOutGlue]>; 160 161def SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>; 162def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd, 163 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 164 165 166 167// These pseudo-instructions have special semantics by virtue of being passed to 168// the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by 169// LowerCall to (in our case) tell the back-end about stack adjustments for 170// arguments passed on the stack. Here we select those markers to 171// pseudo-instructions which explicitly set the stack, and finally in the 172// RegisterInfo we convert them to a true stack adjustment. 173let Defs = [XSP], Uses = [XSP] in { 174 def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt), 175 [(AArch64callseq_start timm:$amt)]>; 176 177 def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2), 178 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>; 179} 180 181//===----------------------------------------------------------------------===// 182// Atomic operation pseudo-instructions 183//===----------------------------------------------------------------------===// 184 185// These get selected from C++ code as a pretty much direct translation from the 186// generic DAG nodes. The one exception is the AtomicOrdering is added as an 187// operand so that the eventual lowering can make use of it and choose 188// acquire/release operations when required. 189 190let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in { 191multiclass AtomicSizes { 192 def _I8 : PseudoInst<(outs GPR32:$dst), 193 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>; 194 def _I16 : PseudoInst<(outs GPR32:$dst), 195 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>; 196 def _I32 : PseudoInst<(outs GPR32:$dst), 197 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>; 198 def _I64 : PseudoInst<(outs GPR64:$dst), 199 (ins GPR64xsp:$ptr, GPR64:$incr, i32imm:$ordering), []>; 200} 201} 202 203defm ATOMIC_LOAD_ADD : AtomicSizes; 204defm ATOMIC_LOAD_SUB : AtomicSizes; 205defm ATOMIC_LOAD_AND : AtomicSizes; 206defm ATOMIC_LOAD_OR : AtomicSizes; 207defm ATOMIC_LOAD_XOR : AtomicSizes; 208defm ATOMIC_LOAD_NAND : AtomicSizes; 209defm ATOMIC_SWAP : AtomicSizes; 210let Defs = [NZCV] in { 211 // These operations need a CMP to calculate the correct value 212 defm ATOMIC_LOAD_MIN : AtomicSizes; 213 defm ATOMIC_LOAD_MAX : AtomicSizes; 214 defm ATOMIC_LOAD_UMIN : AtomicSizes; 215 defm ATOMIC_LOAD_UMAX : AtomicSizes; 216} 217 218class AtomicCmpSwap<RegisterClass GPRData> 219 : PseudoInst<(outs GPRData:$dst), 220 (ins GPR64xsp:$ptr, GPRData:$old, GPRData:$new, 221 i32imm:$ordering), []> { 222 let usesCustomInserter = 1; 223 let hasCtrlDep = 1; 224 let mayLoad = 1; 225 let mayStore = 1; 226 let Defs = [NZCV]; 227} 228 229def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>; 230def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>; 231def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>; 232def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>; 233 234//===----------------------------------------------------------------------===// 235// Add-subtract (extended register) instructions 236//===----------------------------------------------------------------------===// 237// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP 238 239// The RHS of these operations is conceptually a sign/zero-extended 240// register, optionally shifted left by 1-4. The extension can be a 241// NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but 242// must be specified with one exception: 243 244// If one of the registers is sp/wsp then LSL is an alias for UXTW in 245// 32-bit instructions and UXTX in 64-bit versions, the shift amount 246// is not optional in that case (but can explicitly be 0), and the 247// entire suffix can be skipped (e.g. "add sp, x3, x2"). 248 249multiclass extend_operands<string PREFIX, string Diag> { 250 def _asmoperand : AsmOperandClass { 251 let Name = PREFIX; 252 let RenderMethod = "addRegExtendOperands"; 253 let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">"; 254 let DiagnosticType = "AddSubRegExtend" # Diag; 255 } 256 257 def _operand : Operand<i64>, 258 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> { 259 let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">"; 260 let DecoderMethod = "DecodeRegExtendOperand"; 261 let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand"); 262 } 263} 264 265defm UXTB : extend_operands<"UXTB", "Small">; 266defm UXTH : extend_operands<"UXTH", "Small">; 267defm UXTW : extend_operands<"UXTW", "Small">; 268defm UXTX : extend_operands<"UXTX", "Large">; 269defm SXTB : extend_operands<"SXTB", "Small">; 270defm SXTH : extend_operands<"SXTH", "Small">; 271defm SXTW : extend_operands<"SXTW", "Small">; 272defm SXTX : extend_operands<"SXTX", "Large">; 273 274def LSL_extasmoperand : AsmOperandClass { 275 let Name = "RegExtendLSL"; 276 let RenderMethod = "addRegExtendOperands"; 277 let DiagnosticType = "AddSubRegExtendLarge"; 278} 279 280def LSL_extoperand : Operand<i64> { 281 let ParserMatchClass = LSL_extasmoperand; 282} 283 284 285// The patterns for various sign-extensions are a little ugly and 286// non-uniform because everything has already been promoted to the 287// legal i64 and i32 types. We'll wrap the various variants up in a 288// class for use later. 289class extend_types { 290 dag uxtb; dag uxth; dag uxtw; dag uxtx; 291 dag sxtb; dag sxth; dag sxtw; dag sxtx; 292 ValueType ty; 293 RegisterClass GPR; 294} 295 296def extends_to_i64 : extend_types { 297 let uxtb = (and (anyext i32:$Rm), 255); 298 let uxth = (and (anyext i32:$Rm), 65535); 299 let uxtw = (zext i32:$Rm); 300 let uxtx = (i64 $Rm); 301 302 let sxtb = (sext_inreg (anyext i32:$Rm), i8); 303 let sxth = (sext_inreg (anyext i32:$Rm), i16); 304 let sxtw = (sext i32:$Rm); 305 let sxtx = (i64 $Rm); 306 307 let ty = i64; 308 let GPR = GPR64xsp; 309} 310 311 312def extends_to_i32 : extend_types { 313 let uxtb = (and i32:$Rm, 255); 314 let uxth = (and i32:$Rm, 65535); 315 let uxtw = (i32 i32:$Rm); 316 let uxtx = (i32 i32:$Rm); 317 318 let sxtb = (sext_inreg i32:$Rm, i8); 319 let sxth = (sext_inreg i32:$Rm, i16); 320 let sxtw = (i32 i32:$Rm); 321 let sxtx = (i32 i32:$Rm); 322 323 let ty = i32; 324 let GPR = GPR32wsp; 325} 326 327// Now, six of the extensions supported are easy and uniform: if the source size 328// is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate 329// those instructions in one block. 330 331// The uxtx/sxtx could potentially be merged in, but three facts dissuaded me: 332// + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would 333// be impossible. 334// + Patterns are very different as well. 335// + Passing different registers would be ugly (more fields in extend_types 336// would probably be the best option). 337multiclass addsub_exts<bit sf, bit op, bit S, string asmop, 338 SDPatternOperator opfrag, 339 dag outs, extend_types exts> { 340 def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000, 341 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3), 342 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 343 [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))], 344 NoItinerary>; 345 def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001, 346 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3), 347 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 348 [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))], 349 NoItinerary>; 350 def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010, 351 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3), 352 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 353 [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))], 354 NoItinerary>; 355 356 def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100, 357 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3), 358 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 359 [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))], 360 NoItinerary>; 361 def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101, 362 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3), 363 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 364 [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))], 365 NoItinerary>; 366 def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110, 367 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3), 368 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 369 [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))], 370 NoItinerary>; 371} 372 373// These two could be merge in with the above, but their patterns aren't really 374// necessary and the naming-scheme would necessarily break: 375multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag, 376 dag outs> { 377 def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011, 378 outs, 379 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3), 380 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 381 [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))], 382 NoItinerary>; 383 384 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111, 385 outs, 386 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3), 387 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 388 [/* No Pattern: same as uxtx */], 389 NoItinerary>; 390} 391 392multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> { 393 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011, 394 outs, 395 (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3), 396 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 397 [/* No pattern: probably same as uxtw */], 398 NoItinerary>; 399 400 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111, 401 outs, 402 (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3), 403 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 404 [/* No Pattern: probably same as uxtw */], 405 NoItinerary>; 406} 407 408class SetRD<RegisterClass RC, SDPatternOperator op> 409 : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>; 410class SetNZCV<SDPatternOperator op> 411 : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>; 412 413defm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>, 414 (outs GPR64xsp:$Rd), extends_to_i64>, 415 addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>, 416 (outs GPR64xsp:$Rd)>; 417defm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>, 418 (outs GPR32wsp:$Rd), extends_to_i32>, 419 addsub_wxtx< 0b0, 0b0, "add\t$Rd, ", 420 (outs GPR32wsp:$Rd)>; 421defm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>, 422 (outs GPR64xsp:$Rd), extends_to_i64>, 423 addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>, 424 (outs GPR64xsp:$Rd)>; 425defm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>, 426 (outs GPR32wsp:$Rd), extends_to_i32>, 427 addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ", 428 (outs GPR32wsp:$Rd)>; 429 430let Defs = [NZCV] in { 431defm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>, 432 (outs GPR64:$Rd), extends_to_i64>, 433 addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>, 434 (outs GPR64:$Rd)>; 435defm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>, 436 (outs GPR32:$Rd), extends_to_i32>, 437 addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ", 438 (outs GPR32:$Rd)>; 439defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>, 440 (outs GPR64:$Rd), extends_to_i64>, 441 addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>, 442 (outs GPR64:$Rd)>; 443defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>, 444 (outs GPR32:$Rd), extends_to_i32>, 445 addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ", 446 (outs GPR32:$Rd)>; 447 448 449let Rd = 0b11111, isCompare = 1 in { 450defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, 451 (outs), extends_to_i64>, 452 addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>; 453defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, 454 (outs), extends_to_i32>, 455 addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>; 456defm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, 457 (outs), extends_to_i64>, 458 addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>; 459defm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, 460 (outs), extends_to_i32>, 461 addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>; 462} 463} 464 465// Now patterns for the operation without a shift being needed. No patterns are 466// created for uxtx/sxtx since they're non-uniform and it's expected that 467// add/sub (shifted register) will handle those cases anyway. 468multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop, 469 extend_types exts> { 470 def : Pat<(nodeop exts.ty:$Rn, exts.uxtb), 471 (!cast<Instruction>(prefix # "w_uxtb") $Rn, $Rm, 0)>; 472 def : Pat<(nodeop exts.ty:$Rn, exts.uxth), 473 (!cast<Instruction>(prefix # "w_uxth") $Rn, $Rm, 0)>; 474 def : Pat<(nodeop exts.ty:$Rn, exts.uxtw), 475 (!cast<Instruction>(prefix # "w_uxtw") $Rn, $Rm, 0)>; 476 477 def : Pat<(nodeop exts.ty:$Rn, exts.sxtb), 478 (!cast<Instruction>(prefix # "w_sxtb") $Rn, $Rm, 0)>; 479 def : Pat<(nodeop exts.ty:$Rn, exts.sxth), 480 (!cast<Instruction>(prefix # "w_sxth") $Rn, $Rm, 0)>; 481 def : Pat<(nodeop exts.ty:$Rn, exts.sxtw), 482 (!cast<Instruction>(prefix # "w_sxtw") $Rn, $Rm, 0)>; 483} 484 485defm : addsubext_noshift_patterns<"ADDxx", add, extends_to_i64>; 486defm : addsubext_noshift_patterns<"ADDww", add, extends_to_i32>; 487defm : addsubext_noshift_patterns<"SUBxx", sub, extends_to_i64>; 488defm : addsubext_noshift_patterns<"SUBww", sub, extends_to_i32>; 489 490defm : addsubext_noshift_patterns<"CMNx", A64cmn, extends_to_i64>; 491defm : addsubext_noshift_patterns<"CMNw", A64cmn, extends_to_i32>; 492defm : addsubext_noshift_patterns<"CMPx", A64cmp, extends_to_i64>; 493defm : addsubext_noshift_patterns<"CMPw", A64cmp, extends_to_i32>; 494 495// An extend of "lsl #imm" is valid if and only if one of Rn and Rd is 496// sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the 497// operation. Also permitted in this case is complete omission of the argument, 498// which implies "lsl #0". 499multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd, 500 RegisterClass GPR_Rn, RegisterClass GPR_Rm> { 501 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 502 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>; 503 504 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"), 505 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>; 506 507} 508 509defm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>; 510defm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>; 511defm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>; 512defm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>; 513defm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>; 514defm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>; 515defm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>; 516defm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>; 517 518// Rd cannot be sp for flag-setting variants so only half of the aliases are 519// needed. 520defm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>; 521defm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>; 522defm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>; 523defm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>; 524 525// CMP unfortunately has to be different because the instruction doesn't have a 526// dest register. 527multiclass cmp_lsl_aliases<string asmop, Instruction inst, 528 RegisterClass GPR_Rn, RegisterClass GPR_Rm> { 529 def : InstAlias<!strconcat(asmop, " $Rn, $Rm"), 530 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>; 531 532 def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"), 533 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>; 534} 535 536defm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>; 537defm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>; 538defm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>; 539defm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>; 540 541//===----------------------------------------------------------------------===// 542// Add-subtract (immediate) instructions 543//===----------------------------------------------------------------------===// 544// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV 545 546// These instructions accept a 12-bit unsigned immediate, optionally shifted 547// left by 12 bits. Official assembly format specifies a 12 bit immediate with 548// one of "", "LSL #0", "LSL #12" supplementary operands. 549 550// There are surprisingly few ways to make this work with TableGen, so this 551// implementation has separate instructions for the "LSL #0" and "LSL #12" 552// variants. 553 554// If the MCInst retained a single combined immediate (which could be 0x123000, 555// for example) then both components (imm & shift) would have to be delegated to 556// a single assembly operand. This would entail a separate operand parser 557// (because the LSL would have to live in the same AArch64Operand as the 558// immediate to be accessible); assembly parsing is rather complex and 559// error-prone C++ code. 560// 561// By splitting the immediate, we can delegate handling this optional operand to 562// an InstAlias. Supporting functions to generate the correct MCInst are still 563// required, but these are essentially trivial and parsing can remain generic. 564// 565// Rejected plans with rationale: 566// ------------------------------ 567// 568// In an ideal world you'de have two first class immediate operands (in 569// InOperandList, specifying imm12 and shift). Unfortunately this is not 570// selectable by any means I could discover. 571// 572// An Instruction with two MCOperands hidden behind a single entry in 573// InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional, 574// but required more C++ code to handle encoding/decoding. Parsing (the intended 575// main beneficiary) ended up equally complex because of the optional nature of 576// "LSL #0". 577// 578// Attempting to circumvent the need for a custom OperandParser above by giving 579// InstAliases without the "lsl #0" failed. add/sub could be accommodated but 580// the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands 581// should be parsed: there was no way to accommodate an "lsl #12". 582 583let ParserMethod = "ParseImmWithLSLOperand", 584 RenderMethod = "addImmWithLSLOperands" in { 585 // Derived PredicateMethod fields are different for each 586 def addsubimm_lsl0_asmoperand : AsmOperandClass { 587 let Name = "AddSubImmLSL0"; 588 // If an error is reported against this operand, instruction could also be a 589 // register variant. 590 let DiagnosticType = "AddSubSecondSource"; 591 } 592 593 def addsubimm_lsl12_asmoperand : AsmOperandClass { 594 let Name = "AddSubImmLSL12"; 595 let DiagnosticType = "AddSubSecondSource"; 596 } 597} 598 599def shr_12_XFORM : SDNodeXForm<imm, [{ 600 return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32); 601}]>; 602 603def shr_12_neg_XFORM : SDNodeXForm<imm, [{ 604 return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32); 605}]>; 606 607def neg_XFORM : SDNodeXForm<imm, [{ 608 return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32); 609}]>; 610 611 612multiclass addsub_imm_operands<ValueType ty> { 613 let PrintMethod = "printAddSubImmLSL0Operand", 614 EncoderMethod = "getAddSubImmOpValue", 615 ParserMatchClass = addsubimm_lsl0_asmoperand in { 616 def _posimm_lsl0 : Operand<ty>, 617 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>; 618 def _negimm_lsl0 : Operand<ty>, 619 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }], 620 neg_XFORM>; 621 } 622 623 let PrintMethod = "printAddSubImmLSL12Operand", 624 EncoderMethod = "getAddSubImmOpValue", 625 ParserMatchClass = addsubimm_lsl12_asmoperand in { 626 def _posimm_lsl12 : Operand<ty>, 627 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }], 628 shr_12_XFORM>; 629 630 def _negimm_lsl12 : Operand<ty>, 631 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }], 632 shr_12_neg_XFORM>; 633 } 634} 635 636// The add operands don't need any transformation 637defm addsubimm_operand_i32 : addsub_imm_operands<i32>; 638defm addsubimm_operand_i64 : addsub_imm_operands<i64>; 639 640multiclass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift, 641 string asmop, string cmpasmop, 642 Operand imm_operand, Operand cmp_imm_operand, 643 RegisterClass GPR, RegisterClass GPRsp, 644 AArch64Reg ZR, ValueType Ty> { 645 // All registers for non-S variants allow SP 646 def _s : A64I_addsubimm<sf, op, 0b0, shift, 647 (outs GPRsp:$Rd), 648 (ins GPRsp:$Rn, imm_operand:$Imm12), 649 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"), 650 [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))], 651 NoItinerary>; 652 653 654 // S variants can read SP but would write to ZR 655 def _S : A64I_addsubimm<sf, op, 0b1, shift, 656 (outs GPR:$Rd), 657 (ins GPRsp:$Rn, imm_operand:$Imm12), 658 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"), 659 [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))], 660 NoItinerary> { 661 let Defs = [NZCV]; 662 } 663 664 // Note that the pattern here for ADDS is subtle. Canonically CMP 665 // a, b becomes SUBS a, b. If b < 0 then this is equivalent to 666 // ADDS a, (-b). This is not true in general. 667 def _cmp : A64I_addsubimm<sf, op, 0b1, shift, 668 (outs), (ins GPRsp:$Rn, imm_operand:$Imm12), 669 !strconcat(cmpasmop, " $Rn, $Imm12"), 670 [(set NZCV, 671 (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))], 672 NoItinerary> { 673 let Rd = 0b11111; 674 let Defs = [NZCV]; 675 let isCompare = 1; 676 } 677} 678 679 680multiclass addsubimm_shifts<string prefix, bit sf, bit op, 681 string asmop, string cmpasmop, string operand, string cmpoperand, 682 RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR, 683 ValueType Ty> { 684 defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00, 685 asmop, cmpasmop, 686 !cast<Operand>(operand # "_lsl0"), 687 !cast<Operand>(cmpoperand # "_lsl0"), 688 GPR, GPRsp, ZR, Ty>; 689 690 defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01, 691 asmop, cmpasmop, 692 !cast<Operand>(operand # "_lsl12"), 693 !cast<Operand>(cmpoperand # "_lsl12"), 694 GPR, GPRsp, ZR, Ty>; 695} 696 697defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn", 698 "addsubimm_operand_i32_posimm", 699 "addsubimm_operand_i32_negimm", 700 GPR32, GPR32wsp, WZR, i32>; 701defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn", 702 "addsubimm_operand_i64_posimm", 703 "addsubimm_operand_i64_negimm", 704 GPR64, GPR64xsp, XZR, i64>; 705defm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp", 706 "addsubimm_operand_i32_negimm", 707 "addsubimm_operand_i32_posimm", 708 GPR32, GPR32wsp, WZR, i32>; 709defm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp", 710 "addsubimm_operand_i64_negimm", 711 "addsubimm_operand_i64_posimm", 712 GPR64, GPR64xsp, XZR, i64>; 713 714multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> { 715 def _fromsp : InstAlias<"mov $Rd, $Rn", 716 (addop GPRsp:$Rd, SP:$Rn, 0), 717 0b1>; 718 719 def _tosp : InstAlias<"mov $Rd, $Rn", 720 (addop SP:$Rd, GPRsp:$Rn, 0), 721 0b1>; 722} 723 724// Recall Rxsp is a RegisterClass containing *just* xsp. 725defm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>; 726defm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>; 727 728//===----------------------------------------------------------------------===// 729// Add-subtract (shifted register) instructions 730//===----------------------------------------------------------------------===// 731// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS 732 733//===------------------------------- 734// 1. The "shifed register" operands. Shared with logical insts. 735//===------------------------------- 736 737multiclass shift_operands<string prefix, string form> { 738 def _asmoperand_i32 : AsmOperandClass { 739 let Name = "Shift" # form # "i32"; 740 let RenderMethod = "addShiftOperands"; 741 let PredicateMethod = "isShift<A64SE::" # form # ", false>"; 742 let DiagnosticType = "AddSubRegShift32"; 743 } 744 745 // Note that the operand type is intentionally i64 because the DAGCombiner 746 // puts these into a canonical form. 747 def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 748 let ParserMatchClass 749 = !cast<AsmOperandClass>(prefix # "_asmoperand_i32"); 750 let PrintMethod = "printShiftOperand<A64SE::" # form # ">"; 751 let DecoderMethod = "Decode32BitShiftOperand"; 752 } 753 754 def _asmoperand_i64 : AsmOperandClass { 755 let Name = "Shift" # form # "i64"; 756 let RenderMethod = "addShiftOperands"; 757 let PredicateMethod = "isShift<A64SE::" # form # ", true>"; 758 let DiagnosticType = "AddSubRegShift64"; 759 } 760 761 def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 762 let ParserMatchClass 763 = !cast<AsmOperandClass>(prefix # "_asmoperand_i64"); 764 let PrintMethod = "printShiftOperand<A64SE::" # form # ">"; 765 } 766} 767 768defm lsl_operand : shift_operands<"lsl_operand", "LSL">; 769defm lsr_operand : shift_operands<"lsr_operand", "LSR">; 770defm asr_operand : shift_operands<"asr_operand", "ASR">; 771 772// Not used for add/sub, but defined here for completeness. The "logical 773// (shifted register)" instructions *do* have an ROR variant. 774defm ror_operand : shift_operands<"ror_operand", "ROR">; 775 776//===------------------------------- 777// 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions. 778//===------------------------------- 779 780// N.b. the commutable parameter is just !N. It will be first against the wall 781// when the revolution comes. 782multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable, 783 string asmop, SDPatternOperator opfrag, ValueType ty, 784 RegisterClass GPR, list<Register> defs> { 785 let isCommutable = commutable, Defs = defs in { 786 def _lsl : A64I_addsubshift<sf, op, s, 0b00, 787 (outs GPR:$Rd), 788 (ins GPR:$Rn, GPR:$Rm, 789 !cast<Operand>("lsl_operand_" # ty):$Imm6), 790 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 791 [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm, 792 !cast<Operand>("lsl_operand_" # ty):$Imm6)) 793 )], 794 NoItinerary>; 795 796 def _lsr : A64I_addsubshift<sf, op, s, 0b01, 797 (outs GPR:$Rd), 798 (ins GPR:$Rn, GPR:$Rm, 799 !cast<Operand>("lsr_operand_" # ty):$Imm6), 800 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 801 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm, 802 !cast<Operand>("lsr_operand_" # ty):$Imm6)) 803 )], 804 NoItinerary>; 805 806 def _asr : A64I_addsubshift<sf, op, s, 0b10, 807 (outs GPR:$Rd), 808 (ins GPR:$Rn, GPR:$Rm, 809 !cast<Operand>("asr_operand_" # ty):$Imm6), 810 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 811 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm, 812 !cast<Operand>("asr_operand_" # ty):$Imm6)) 813 )], 814 NoItinerary>; 815 } 816 817 def _noshift 818 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 819 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn, 820 GPR:$Rm, 0)>; 821 822 def : Pat<(opfrag ty:$Rn, ty:$Rm), 823 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 824} 825 826multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable, 827 string asmop, SDPatternOperator opfrag, 828 list<Register> defs> { 829 defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s, 830 commutable, asmop, opfrag, i64, GPR64, defs>; 831 defm www : addsub_shifts<prefix # "www", 0b0, op, s, 832 commutable, asmop, opfrag, i32, GPR32, defs>; 833} 834 835 836defm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>; 837defm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>; 838 839defm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>; 840defm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>; 841 842//===------------------------------- 843// 1. The NEG/NEGS aliases 844//===------------------------------- 845 846multiclass neg_alias<Instruction INST, RegisterClass GPR, Register ZR, 847 ValueType ty, Operand shift_operand, SDNode shiftop> { 848 def : InstAlias<"neg $Rd, $Rm, $Imm6", 849 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>; 850 851 def : Pat<(sub 0, (shiftop ty:$Rm, shift_operand:$Imm6)), 852 (INST ZR, $Rm, shift_operand:$Imm6)>; 853} 854 855defm : neg_alias<SUBwww_lsl, GPR32, WZR, i32, lsl_operand_i32, shl>; 856defm : neg_alias<SUBwww_lsr, GPR32, WZR, i32, lsr_operand_i32, srl>; 857defm : neg_alias<SUBwww_asr, GPR32, WZR, i32, asr_operand_i32, sra>; 858def : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 859def : Pat<(sub 0, i32:$Rm), (SUBwww_lsl WZR, $Rm, 0)>; 860 861defm : neg_alias<SUBxxx_lsl, GPR64, XZR, i64, lsl_operand_i64, shl>; 862defm : neg_alias<SUBxxx_lsr, GPR64, XZR, i64, lsr_operand_i64, srl>; 863defm : neg_alias<SUBxxx_asr, GPR64, XZR, i64, asr_operand_i64, sra>; 864def : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 865def : Pat<(sub 0, i64:$Rm), (SUBxxx_lsl XZR, $Rm, 0)>; 866 867// NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to 868// be involved. 869class negs_alias<Instruction INST, RegisterClass GPR, 870 Register ZR, Operand shift_operand, SDNode shiftop> 871 : InstAlias<"negs $Rd, $Rm, $Imm6", 872 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>; 873 874def : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>; 875def : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>; 876def : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>; 877def : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 878 879def : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>; 880def : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>; 881def : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>; 882def : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 883 884//===------------------------------- 885// 1. The CMP/CMN aliases 886//===------------------------------- 887 888multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable, 889 string asmop, SDPatternOperator opfrag, ValueType ty, 890 RegisterClass GPR> { 891 let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in { 892 def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00, 893 (outs), 894 (ins GPR:$Rn, GPR:$Rm, 895 !cast<Operand>("lsl_operand_" # ty):$Imm6), 896 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 897 [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm, 898 !cast<Operand>("lsl_operand_" # ty):$Imm6)) 899 )], 900 NoItinerary>; 901 902 def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01, 903 (outs), 904 (ins GPR:$Rn, GPR:$Rm, 905 !cast<Operand>("lsr_operand_" # ty):$Imm6), 906 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 907 [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm, 908 !cast<Operand>("lsr_operand_" # ty):$Imm6)) 909 )], 910 NoItinerary>; 911 912 def _asr : A64I_addsubshift<sf, op, 0b1, 0b10, 913 (outs), 914 (ins GPR:$Rn, GPR:$Rm, 915 !cast<Operand>("asr_operand_" # ty):$Imm6), 916 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 917 [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm, 918 !cast<Operand>("asr_operand_" # ty):$Imm6)) 919 )], 920 NoItinerary>; 921 } 922 923 def _noshift 924 : InstAlias<!strconcat(asmop, " $Rn, $Rm"), 925 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 926 927 def : Pat<(opfrag ty:$Rn, ty:$Rm), 928 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 929} 930 931defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, i32, GPR32>; 932defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, i64, GPR64>; 933 934defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, i32, GPR32>; 935defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, i64, GPR64>; 936 937//===----------------------------------------------------------------------===// 938// Add-subtract (with carry) instructions 939//===----------------------------------------------------------------------===// 940// Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS 941 942multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> { 943 let Uses = [NZCV] in { 944 def www : A64I_addsubcarry<0b0, op, s, 0b000000, 945 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm), 946 !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 947 [], NoItinerary>; 948 949 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000, 950 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm), 951 !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 952 [], NoItinerary>; 953 } 954} 955 956let isCommutable = 1 in { 957 defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">; 958} 959 960defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">; 961 962let Defs = [NZCV] in { 963 let isCommutable = 1 in { 964 defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">; 965 } 966 967 defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">; 968} 969 970def : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>; 971def : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>; 972def : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>; 973def : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>; 974 975// Note that adde and sube can form a chain longer than two (e.g. for 256-bit 976// addition). So the flag-setting instructions are appropriate. 977def : Pat<(adde i32:$Rn, i32:$Rm), (ADCSwww $Rn, $Rm)>; 978def : Pat<(adde i64:$Rn, i64:$Rm), (ADCSxxx $Rn, $Rm)>; 979def : Pat<(sube i32:$Rn, i32:$Rm), (SBCSwww $Rn, $Rm)>; 980def : Pat<(sube i64:$Rn, i64:$Rm), (SBCSxxx $Rn, $Rm)>; 981 982//===----------------------------------------------------------------------===// 983// Bitfield 984//===----------------------------------------------------------------------===// 985// Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL, 986// UBFIZ, UBFX 987 988// Because of the rather complicated nearly-overlapping aliases, the decoding of 989// this range of instructions is handled manually. The architectural 990// instructions are BFM, SBFM and UBFM but a disassembler should never produce 991// these. 992// 993// In the end, the best option was to use BFM instructions for decoding under 994// almost all circumstances, but to create aliasing *Instructions* for each of 995// the canonical forms and specify a completely custom decoder which would 996// substitute the correct MCInst as needed. 997// 998// This also simplifies instruction selection, parsing etc because the MCInsts 999// have a shape that's closer to their use in code. 1000 1001//===------------------------------- 1002// 1. The architectural BFM instructions 1003//===------------------------------- 1004 1005def uimm5_asmoperand : AsmOperandClass { 1006 let Name = "UImm5"; 1007 let PredicateMethod = "isUImm<5>"; 1008 let RenderMethod = "addImmOperands"; 1009 let DiagnosticType = "UImm5"; 1010} 1011 1012def uimm6_asmoperand : AsmOperandClass { 1013 let Name = "UImm6"; 1014 let PredicateMethod = "isUImm<6>"; 1015 let RenderMethod = "addImmOperands"; 1016 let DiagnosticType = "UImm6"; 1017} 1018 1019def bitfield32_imm : Operand<i64>, 1020 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> { 1021 let ParserMatchClass = uimm5_asmoperand; 1022 1023 let DecoderMethod = "DecodeBitfield32ImmOperand"; 1024} 1025 1026 1027def bitfield64_imm : Operand<i64>, 1028 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> { 1029 let ParserMatchClass = uimm6_asmoperand; 1030 1031 // Default decoder works in 64-bit case: the 6-bit field can take any value. 1032} 1033 1034multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> { 1035 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1036 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS), 1037 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1038 [], NoItinerary> { 1039 let DecoderMethod = "DecodeBitfieldInstruction"; 1040 } 1041 1042 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1043 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS), 1044 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1045 [], NoItinerary> { 1046 let DecoderMethod = "DecodeBitfieldInstruction"; 1047 } 1048} 1049 1050defm SBFM : A64I_bitfieldSizes<0b00, "sbfm">; 1051defm UBFM : A64I_bitfieldSizes<0b10, "ubfm">; 1052 1053// BFM instructions modify the destination register rather than defining it 1054// completely. 1055def BFMwwii : 1056 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1057 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS), 1058 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1059 let DecoderMethod = "DecodeBitfieldInstruction"; 1060 let Constraints = "$src = $Rd"; 1061} 1062 1063def BFMxxii : 1064 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1065 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS), 1066 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1067 let DecoderMethod = "DecodeBitfieldInstruction"; 1068 let Constraints = "$src = $Rd"; 1069} 1070 1071 1072//===------------------------------- 1073// 2. Extend aliases to 64-bit dest 1074//===------------------------------- 1075 1076// Unfortunately the extensions that end up as 64-bits cannot be handled by an 1077// instruction alias: their syntax is (for example) "SXTB x0, w0", which needs 1078// to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is 1079// not capable of such a map as far as I'm aware 1080 1081// Note that these instructions are strictly more specific than the 1082// BFM ones (in ImmR) so they can handle their own decoding. 1083class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, ValueType dty, 1084 string asmop, bits<6> imms, dag pattern> 1085 : A64I_bitfield<sf, opc, sf, 1086 (outs GPRDest:$Rd), (ins GPR32:$Rn), 1087 !strconcat(asmop, "\t$Rd, $Rn"), 1088 [(set dty:$Rd, pattern)], NoItinerary> { 1089 let ImmR = 0b000000; 1090 let ImmS = imms; 1091} 1092 1093// Signed extensions 1094def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtb", 7, 1095 (sext_inreg (anyext i32:$Rn), i8)>; 1096def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxtb", 7, 1097 (sext_inreg i32:$Rn, i8)>; 1098def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxth", 15, 1099 (sext_inreg (anyext i32:$Rn), i16)>; 1100def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxth", 15, 1101 (sext_inreg i32:$Rn, i16)>; 1102def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtw", 31, (sext i32:$Rn)>; 1103 1104// Unsigned extensions 1105def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxtb", 7, 1106 (and i32:$Rn, 255)>; 1107def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxth", 15, 1108 (and i32:$Rn, 65535)>; 1109 1110// The 64-bit unsigned variants are not strictly architectural but recommended 1111// for consistency. 1112let isAsmParserOnly = 1 in { 1113 def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxtb", 7, 1114 (and (anyext i32:$Rn), 255)>; 1115 def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxth", 15, 1116 (and (anyext i32:$Rn), 65535)>; 1117} 1118 1119// Extra patterns for when the source register is actually 64-bits 1120// too. There's no architectural difference here, it's just LLVM 1121// shinanigans. There's no need for equivalent zero-extension patterns 1122// because they'll already be caught by logical (immediate) matching. 1123def : Pat<(sext_inreg i64:$Rn, i8), 1124 (SXTBxw (EXTRACT_SUBREG $Rn, sub_32))>; 1125def : Pat<(sext_inreg i64:$Rn, i16), 1126 (SXTHxw (EXTRACT_SUBREG $Rn, sub_32))>; 1127def : Pat<(sext_inreg i64:$Rn, i32), 1128 (SXTWxw (EXTRACT_SUBREG $Rn, sub_32))>; 1129 1130 1131//===------------------------------- 1132// 3. Aliases for ASR and LSR (the simple shifts) 1133//===------------------------------- 1134 1135// These also handle their own decoding because ImmS being set makes 1136// them take precedence over BFM. 1137multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> { 1138 def wwi : A64I_bitfield<0b0, opc, 0b0, 1139 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR), 1140 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"), 1141 [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))], 1142 NoItinerary> { 1143 let ImmS = 31; 1144 } 1145 1146 def xxi : A64I_bitfield<0b1, opc, 0b1, 1147 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR), 1148 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"), 1149 [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))], 1150 NoItinerary> { 1151 let ImmS = 63; 1152 } 1153 1154} 1155 1156defm ASR : A64I_shift<0b00, "asr", sra>; 1157defm LSR : A64I_shift<0b10, "lsr", srl>; 1158 1159//===------------------------------- 1160// 4. Aliases for LSL 1161//===------------------------------- 1162 1163// Unfortunately LSL and subsequent aliases are much more complicated. We need 1164// to be able to say certain output instruction fields depend in a complex 1165// manner on combinations of input assembly fields). 1166// 1167// MIOperandInfo *might* have been able to do it, but at the cost of 1168// significantly more C++ code. 1169 1170// N.b. contrary to usual practice these operands store the shift rather than 1171// the machine bits in an MCInst. The complexity overhead of consistency 1172// outweighed the benefits in this case (custom asmparser, printer and selection 1173// vs custom encoder). 1174def bitfield32_lsl_imm : Operand<i64>, 1175 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 1176 let ParserMatchClass = uimm5_asmoperand; 1177 let EncoderMethod = "getBitfield32LSLOpValue"; 1178} 1179 1180def bitfield64_lsl_imm : Operand<i64>, 1181 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 1182 let ParserMatchClass = uimm6_asmoperand; 1183 let EncoderMethod = "getBitfield64LSLOpValue"; 1184} 1185 1186class A64I_bitfield_lsl<bit sf, RegisterClass GPR, ValueType ty, 1187 Operand operand> 1188 : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm), 1189 "lsl\t$Rd, $Rn, $FullImm", 1190 [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))], 1191 NoItinerary> { 1192 bits<12> FullImm; 1193 let ImmR = FullImm{5-0}; 1194 let ImmS = FullImm{11-6}; 1195 1196 // No disassembler allowed because it would overlap with BFM which does the 1197 // actual work. 1198 let isAsmParserOnly = 1; 1199} 1200 1201def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, i32, bitfield32_lsl_imm>; 1202def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, i64, bitfield64_lsl_imm>; 1203 1204//===------------------------------- 1205// 5. Aliases for bitfield extract instructions 1206//===------------------------------- 1207 1208def bfx32_width_asmoperand : AsmOperandClass { 1209 let Name = "BFX32Width"; 1210 let PredicateMethod = "isBitfieldWidth<32>"; 1211 let RenderMethod = "addBFXWidthOperands"; 1212 let DiagnosticType = "Width32"; 1213} 1214 1215def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> { 1216 let PrintMethod = "printBFXWidthOperand"; 1217 let ParserMatchClass = bfx32_width_asmoperand; 1218} 1219 1220def bfx64_width_asmoperand : AsmOperandClass { 1221 let Name = "BFX64Width"; 1222 let PredicateMethod = "isBitfieldWidth<64>"; 1223 let RenderMethod = "addBFXWidthOperands"; 1224 let DiagnosticType = "Width64"; 1225} 1226 1227def bfx64_width : Operand<i64> { 1228 let PrintMethod = "printBFXWidthOperand"; 1229 let ParserMatchClass = bfx64_width_asmoperand; 1230} 1231 1232 1233multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> { 1234 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1235 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS), 1236 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1237 [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))], 1238 NoItinerary> { 1239 // As above, no disassembler allowed. 1240 let isAsmParserOnly = 1; 1241 } 1242 1243 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1244 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS), 1245 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1246 [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))], 1247 NoItinerary> { 1248 // As above, no disassembler allowed. 1249 let isAsmParserOnly = 1; 1250 } 1251} 1252 1253defm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>; 1254defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>; 1255 1256// Again, variants based on BFM modify Rd so need it as an input too. 1257def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1258 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS), 1259 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1260 // As above, no disassembler allowed. 1261 let isAsmParserOnly = 1; 1262 let Constraints = "$src = $Rd"; 1263} 1264 1265def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1266 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS), 1267 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1268 // As above, no disassembler allowed. 1269 let isAsmParserOnly = 1; 1270 let Constraints = "$src = $Rd"; 1271} 1272 1273// SBFX instructions can do a 1-instruction sign-extension of boolean values. 1274def : Pat<(sext_inreg i64:$Rn, i1), (SBFXxxii $Rn, 0, 0)>; 1275def : Pat<(sext_inreg i32:$Rn, i1), (SBFXwwii $Rn, 0, 0)>; 1276def : Pat<(i64 (sext_inreg (anyext i32:$Rn), i1)), 1277 (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>; 1278 1279// UBFX makes sense as an implementation of a 64-bit zero-extension too. Could 1280// use either 64-bit or 32-bit variant, but 32-bit might be more efficient. 1281def : Pat<(i64 (zext i32:$Rn)), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31), 1282 sub_32)>; 1283 1284//===------------------------------- 1285// 6. Aliases for bitfield insert instructions 1286//===------------------------------- 1287 1288def bfi32_lsb_asmoperand : AsmOperandClass { 1289 let Name = "BFI32LSB"; 1290 let PredicateMethod = "isUImm<5>"; 1291 let RenderMethod = "addBFILSBOperands<32>"; 1292 let DiagnosticType = "UImm5"; 1293} 1294 1295def bfi32_lsb : Operand<i64>, 1296 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 1297 let PrintMethod = "printBFILSBOperand<32>"; 1298 let ParserMatchClass = bfi32_lsb_asmoperand; 1299} 1300 1301def bfi64_lsb_asmoperand : AsmOperandClass { 1302 let Name = "BFI64LSB"; 1303 let PredicateMethod = "isUImm<6>"; 1304 let RenderMethod = "addBFILSBOperands<64>"; 1305 let DiagnosticType = "UImm6"; 1306} 1307 1308def bfi64_lsb : Operand<i64>, 1309 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 1310 let PrintMethod = "printBFILSBOperand<64>"; 1311 let ParserMatchClass = bfi64_lsb_asmoperand; 1312} 1313 1314// Width verification is performed during conversion so width operand can be 1315// shared between 32/64-bit cases. Still needed for the print method though 1316// because ImmR encodes "width - 1". 1317def bfi32_width_asmoperand : AsmOperandClass { 1318 let Name = "BFI32Width"; 1319 let PredicateMethod = "isBitfieldWidth<32>"; 1320 let RenderMethod = "addBFIWidthOperands"; 1321 let DiagnosticType = "Width32"; 1322} 1323 1324def bfi32_width : Operand<i64>, 1325 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> { 1326 let PrintMethod = "printBFIWidthOperand"; 1327 let ParserMatchClass = bfi32_width_asmoperand; 1328} 1329 1330def bfi64_width_asmoperand : AsmOperandClass { 1331 let Name = "BFI64Width"; 1332 let PredicateMethod = "isBitfieldWidth<64>"; 1333 let RenderMethod = "addBFIWidthOperands"; 1334 let DiagnosticType = "Width64"; 1335} 1336 1337def bfi64_width : Operand<i64>, 1338 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> { 1339 let PrintMethod = "printBFIWidthOperand"; 1340 let ParserMatchClass = bfi64_width_asmoperand; 1341} 1342 1343multiclass A64I_bitfield_insert<bits<2> opc, string asmop> { 1344 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1345 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS), 1346 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1347 [], NoItinerary> { 1348 // As above, no disassembler allowed. 1349 let isAsmParserOnly = 1; 1350 } 1351 1352 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1353 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS), 1354 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1355 [], NoItinerary> { 1356 // As above, no disassembler allowed. 1357 let isAsmParserOnly = 1; 1358 } 1359} 1360 1361defm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">; 1362defm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">; 1363 1364 1365def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1366 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS), 1367 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1368 // As above, no disassembler allowed. 1369 let isAsmParserOnly = 1; 1370 let Constraints = "$src = $Rd"; 1371} 1372 1373def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1374 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS), 1375 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1376 // As above, no disassembler allowed. 1377 let isAsmParserOnly = 1; 1378 let Constraints = "$src = $Rd"; 1379} 1380 1381//===----------------------------------------------------------------------===// 1382// Compare and branch (immediate) 1383//===----------------------------------------------------------------------===// 1384// Contains: CBZ, CBNZ 1385 1386class label_asmoperand<int width, int scale> : AsmOperandClass { 1387 let Name = "Label" # width # "_" # scale; 1388 let PredicateMethod = "isLabel<" # width # "," # scale # ">"; 1389 let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">"; 1390 let DiagnosticType = "Label"; 1391} 1392 1393def label_wid19_scal4_asmoperand : label_asmoperand<19, 4>; 1394 1395// All conditional immediate branches are the same really: 19 signed bits scaled 1396// by the instruction-size (4). 1397def bcc_target : Operand<OtherVT> { 1398 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4. 1399 let ParserMatchClass = label_wid19_scal4_asmoperand; 1400 let PrintMethod = "printLabelOperand<19, 4>"; 1401 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>"; 1402 let OperandType = "OPERAND_PCREL"; 1403} 1404 1405multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> { 1406 let isBranch = 1, isTerminator = 1 in { 1407 def x : A64I_cmpbr<0b1, op, 1408 (outs), 1409 (ins GPR64:$Rt, bcc_target:$Label), 1410 !strconcat(asmop,"\t$Rt, $Label"), 1411 [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)], 1412 NoItinerary>; 1413 1414 def w : A64I_cmpbr<0b0, op, 1415 (outs), 1416 (ins GPR32:$Rt, bcc_target:$Label), 1417 !strconcat(asmop,"\t$Rt, $Label"), 1418 [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)], 1419 NoItinerary>; 1420 } 1421} 1422 1423defm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{ 1424 return Imm == A64CC::EQ; 1425}]> >; 1426defm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{ 1427 return Imm == A64CC::NE; 1428}]> >; 1429 1430//===----------------------------------------------------------------------===// 1431// Conditional branch (immediate) instructions 1432//===----------------------------------------------------------------------===// 1433// Contains: B.cc 1434 1435def cond_code_asmoperand : AsmOperandClass { 1436 let Name = "CondCode"; 1437 let DiagnosticType = "CondCode"; 1438} 1439 1440def cond_code : Operand<i32>, ImmLeaf<i32, [{ 1441 return Imm >= 0 && Imm <= 15; 1442}]> { 1443 let PrintMethod = "printCondCodeOperand"; 1444 let ParserMatchClass = cond_code_asmoperand; 1445} 1446 1447def Bcc : A64I_condbr<0b0, 0b0, (outs), 1448 (ins cond_code:$Cond, bcc_target:$Label), 1449 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)], 1450 NoItinerary> { 1451 let Uses = [NZCV]; 1452 let isBranch = 1; 1453 let isTerminator = 1; 1454} 1455 1456//===----------------------------------------------------------------------===// 1457// Conditional compare (immediate) instructions 1458//===----------------------------------------------------------------------===// 1459// Contains: CCMN, CCMP 1460 1461def uimm4_asmoperand : AsmOperandClass { 1462 let Name = "UImm4"; 1463 let PredicateMethod = "isUImm<4>"; 1464 let RenderMethod = "addImmOperands"; 1465 let DiagnosticType = "UImm4"; 1466} 1467 1468def uimm4 : Operand<i32> { 1469 let ParserMatchClass = uimm4_asmoperand; 1470} 1471 1472def uimm5 : Operand<i32> { 1473 let ParserMatchClass = uimm5_asmoperand; 1474} 1475 1476// The only difference between this operand and the one for instructions like 1477// B.cc is that it's parsed manually. The other get parsed implicitly as part of 1478// the mnemonic handling. 1479def cond_code_op_asmoperand : AsmOperandClass { 1480 let Name = "CondCodeOp"; 1481 let RenderMethod = "addCondCodeOperands"; 1482 let PredicateMethod = "isCondCode"; 1483 let ParserMethod = "ParseCondCodeOperand"; 1484 let DiagnosticType = "CondCode"; 1485} 1486 1487def cond_code_op : Operand<i32> { 1488 let PrintMethod = "printCondCodeOperand"; 1489 let ParserMatchClass = cond_code_op_asmoperand; 1490} 1491 1492class A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop> 1493 : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs), 1494 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond), 1495 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"), 1496 [], NoItinerary> { 1497 let Defs = [NZCV]; 1498} 1499 1500def CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">; 1501def CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">; 1502def CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">; 1503def CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">; 1504 1505//===----------------------------------------------------------------------===// 1506// Conditional compare (register) instructions 1507//===----------------------------------------------------------------------===// 1508// Contains: CCMN, CCMP 1509 1510class A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop> 1511 : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1, 1512 (outs), 1513 (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond), 1514 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"), 1515 [], NoItinerary> { 1516 let Defs = [NZCV]; 1517} 1518 1519def CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">; 1520def CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">; 1521def CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">; 1522def CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">; 1523 1524//===----------------------------------------------------------------------===// 1525// Conditional select instructions 1526//===----------------------------------------------------------------------===// 1527// Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG 1528 1529// Condition code which is encoded as the inversion (semantically rather than 1530// bitwise) in the instruction. 1531def inv_cond_code_op_asmoperand : AsmOperandClass { 1532 let Name = "InvCondCodeOp"; 1533 let RenderMethod = "addInvCondCodeOperands"; 1534 let PredicateMethod = "isCondCode"; 1535 let ParserMethod = "ParseCondCodeOperand"; 1536 let DiagnosticType = "CondCode"; 1537} 1538 1539def inv_cond_code_op : Operand<i32> { 1540 let ParserMatchClass = inv_cond_code_op_asmoperand; 1541} 1542 1543// Having a separate operand for the selectable use-case is debatable, but gives 1544// consistency with cond_code. 1545def inv_cond_XFORM : SDNodeXForm<imm, [{ 1546 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue()); 1547 return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32); 1548}]>; 1549 1550def inv_cond_code 1551 : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>; 1552 1553 1554multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop, 1555 SDPatternOperator select> { 1556 let Uses = [NZCV] in { 1557 def wwwc : A64I_condsel<0b0, op, 0b0, op2, 1558 (outs GPR32:$Rd), 1559 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond), 1560 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"), 1561 [(set i32:$Rd, (select i32:$Rn, i32:$Rm))], 1562 NoItinerary>; 1563 1564 1565 def xxxc : A64I_condsel<0b1, op, 0b0, op2, 1566 (outs GPR64:$Rd), 1567 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond), 1568 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"), 1569 [(set i64:$Rd, (select i64:$Rn, i64:$Rm))], 1570 NoItinerary>; 1571 } 1572} 1573 1574def simple_select 1575 : PatFrag<(ops node:$lhs, node:$rhs), 1576 (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>; 1577 1578class complex_select<SDPatternOperator opnode> 1579 : PatFrag<(ops node:$lhs, node:$rhs), 1580 (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>; 1581 1582 1583defm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>; 1584defm CSINC : A64I_condselSizes<0b0, 0b01, "csinc", 1585 complex_select<PatFrag<(ops node:$val), 1586 (add node:$val, 1)>>>; 1587defm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>; 1588defm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>; 1589 1590// Now the instruction aliases, which fit nicely into LLVM's model: 1591 1592def : InstAlias<"cset $Rd, $Cond", 1593 (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>; 1594def : InstAlias<"cset $Rd, $Cond", 1595 (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>; 1596def : InstAlias<"csetm $Rd, $Cond", 1597 (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>; 1598def : InstAlias<"csetm $Rd, $Cond", 1599 (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>; 1600def : InstAlias<"cinc $Rd, $Rn, $Cond", 1601 (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1602def : InstAlias<"cinc $Rd, $Rn, $Cond", 1603 (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1604def : InstAlias<"cinv $Rd, $Rn, $Cond", 1605 (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1606def : InstAlias<"cinv $Rd, $Rn, $Cond", 1607 (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1608def : InstAlias<"cneg $Rd, $Rn, $Cond", 1609 (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1610def : InstAlias<"cneg $Rd, $Rn, $Cond", 1611 (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1612 1613// Finally some helper patterns. 1614 1615// For CSET (a.k.a. zero-extension of icmp) 1616def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond), 1617 (CSINCwwwc WZR, WZR, cond_code:$Cond)>; 1618def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond), 1619 (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>; 1620 1621def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond), 1622 (CSINCxxxc XZR, XZR, cond_code:$Cond)>; 1623def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond), 1624 (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>; 1625 1626// For CSETM (a.k.a. sign-extension of icmp) 1627def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond), 1628 (CSINVwwwc WZR, WZR, cond_code:$Cond)>; 1629def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond), 1630 (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>; 1631 1632def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond), 1633 (CSINVxxxc XZR, XZR, cond_code:$Cond)>; 1634def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond), 1635 (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>; 1636 1637// CINC, CINV and CNEG get dealt with automatically, which leaves the issue of 1638// commutativity. The instructions are to complex for isCommutable to be used, 1639// so we have to create the patterns manually: 1640 1641// No commutable pattern for CSEL since the commuted version is isomorphic. 1642 1643// CSINC 1644def :Pat<(A64select_cc NZCV, (add i32:$Rm, 1), i32:$Rn, inv_cond_code:$Cond), 1645 (CSINCwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1646def :Pat<(A64select_cc NZCV, (add i64:$Rm, 1), i64:$Rn, inv_cond_code:$Cond), 1647 (CSINCxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1648 1649// CSINV 1650def :Pat<(A64select_cc NZCV, (not i32:$Rm), i32:$Rn, inv_cond_code:$Cond), 1651 (CSINVwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1652def :Pat<(A64select_cc NZCV, (not i64:$Rm), i64:$Rn, inv_cond_code:$Cond), 1653 (CSINVxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1654 1655// CSNEG 1656def :Pat<(A64select_cc NZCV, (ineg i32:$Rm), i32:$Rn, inv_cond_code:$Cond), 1657 (CSNEGwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1658def :Pat<(A64select_cc NZCV, (ineg i64:$Rm), i64:$Rn, inv_cond_code:$Cond), 1659 (CSNEGxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1660 1661//===----------------------------------------------------------------------===// 1662// Data Processing (1 source) instructions 1663//===----------------------------------------------------------------------===// 1664// Contains: RBIT, REV16, REV, REV32, CLZ, CLS. 1665 1666// We define an unary operator which always fails. We will use this to 1667// define unary operators that cannot be matched. 1668 1669class A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop, 1670 list<dag> patterns, RegisterClass GPRrc, 1671 InstrItinClass itin>: 1672 A64I_dp_1src<sf, 1673 0, 1674 0b00000, 1675 opcode, 1676 !strconcat(asmop, "\t$Rd, $Rn"), 1677 (outs GPRrc:$Rd), 1678 (ins GPRrc:$Rn), 1679 patterns, 1680 itin>; 1681 1682multiclass A64I_dp_1src <bits<6> opcode, string asmop> { 1683 let hasSideEffects = 0 in { 1684 def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>; 1685 def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>; 1686 } 1687} 1688 1689defm RBIT : A64I_dp_1src<0b000000, "rbit">; 1690defm CLS : A64I_dp_1src<0b000101, "cls">; 1691defm CLZ : A64I_dp_1src<0b000100, "clz">; 1692 1693def : Pat<(ctlz i32:$Rn), (CLZww $Rn)>; 1694def : Pat<(ctlz i64:$Rn), (CLZxx $Rn)>; 1695def : Pat<(ctlz_zero_undef i32:$Rn), (CLZww $Rn)>; 1696def : Pat<(ctlz_zero_undef i64:$Rn), (CLZxx $Rn)>; 1697 1698def : Pat<(cttz i32:$Rn), (CLZww (RBITww $Rn))>; 1699def : Pat<(cttz i64:$Rn), (CLZxx (RBITxx $Rn))>; 1700def : Pat<(cttz_zero_undef i32:$Rn), (CLZww (RBITww $Rn))>; 1701def : Pat<(cttz_zero_undef i64:$Rn), (CLZxx (RBITxx $Rn))>; 1702 1703 1704def REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev", 1705 [(set i32:$Rd, (bswap i32:$Rn))], 1706 GPR32, NoItinerary>; 1707def REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev", 1708 [(set i64:$Rd, (bswap i64:$Rn))], 1709 GPR64, NoItinerary>; 1710def REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32", 1711 [(set i64:$Rd, (bswap (rotr i64:$Rn, (i64 32))))], 1712 GPR64, NoItinerary>; 1713def REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16", 1714 [(set i32:$Rd, (bswap (rotr i32:$Rn, (i64 16))))], 1715 GPR32, 1716 NoItinerary>; 1717def REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>; 1718 1719//===----------------------------------------------------------------------===// 1720// Data Processing (2 sources) instructions 1721//===----------------------------------------------------------------------===// 1722// Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL, 1723// LSR, ASR, ROR 1724 1725 1726class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns, 1727 RegisterClass GPRsp, 1728 InstrItinClass itin>: 1729 A64I_dp_2src<sf, 1730 opcode, 1731 0, 1732 !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 1733 (outs GPRsp:$Rd), 1734 (ins GPRsp:$Rn, GPRsp:$Rm), 1735 patterns, 1736 itin>; 1737 1738multiclass dp_2src_crc<bit c, string asmop> { 1739 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0}, 1740 !strconcat(asmop, "b"), [], GPR32, NoItinerary>; 1741 def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1}, 1742 !strconcat(asmop, "h"), [], GPR32, NoItinerary>; 1743 def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0}, 1744 !strconcat(asmop, "w"), [], GPR32, NoItinerary>; 1745 def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0, 1746 !strconcat(asmop, "x\t$Rd, $Rn, $Rm"), 1747 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [], 1748 NoItinerary>; 1749} 1750 1751multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> { 1752 def www : dp_2src_impl<0b0, 1753 opcode, 1754 asmop, 1755 [(set i32:$Rd, 1756 (op i32:$Rn, (i64 (zext i32:$Rm))))], 1757 GPR32, 1758 NoItinerary>; 1759 def xxx : dp_2src_impl<0b1, 1760 opcode, 1761 asmop, 1762 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))], 1763 GPR64, 1764 NoItinerary>; 1765} 1766 1767 1768multiclass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> { 1769 def www : dp_2src_impl<0b0, 1770 opcode, 1771 asmop, 1772 [(set i32:$Rd, (op i32:$Rn, i32:$Rm))], 1773 GPR32, 1774 NoItinerary>; 1775 def xxx : dp_2src_impl<0b1, 1776 opcode, 1777 asmop, 1778 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))], 1779 GPR64, 1780 NoItinerary>; 1781} 1782 1783// Here we define the data processing 2 source instructions. 1784defm CRC32 : dp_2src_crc<0b0, "crc32">; 1785defm CRC32C : dp_2src_crc<0b1, "crc32c">; 1786 1787defm UDIV : dp_2src<0b000010, "udiv", udiv>; 1788defm SDIV : dp_2src<0b000011, "sdiv", sdiv>; 1789 1790defm LSLV : dp_2src_zext<0b001000, "lsl", shl>; 1791defm LSRV : dp_2src_zext<0b001001, "lsr", srl>; 1792defm ASRV : dp_2src_zext<0b001010, "asr", sra>; 1793defm RORV : dp_2src_zext<0b001011, "ror", rotr>; 1794 1795// Extra patterns for an incoming 64-bit value for a 32-bit 1796// operation. Since the LLVM operations are undefined (as in C) if the 1797// RHS is out of range, it's perfectly permissible to discard the high 1798// bits of the GPR64. 1799def : Pat<(shl i32:$Rn, i64:$Rm), 1800 (LSLVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1801def : Pat<(srl i32:$Rn, i64:$Rm), 1802 (LSRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1803def : Pat<(sra i32:$Rn, i64:$Rm), 1804 (ASRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1805def : Pat<(rotr i32:$Rn, i64:$Rm), 1806 (RORVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1807 1808// Here we define the aliases for the data processing 2 source instructions. 1809def LSL_mnemonic : MnemonicAlias<"lslv", "lsl">; 1810def LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">; 1811def ASR_menmonic : MnemonicAlias<"asrv", "asr">; 1812def ROR_menmonic : MnemonicAlias<"rorv", "ror">; 1813 1814//===----------------------------------------------------------------------===// 1815// Data Processing (3 sources) instructions 1816//===----------------------------------------------------------------------===// 1817// Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH 1818// + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL 1819 1820class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg, 1821 ValueType AccTy, RegisterClass SrcReg, 1822 string asmop, dag pattern> 1823 : A64I_dp3<sf, opcode, 1824 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra), 1825 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"), 1826 [(set AccTy:$Rd, pattern)], NoItinerary> { 1827 RegisterClass AccGPR = AccReg; 1828 RegisterClass SrcGPR = SrcReg; 1829} 1830 1831def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, i32, GPR32, "madd", 1832 (add i32:$Ra, (mul i32:$Rn, i32:$Rm))>; 1833def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, i64, GPR64, "madd", 1834 (add i64:$Ra, (mul i64:$Rn, i64:$Rm))>; 1835 1836def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, i32, GPR32, "msub", 1837 (sub i32:$Ra, (mul i32:$Rn, i32:$Rm))>; 1838def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, i64, GPR64, "msub", 1839 (sub i64:$Ra, (mul i64:$Rn, i64:$Rm))>; 1840 1841def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, i64, GPR32, "smaddl", 1842 (add i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1843def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, i64, GPR32, "smsubl", 1844 (sub i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1845 1846def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, i64, GPR32, "umaddl", 1847 (add i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1848def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, i64, GPR32, "umsubl", 1849 (sub i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1850 1851let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in { 1852 def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd), 1853 (ins GPR64:$Rn, GPR64:$Rm), 1854 "umulh\t$Rd, $Rn, $Rm", 1855 [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))], 1856 NoItinerary>; 1857 1858 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd), 1859 (ins GPR64:$Rn, GPR64:$Rm), 1860 "smulh\t$Rd, $Rn, $Rm", 1861 [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))], 1862 NoItinerary>; 1863} 1864 1865multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST, 1866 Register ZR, dag pattern> { 1867 def : InstAlias<asmop # " $Rd, $Rn, $Rm", 1868 (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>; 1869 1870 def : Pat<pattern, (INST $Rn, $Rm, ZR)>; 1871} 1872 1873defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul i32:$Rn, i32:$Rm)>; 1874defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul i64:$Rn, i64:$Rm)>; 1875 1876defm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR, 1877 (sub 0, (mul i32:$Rn, i32:$Rm))>; 1878defm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR, 1879 (sub 0, (mul i64:$Rn, i64:$Rm))>; 1880 1881defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR, 1882 (mul (i64 (sext i32:$Rn)), (sext i32:$Rm))>; 1883defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR, 1884 (sub 0, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1885 1886defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR, 1887 (mul (i64 (zext i32:$Rn)), (zext i32:$Rm))>; 1888defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR, 1889 (sub 0, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1890 1891 1892//===----------------------------------------------------------------------===// 1893// Exception generation 1894//===----------------------------------------------------------------------===// 1895// Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3 1896 1897def uimm16_asmoperand : AsmOperandClass { 1898 let Name = "UImm16"; 1899 let PredicateMethod = "isUImm<16>"; 1900 let RenderMethod = "addImmOperands"; 1901 let DiagnosticType = "UImm16"; 1902} 1903 1904def uimm16 : Operand<i32> { 1905 let ParserMatchClass = uimm16_asmoperand; 1906} 1907 1908class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop> 1909 : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16), 1910 !strconcat(asmop, "\t$UImm16"), [], NoItinerary> { 1911 let isBranch = 1; 1912 let isTerminator = 1; 1913} 1914 1915def SVCi : A64I_exceptImpl<0b000, 0b01, "svc">; 1916def HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">; 1917def SMCi : A64I_exceptImpl<0b000, 0b11, "smc">; 1918def BRKi : A64I_exceptImpl<0b001, 0b00, "brk">; 1919def HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">; 1920 1921def DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">; 1922def DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">; 1923def DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">; 1924 1925// The immediate is optional for the DCPS instructions, defaulting to 0. 1926def : InstAlias<"dcps1", (DCPS1i 0)>; 1927def : InstAlias<"dcps2", (DCPS2i 0)>; 1928def : InstAlias<"dcps3", (DCPS3i 0)>; 1929 1930//===----------------------------------------------------------------------===// 1931// Extract (immediate) 1932//===----------------------------------------------------------------------===// 1933// Contains: EXTR + alias ROR 1934 1935def EXTRwwwi : A64I_extract<0b0, 0b000, 0b0, 1936 (outs GPR32:$Rd), 1937 (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB), 1938 "extr\t$Rd, $Rn, $Rm, $LSB", 1939 [(set i32:$Rd, 1940 (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))], 1941 NoItinerary>; 1942def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1, 1943 (outs GPR64:$Rd), 1944 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB), 1945 "extr\t$Rd, $Rn, $Rm, $LSB", 1946 [(set i64:$Rd, 1947 (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))], 1948 NoItinerary>; 1949 1950def : InstAlias<"ror $Rd, $Rs, $LSB", 1951 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>; 1952def : InstAlias<"ror $Rd, $Rs, $LSB", 1953 (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>; 1954 1955def : Pat<(rotr i32:$Rn, bitfield32_imm:$LSB), 1956 (EXTRwwwi $Rn, $Rn, bitfield32_imm:$LSB)>; 1957def : Pat<(rotr i64:$Rn, bitfield64_imm:$LSB), 1958 (EXTRxxxi $Rn, $Rn, bitfield64_imm:$LSB)>; 1959 1960//===----------------------------------------------------------------------===// 1961// Floating-point compare instructions 1962//===----------------------------------------------------------------------===// 1963// Contains: FCMP, FCMPE 1964 1965def fpzero_asmoperand : AsmOperandClass { 1966 let Name = "FPZero"; 1967 let ParserMethod = "ParseFPImmOperand"; 1968 let DiagnosticType = "FPZero"; 1969} 1970 1971def fpz32 : Operand<f32>, 1972 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> { 1973 let ParserMatchClass = fpzero_asmoperand; 1974 let PrintMethod = "printFPZeroOperand"; 1975 let DecoderMethod = "DecodeFPZeroOperand"; 1976} 1977 1978def fpz64 : Operand<f64>, 1979 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> { 1980 let ParserMatchClass = fpzero_asmoperand; 1981 let PrintMethod = "printFPZeroOperand"; 1982 let DecoderMethod = "DecodeFPZeroOperand"; 1983} 1984 1985def fpz64movi : Operand<i64>, 1986 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> { 1987 let ParserMatchClass = fpzero_asmoperand; 1988 let PrintMethod = "printFPZeroOperand"; 1989 let DecoderMethod = "DecodeFPZeroOperand"; 1990} 1991 1992multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> { 1993 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0}, 1994 (outs), ins, "fcmp\t$Rn, $Rm", [pattern], 1995 NoItinerary> { 1996 let Defs = [NZCV]; 1997 } 1998 1999 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0}, 2000 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> { 2001 let Defs = [NZCV]; 2002 } 2003} 2004 2005defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm), 2006 (set NZCV, (A64cmp f32:$Rn, f32:$Rm))>; 2007defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm), 2008 (set NZCV, (A64cmp f64:$Rn, f64:$Rm))>; 2009 2010// What would be Rm should be written as 0; note that even though it's called 2011// "$Rm" here to fit in with the InstrFormats, it's actually an immediate. 2012defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm), 2013 (set NZCV, (A64cmp f32:$Rn, fpz32:$Rm))>; 2014 2015defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm), 2016 (set NZCV, (A64cmp f64:$Rn, fpz64:$Rm))>; 2017 2018 2019//===----------------------------------------------------------------------===// 2020// Floating-point conditional compare instructions 2021//===----------------------------------------------------------------------===// 2022// Contains: FCCMP, FCCMPE 2023 2024class A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop> 2025 : A64I_fpccmp<0b0, 0b0, type, op, 2026 (outs), 2027 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond), 2028 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"), 2029 [], NoItinerary> { 2030 let Defs = [NZCV]; 2031} 2032 2033def FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">; 2034def FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">; 2035def FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">; 2036def FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">; 2037 2038//===----------------------------------------------------------------------===// 2039// Floating-point conditional select instructions 2040//===----------------------------------------------------------------------===// 2041// Contains: FCSEL 2042 2043let Uses = [NZCV] in { 2044 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd), 2045 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond), 2046 "fcsel\t$Rd, $Rn, $Rm, $Cond", 2047 [(set f32:$Rd, 2048 (simple_select f32:$Rn, f32:$Rm))], 2049 NoItinerary>; 2050 2051 2052 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd), 2053 (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond), 2054 "fcsel\t$Rd, $Rn, $Rm, $Cond", 2055 [(set f64:$Rd, 2056 (simple_select f64:$Rn, f64:$Rm))], 2057 NoItinerary>; 2058} 2059 2060//===----------------------------------------------------------------------===// 2061// Floating-point data-processing (1 source) 2062//===----------------------------------------------------------------------===// 2063// Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI]. 2064 2065def FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val), 2066 [{ (void)N; return false; }]>; 2067 2068// First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d" 2069// syntax. Default to no pattern because most are odd enough not to have one. 2070multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr, 2071 SDPatternOperator opnode = FPNoUnop> { 2072 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn), 2073 !strconcat(asmstr, "\t$Rd, $Rn"), 2074 [(set f32:$Rd, (opnode f32:$Rn))], 2075 NoItinerary>; 2076 2077 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn), 2078 !strconcat(asmstr, "\t$Rd, $Rn"), 2079 [(set f64:$Rd, (opnode f64:$Rn))], 2080 NoItinerary>; 2081} 2082 2083defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">; 2084defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>; 2085defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>; 2086defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>; 2087 2088defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">; 2089defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>; 2090defm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>; 2091defm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>; 2092defm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">; 2093defm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>; 2094defm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>; 2095 2096// The FCVT instrucitons have different source and destination register-types, 2097// but the fields are uniform everywhere a D-register (say) crops up. Package 2098// this information in a Record. 2099class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> { 2100 RegisterClass Class = rc; 2101 ValueType VT = vt; 2102 bit t1 = fld{1}; 2103 bit t0 = fld{0}; 2104} 2105 2106def FCVT16 : FCVTRegType<FPR16, 0b11, f16>; 2107def FCVT32 : FCVTRegType<FPR32, 0b00, f32>; 2108def FCVT64 : FCVTRegType<FPR64, 0b01, f64>; 2109 2110class A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode> 2111 : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0}, 2112 {0,0,0,1, DestReg.t1, DestReg.t0}, 2113 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn), 2114 "fcvt\t$Rd, $Rn", 2115 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>; 2116 2117def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>; 2118def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>; 2119def FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>; 2120def FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>; 2121def FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>; 2122def FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>; 2123 2124 2125//===----------------------------------------------------------------------===// 2126// Floating-point data-processing (2 sources) instructions 2127//===----------------------------------------------------------------------===// 2128// Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL 2129 2130def FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs), 2131 [{ (void)N; return false; }]>; 2132 2133multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr, 2134 SDPatternOperator opnode> { 2135 def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode, 2136 (outs FPR32:$Rd), 2137 (ins FPR32:$Rn, FPR32:$Rm), 2138 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"), 2139 [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))], 2140 NoItinerary>; 2141 2142 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode, 2143 (outs FPR64:$Rd), 2144 (ins FPR64:$Rn, FPR64:$Rm), 2145 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"), 2146 [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))], 2147 NoItinerary>; 2148} 2149 2150let isCommutable = 1 in { 2151 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>; 2152 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>; 2153 2154 // No patterns for these. 2155 defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>; 2156 defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>; 2157 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>; 2158 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>; 2159 2160 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul", 2161 PatFrag<(ops node:$lhs, node:$rhs), 2162 (fneg (fmul node:$lhs, node:$rhs))> >; 2163} 2164 2165defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>; 2166defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>; 2167 2168//===----------------------------------------------------------------------===// 2169// Floating-point data-processing (3 sources) instructions 2170//===----------------------------------------------------------------------===// 2171// Contains: FMADD, FMSUB, FNMADD, FNMSUB 2172 2173def fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2174 (fma (fneg node:$Rn), node:$Rm, node:$Ra)>; 2175def fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2176 (fma node:$Rn, node:$Rm, (fneg node:$Ra))>; 2177def fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2178 (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>; 2179 2180class A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT, 2181 bits<2> type, bit o1, bit o0, SDPatternOperator fmakind> 2182 : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd), 2183 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra), 2184 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"), 2185 [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))], 2186 NoItinerary>; 2187 2188def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>; 2189def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>; 2190def FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>; 2191def FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>; 2192 2193def FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>; 2194def FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>; 2195def FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>; 2196def FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>; 2197 2198// Extra patterns for when we're allowed to optimise separate multiplication and 2199// addition. 2200let Predicates = [HasFPARMv8, UseFusedMAC] in { 2201def : Pat<(f32 (fadd FPR32:$Ra, (f32 (fmul FPR32:$Rn, FPR32:$Rm)))), 2202 (FMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 2203def : Pat<(f32 (fsub FPR32:$Ra, (f32 (fmul FPR32:$Rn, FPR32:$Rm)))), 2204 (FMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 2205def : Pat<(f32 (fsub (f32 (fmul FPR32:$Rn, FPR32:$Rm)), FPR32:$Ra)), 2206 (FNMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 2207def : Pat<(f32 (fsub (f32 (fneg FPR32:$Ra)), (f32 (fmul FPR32:$Rn, FPR32:$Rm)))), 2208 (FNMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 2209 2210def : Pat<(f64 (fadd FPR64:$Ra, (f64 (fmul FPR64:$Rn, FPR64:$Rm)))), 2211 (FMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 2212def : Pat<(f64 (fsub FPR64:$Ra, (f64 (fmul FPR64:$Rn, FPR64:$Rm)))), 2213 (FMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 2214def : Pat<(f64 (fsub (f64 (fmul FPR64:$Rn, FPR64:$Rm)), FPR64:$Ra)), 2215 (FNMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 2216def : Pat<(f64 (fsub (f64 (fneg FPR64:$Ra)), (f64 (fmul FPR64:$Rn, FPR64:$Rm)))), 2217 (FNMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 2218} 2219 2220 2221//===----------------------------------------------------------------------===// 2222// Floating-point <-> fixed-point conversion instructions 2223//===----------------------------------------------------------------------===// 2224// Contains: FCVTZS, FCVTZU, SCVTF, UCVTF 2225 2226// #1-#32 allowed, encoded as "64 - <specified imm> 2227def fixedpos_asmoperand_i32 : AsmOperandClass { 2228 let Name = "CVTFixedPos32"; 2229 let RenderMethod = "addCVTFixedPosOperands"; 2230 let PredicateMethod = "isCVTFixedPos<32>"; 2231 let DiagnosticType = "CVTFixedPos32"; 2232} 2233 2234// Also encoded as "64 - <specified imm>" but #1-#64 allowed. 2235def fixedpos_asmoperand_i64 : AsmOperandClass { 2236 let Name = "CVTFixedPos64"; 2237 let RenderMethod = "addCVTFixedPosOperands"; 2238 let PredicateMethod = "isCVTFixedPos<64>"; 2239 let DiagnosticType = "CVTFixedPos64"; 2240} 2241 2242// We need the cartesian product of f32/f64 i32/i64 operands for 2243// conversions: 2244// + Selection needs to use operands of correct floating type 2245// + Assembly parsing and decoding depend on integer width 2246class cvtfix_i32_op<ValueType FloatVT> 2247 : Operand<FloatVT>, 2248 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> { 2249 let ParserMatchClass = fixedpos_asmoperand_i32; 2250 let DecoderMethod = "DecodeCVT32FixedPosOperand"; 2251 let PrintMethod = "printCVTFixedPosOperand"; 2252} 2253 2254class cvtfix_i64_op<ValueType FloatVT> 2255 : Operand<FloatVT>, 2256 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> { 2257 let ParserMatchClass = fixedpos_asmoperand_i64; 2258 let PrintMethod = "printCVTFixedPosOperand"; 2259} 2260 2261// Because of the proliferation of weird operands, it's not really 2262// worth going for a multiclass here. Oh well. 2263 2264class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode, 2265 RegisterClass GPR, RegisterClass FPR, 2266 ValueType DstTy, ValueType SrcTy, 2267 Operand scale_op, string asmop, SDNode cvtop> 2268 : A64I_fpfixed<sf, 0b0, type, 0b11, opcode, 2269 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale), 2270 !strconcat(asmop, "\t$Rd, $Rn, $Scale"), 2271 [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))], 2272 NoItinerary>; 2273 2274def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32, 2275 cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>; 2276def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32, i64, f32, 2277 cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>; 2278def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32, i32, f32, 2279 cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>; 2280def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32, i64, f32, 2281 cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>; 2282 2283def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64, i32, f64, 2284 cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>; 2285def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64, i64, f64, 2286 cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>; 2287def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64, i32, f64, 2288 cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>; 2289def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64, i64, f64, 2290 cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>; 2291 2292 2293class A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode, 2294 RegisterClass FPR, RegisterClass GPR, 2295 ValueType DstTy, ValueType SrcTy, 2296 Operand scale_op, string asmop, SDNode cvtop> 2297 : A64I_fpfixed<sf, 0b0, type, 0b00, opcode, 2298 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale), 2299 !strconcat(asmop, "\t$Rd, $Rn, $Scale"), 2300 [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))], 2301 NoItinerary>; 2302 2303def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32, 2304 cvtfix_i32_op<f32>, "scvtf", sint_to_fp>; 2305def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64, f32, i64, 2306 cvtfix_i64_op<f32>, "scvtf", sint_to_fp>; 2307def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32, f32, i32, 2308 cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>; 2309def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64, f32, i64, 2310 cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>; 2311def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32, f64, i32, 2312 cvtfix_i32_op<f64>, "scvtf", sint_to_fp>; 2313def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64, f64, i64, 2314 cvtfix_i64_op<f64>, "scvtf", sint_to_fp>; 2315def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32, f64, i32, 2316 cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>; 2317def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64, f64, i64, 2318 cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>; 2319 2320//===----------------------------------------------------------------------===// 2321// Floating-point <-> integer conversion instructions 2322//===----------------------------------------------------------------------===// 2323// Contains: FCVTZS, FCVTZU, SCVTF, UCVTF 2324 2325class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode, 2326 RegisterClass DestPR, RegisterClass SrcPR, string asmop> 2327 : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn), 2328 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>; 2329 2330multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> { 2331 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0}, 2332 GPR32, FPR32, asmop # "s">; 2333 def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0}, 2334 GPR64, FPR32, asmop # "s">; 2335 def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1}, 2336 GPR32, FPR32, asmop # "u">; 2337 def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1}, 2338 GPR64, FPR32, asmop # "u">; 2339 2340 def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0}, 2341 GPR32, FPR64, asmop # "s">; 2342 def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0}, 2343 GPR64, FPR64, asmop # "s">; 2344 def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1}, 2345 GPR32, FPR64, asmop # "u">; 2346 def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1}, 2347 GPR64, FPR64, asmop # "u">; 2348} 2349 2350defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">; 2351defm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">; 2352defm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">; 2353defm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">; 2354defm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">; 2355 2356let Predicates = [HasFPARMv8] in { 2357def : Pat<(i32 (fp_to_sint f32:$Rn)), (FCVTZSws $Rn)>; 2358def : Pat<(i64 (fp_to_sint f32:$Rn)), (FCVTZSxs $Rn)>; 2359def : Pat<(i32 (fp_to_uint f32:$Rn)), (FCVTZUws $Rn)>; 2360def : Pat<(i64 (fp_to_uint f32:$Rn)), (FCVTZUxs $Rn)>; 2361def : Pat<(i32 (fp_to_sint f64:$Rn)), (FCVTZSwd $Rn)>; 2362def : Pat<(i64 (fp_to_sint f64:$Rn)), (FCVTZSxd $Rn)>; 2363def : Pat<(i32 (fp_to_uint f64:$Rn)), (FCVTZUwd $Rn)>; 2364def : Pat<(i64 (fp_to_uint f64:$Rn)), (FCVTZUxd $Rn)>; 2365} 2366 2367multiclass A64I_inttofp<bit o0, string asmop> { 2368 def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>; 2369 def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>; 2370 def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>; 2371 def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>; 2372} 2373 2374defm S : A64I_inttofp<0b0, "scvtf">; 2375defm U : A64I_inttofp<0b1, "ucvtf">; 2376 2377let Predicates = [HasFPARMv8] in { 2378def : Pat<(f32 (sint_to_fp i32:$Rn)), (SCVTFsw $Rn)>; 2379def : Pat<(f32 (sint_to_fp i64:$Rn)), (SCVTFsx $Rn)>; 2380def : Pat<(f64 (sint_to_fp i32:$Rn)), (SCVTFdw $Rn)>; 2381def : Pat<(f64 (sint_to_fp i64:$Rn)), (SCVTFdx $Rn)>; 2382def : Pat<(f32 (uint_to_fp i32:$Rn)), (UCVTFsw $Rn)>; 2383def : Pat<(f32 (uint_to_fp i64:$Rn)), (UCVTFsx $Rn)>; 2384def : Pat<(f64 (uint_to_fp i32:$Rn)), (UCVTFdw $Rn)>; 2385def : Pat<(f64 (uint_to_fp i64:$Rn)), (UCVTFdx $Rn)>; 2386} 2387 2388def FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">; 2389def FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">; 2390def FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">; 2391def FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">; 2392 2393let Predicates = [HasFPARMv8] in { 2394def : Pat<(i32 (bitconvert f32:$Rn)), (FMOVws $Rn)>; 2395def : Pat<(f32 (bitconvert i32:$Rn)), (FMOVsw $Rn)>; 2396def : Pat<(i64 (bitconvert f64:$Rn)), (FMOVxd $Rn)>; 2397def : Pat<(f64 (bitconvert i64:$Rn)), (FMOVdx $Rn)>; 2398} 2399 2400def lane1_asmoperand : AsmOperandClass { 2401 let Name = "Lane1"; 2402 let RenderMethod = "addImmOperands"; 2403 let DiagnosticType = "Lane1"; 2404} 2405 2406def lane1 : Operand<i32> { 2407 let ParserMatchClass = lane1_asmoperand; 2408 let PrintMethod = "printBareImmOperand"; 2409} 2410 2411let DecoderMethod = "DecodeFMOVLaneInstruction" in { 2412 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110, 2413 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane), 2414 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>; 2415 2416 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111, 2417 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane), 2418 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>; 2419} 2420 2421let Predicates = [HasFPARMv8] in { 2422def : InstAlias<"fmov $Rd, $Rn.2d[$Lane]", 2423 (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>; 2424 2425def : InstAlias<"fmov $Rd.2d[$Lane], $Rn", 2426 (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>; 2427} 2428 2429//===----------------------------------------------------------------------===// 2430// Floating-point immediate instructions 2431//===----------------------------------------------------------------------===// 2432// Contains: FMOV 2433 2434def fpimm_asmoperand : AsmOperandClass { 2435 let Name = "FMOVImm"; 2436 let ParserMethod = "ParseFPImmOperand"; 2437 let DiagnosticType = "FPImm"; 2438} 2439 2440// The MCOperand for these instructions are the encoded 8-bit values. 2441def SDXF_fpimm : SDNodeXForm<fpimm, [{ 2442 uint32_t Imm8; 2443 A64Imms::isFPImm(N->getValueAPF(), Imm8); 2444 return CurDAG->getTargetConstant(Imm8, MVT::i32); 2445}]>; 2446 2447class fmov_operand<ValueType FT> 2448 : Operand<i32>, 2449 PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }], 2450 SDXF_fpimm> { 2451 let PrintMethod = "printFPImmOperand"; 2452 let ParserMatchClass = fpimm_asmoperand; 2453} 2454 2455def fmov32_operand : fmov_operand<f32>; 2456def fmov64_operand : fmov_operand<f64>; 2457 2458class A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT, 2459 Operand fmov_operand> 2460 : A64I_fpimm<0b0, 0b0, type, 0b00000, 2461 (outs Reg:$Rd), 2462 (ins fmov_operand:$Imm8), 2463 "fmov\t$Rd, $Imm8", 2464 [(set VT:$Rd, fmov_operand:$Imm8)], 2465 NoItinerary>; 2466 2467def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>; 2468def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>; 2469 2470//===----------------------------------------------------------------------===// 2471// Load-register (literal) instructions 2472//===----------------------------------------------------------------------===// 2473// Contains: LDR, LDRSW, PRFM 2474 2475def ldrlit_label_asmoperand : AsmOperandClass { 2476 let Name = "LoadLitLabel"; 2477 let RenderMethod = "addLabelOperands<19, 4>"; 2478 let DiagnosticType = "Label"; 2479} 2480 2481def ldrlit_label : Operand<i64> { 2482 let EncoderMethod = "getLoadLitLabelOpValue"; 2483 2484 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4. 2485 let PrintMethod = "printLabelOperand<19, 4>"; 2486 let ParserMatchClass = ldrlit_label_asmoperand; 2487 let OperandType = "OPERAND_PCREL"; 2488} 2489 2490// Various instructions take an immediate value (which can always be used), 2491// where some numbers have a symbolic name to make things easier. These operands 2492// and the associated functions abstract away the differences. 2493multiclass namedimm<string prefix, string mapper> { 2494 def _asmoperand : AsmOperandClass { 2495 let Name = "NamedImm" # prefix; 2496 let PredicateMethod = "isUImm"; 2497 let RenderMethod = "addImmOperands"; 2498 let ParserMethod = "ParseNamedImmOperand<" # mapper # ">"; 2499 let DiagnosticType = "NamedImm_" # prefix; 2500 } 2501 2502 def _op : Operand<i32> { 2503 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 2504 let PrintMethod = "printNamedImmOperand<" # mapper # ">"; 2505 let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">"; 2506 } 2507} 2508 2509defm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">; 2510 2511class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg, 2512 list<dag> patterns = []> 2513 : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19), 2514 "ldr\t$Rt, $Imm19", patterns, NoItinerary>; 2515 2516let mayLoad = 1 in { 2517 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>; 2518 def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>; 2519} 2520 2521let Predicates = [HasFPARMv8] in { 2522def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>; 2523def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>; 2524} 2525 2526let mayLoad = 1 in { 2527 let Predicates = [HasFPARMv8] in { 2528 def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>; 2529 } 2530 2531 2532 def LDRSWx_lit : A64I_LDRlit<0b10, 0b0, 2533 (outs GPR64:$Rt), 2534 (ins ldrlit_label:$Imm19), 2535 "ldrsw\t$Rt, $Imm19", 2536 [], NoItinerary>; 2537 2538 def PRFM_lit : A64I_LDRlit<0b11, 0b0, 2539 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19), 2540 "prfm\t$Rt, $Imm19", 2541 [], NoItinerary>; 2542} 2543 2544//===----------------------------------------------------------------------===// 2545// Load-store exclusive instructions 2546//===----------------------------------------------------------------------===// 2547// Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB, 2548// STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB, 2549// STLRH, STLR, LDARB, LDARH, LDAR 2550 2551// Since these instructions have the undefined register bits set to 1 in 2552// their canonical form, we need a post encoder method to set those bits 2553// to 1 when encoding these instructions. We do this using the 2554// fixLoadStoreExclusive function. This function has template parameters: 2555// 2556// fixLoadStoreExclusive<int hasRs, int hasRt2> 2557// 2558// hasRs indicates that the instruction uses the Rs field, so we won't set 2559// it to 1 (and the same for Rt2). We don't need template parameters for 2560// the other register fiels since Rt and Rn are always used. 2561 2562// This operand parses a GPR64xsp register, followed by an optional immediate 2563// #0. 2564def GPR64xsp0_asmoperand : AsmOperandClass { 2565 let Name = "GPR64xsp0"; 2566 let PredicateMethod = "isWrappedReg"; 2567 let RenderMethod = "addRegOperands"; 2568 let ParserMethod = "ParseLSXAddressOperand"; 2569 // Diagnostics are provided by ParserMethod 2570} 2571 2572def GPR64xsp0 : RegisterOperand<GPR64xsp> { 2573 let ParserMatchClass = GPR64xsp0_asmoperand; 2574} 2575 2576//===---------------------------------- 2577// Store-exclusive (releasing & normal) 2578//===---------------------------------- 2579 2580class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2581 dag ins, list<dag> pat, 2582 InstrItinClass itin> : 2583 A64I_LDSTex_stn <size, 2584 opcode{2}, 0, opcode{1}, opcode{0}, 2585 outs, ins, 2586 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"), 2587 pat, itin> { 2588 let mayStore = 1; 2589 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>"; 2590 let Constraints = "@earlyclobber $Rs"; 2591} 2592 2593multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> { 2594 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2595 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2596 [], NoItinerary>; 2597 2598 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2599 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2600 [],NoItinerary>; 2601 2602 def _word: A64I_SRexs_impl<0b10, opcode, asmstr, 2603 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2604 [], NoItinerary>; 2605 2606 def _dword: A64I_SRexs_impl<0b11, opcode, asmstr, 2607 (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn), 2608 [], NoItinerary>; 2609} 2610 2611defm STXR : A64I_SRex<"stxr", 0b000, "STXR">; 2612defm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">; 2613 2614//===---------------------------------- 2615// Loads 2616//===---------------------------------- 2617 2618class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2619 dag ins, list<dag> pat, 2620 InstrItinClass itin> : 2621 A64I_LDSTex_tn <size, 2622 opcode{2}, 1, opcode{1}, opcode{0}, 2623 outs, ins, 2624 !strconcat(asm, "\t$Rt, [$Rn]"), 2625 pat, itin> { 2626 let mayLoad = 1; 2627 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>"; 2628} 2629 2630multiclass A64I_LRex<string asmstr, bits<3> opcode> { 2631 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2632 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2633 [], NoItinerary>; 2634 2635 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2636 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2637 [], NoItinerary>; 2638 2639 def _word: A64I_LRexs_impl<0b10, opcode, asmstr, 2640 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2641 [], NoItinerary>; 2642 2643 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr, 2644 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn), 2645 [], NoItinerary>; 2646} 2647 2648defm LDXR : A64I_LRex<"ldxr", 0b000>; 2649defm LDAXR : A64I_LRex<"ldaxr", 0b001>; 2650defm LDAR : A64I_LRex<"ldar", 0b101>; 2651 2652class acquiring_load<PatFrag base> 2653 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 2654 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 2655 return Ordering == Acquire || Ordering == SequentiallyConsistent; 2656}]>; 2657 2658def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 2659def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 2660def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 2661def atomic_load_acquire_64 : acquiring_load<atomic_load_64>; 2662 2663def : Pat<(atomic_load_acquire_8 i64:$Rn), (LDAR_byte $Rn)>; 2664def : Pat<(atomic_load_acquire_16 i64:$Rn), (LDAR_hword $Rn)>; 2665def : Pat<(atomic_load_acquire_32 i64:$Rn), (LDAR_word $Rn)>; 2666def : Pat<(atomic_load_acquire_64 i64:$Rn), (LDAR_dword $Rn)>; 2667 2668//===---------------------------------- 2669// Store-release (no exclusivity) 2670//===---------------------------------- 2671 2672class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2673 dag ins, list<dag> pat, 2674 InstrItinClass itin> : 2675 A64I_LDSTex_tn <size, 2676 opcode{2}, 0, opcode{1}, opcode{0}, 2677 outs, ins, 2678 !strconcat(asm, "\t$Rt, [$Rn]"), 2679 pat, itin> { 2680 let mayStore = 1; 2681 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>"; 2682} 2683 2684class releasing_store<PatFrag base> 2685 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 2686 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 2687 return Ordering == Release || Ordering == SequentiallyConsistent; 2688}]>; 2689 2690def atomic_store_release_8 : releasing_store<atomic_store_8>; 2691def atomic_store_release_16 : releasing_store<atomic_store_16>; 2692def atomic_store_release_32 : releasing_store<atomic_store_32>; 2693def atomic_store_release_64 : releasing_store<atomic_store_64>; 2694 2695multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> { 2696 def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2697 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2698 [(atomic_store_release_8 i64:$Rn, i32:$Rt)], 2699 NoItinerary>; 2700 2701 def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2702 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2703 [(atomic_store_release_16 i64:$Rn, i32:$Rt)], 2704 NoItinerary>; 2705 2706 def _word: A64I_SLexs_impl<0b10, opcode, asmstr, 2707 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2708 [(atomic_store_release_32 i64:$Rn, i32:$Rt)], 2709 NoItinerary>; 2710 2711 def _dword: A64I_SLexs_impl<0b11, opcode, asmstr, 2712 (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn), 2713 [(atomic_store_release_64 i64:$Rn, i64:$Rt)], 2714 NoItinerary>; 2715} 2716 2717defm STLR : A64I_SLex<"stlr", 0b101, "STLR">; 2718 2719//===---------------------------------- 2720// Store-exclusive pair (releasing & normal) 2721//===---------------------------------- 2722 2723class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2724 dag ins, list<dag> pat, 2725 InstrItinClass itin> : 2726 A64I_LDSTex_stt2n <size, 2727 opcode{2}, 0, opcode{1}, opcode{0}, 2728 outs, ins, 2729 !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"), 2730 pat, itin> { 2731 let mayStore = 1; 2732} 2733 2734 2735multiclass A64I_SPex<string asmstr, bits<3> opcode> { 2736 def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs), 2737 (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2, 2738 GPR64xsp0:$Rn), 2739 [], NoItinerary>; 2740 2741 def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs), 2742 (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2, 2743 GPR64xsp0:$Rn), 2744 [], NoItinerary>; 2745} 2746 2747defm STXP : A64I_SPex<"stxp", 0b010>; 2748defm STLXP : A64I_SPex<"stlxp", 0b011>; 2749 2750//===---------------------------------- 2751// Load-exclusive pair (acquiring & normal) 2752//===---------------------------------- 2753 2754class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2755 dag ins, list<dag> pat, 2756 InstrItinClass itin> : 2757 A64I_LDSTex_tt2n <size, 2758 opcode{2}, 1, opcode{1}, opcode{0}, 2759 outs, ins, 2760 !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"), 2761 pat, itin>{ 2762 let mayLoad = 1; 2763 let DecoderMethod = "DecodeLoadPairExclusiveInstruction"; 2764 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>"; 2765} 2766 2767multiclass A64I_LPex<string asmstr, bits<3> opcode> { 2768 def _word: A64I_LPexs_impl<0b10, opcode, asmstr, 2769 (outs GPR32:$Rt, GPR32:$Rt2), 2770 (ins GPR64xsp0:$Rn), 2771 [], NoItinerary>; 2772 2773 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr, 2774 (outs GPR64:$Rt, GPR64:$Rt2), 2775 (ins GPR64xsp0:$Rn), 2776 [], NoItinerary>; 2777} 2778 2779defm LDXP : A64I_LPex<"ldxp", 0b010>; 2780defm LDAXP : A64I_LPex<"ldaxp", 0b011>; 2781 2782//===----------------------------------------------------------------------===// 2783// Load-store register (unscaled immediate) instructions 2784//===----------------------------------------------------------------------===// 2785// Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM 2786// 2787// and 2788// 2789//===----------------------------------------------------------------------===// 2790// Load-store register (register offset) instructions 2791//===----------------------------------------------------------------------===// 2792// Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM 2793// 2794// and 2795// 2796//===----------------------------------------------------------------------===// 2797// Load-store register (unsigned immediate) instructions 2798//===----------------------------------------------------------------------===// 2799// Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM 2800// 2801// and 2802// 2803//===----------------------------------------------------------------------===// 2804// Load-store register (immediate post-indexed) instructions 2805//===----------------------------------------------------------------------===// 2806// Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW 2807// 2808// and 2809// 2810//===----------------------------------------------------------------------===// 2811// Load-store register (immediate pre-indexed) instructions 2812//===----------------------------------------------------------------------===// 2813// Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW 2814 2815// Note that patterns are much later on in a completely separate section (they 2816// need ADRPxi to be defined). 2817 2818//===------------------------------- 2819// 1. Various operands needed 2820//===------------------------------- 2821 2822//===------------------------------- 2823// 1.1 Unsigned 12-bit immediate operands 2824//===------------------------------- 2825// The addressing mode for these instructions consists of an unsigned 12-bit 2826// immediate which is scaled by the size of the memory access. 2827// 2828// We represent this in the MC layer by two operands: 2829// 1. A base register. 2830// 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]" 2831// would have '1' in this field. 2832// This means that separate functions are needed for converting representations 2833// which *are* aware of the intended access size. 2834 2835// Anything that creates an MCInst (Decoding, selection and AsmParsing) has to 2836// know the access size via some means. An isolated operand does not have this 2837// information unless told from here, which means we need separate tablegen 2838// Operands for each access size. This multiclass takes care of instantiating 2839// the correct template functions in the rest of the backend. 2840 2841//===------------------------------- 2842// 1.1 Unsigned 12-bit immediate operands 2843//===------------------------------- 2844 2845multiclass offsets_uimm12<int MemSize, string prefix> { 2846 def uimm12_asmoperand : AsmOperandClass { 2847 let Name = "OffsetUImm12_" # MemSize; 2848 let PredicateMethod = "isOffsetUImm12<" # MemSize # ">"; 2849 let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">"; 2850 let DiagnosticType = "LoadStoreUImm12_" # MemSize; 2851 } 2852 2853 // Pattern is really no more than an ImmLeaf, but predicated on MemSize which 2854 // complicates things beyond TableGen's ken. 2855 def uimm12 : Operand<i64>, 2856 ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> { 2857 let ParserMatchClass 2858 = !cast<AsmOperandClass>(prefix # uimm12_asmoperand); 2859 2860 let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">"; 2861 let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">"; 2862 } 2863} 2864 2865defm byte_ : offsets_uimm12<1, "byte_">; 2866defm hword_ : offsets_uimm12<2, "hword_">; 2867defm word_ : offsets_uimm12<4, "word_">; 2868defm dword_ : offsets_uimm12<8, "dword_">; 2869defm qword_ : offsets_uimm12<16, "qword_">; 2870 2871//===------------------------------- 2872// 1.1 Signed 9-bit immediate operands 2873//===------------------------------- 2874 2875// The MCInst is expected to store the bit-wise encoding of the value, 2876// which amounts to lopping off the extended sign bits. 2877def SDXF_simm9 : SDNodeXForm<imm, [{ 2878 return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32); 2879}]>; 2880 2881def simm9_asmoperand : AsmOperandClass { 2882 let Name = "SImm9"; 2883 let PredicateMethod = "isSImm<9>"; 2884 let RenderMethod = "addSImmOperands<9>"; 2885 let DiagnosticType = "LoadStoreSImm9"; 2886} 2887 2888def simm9 : Operand<i64>, 2889 ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }], 2890 SDXF_simm9> { 2891 let PrintMethod = "printOffsetSImm9Operand"; 2892 let ParserMatchClass = simm9_asmoperand; 2893} 2894 2895 2896//===------------------------------- 2897// 1.3 Register offset extensions 2898//===------------------------------- 2899 2900// The assembly-syntax for these addressing-modes is: 2901// [<Xn|SP>, <R><m> {, <extend> {<amount>}}] 2902// 2903// The essential semantics are: 2904// + <amount> is a shift: #<log(transfer size)> or #0 2905// + <R> can be W or X. 2906// + If <R> is W, <extend> can be UXTW or SXTW 2907// + If <R> is X, <extend> can be LSL or SXTX 2908// 2909// The trickiest of those constraints is that Rm can be either GPR32 or GPR64, 2910// which will need separate instructions for LLVM type-consistency. We'll also 2911// need separate operands, of course. 2912multiclass regexts<int MemSize, int RmSize, RegisterClass GPR, 2913 string Rm, string prefix> { 2914 def regext_asmoperand : AsmOperandClass { 2915 let Name = "AddrRegExtend_" # MemSize # "_" # Rm; 2916 let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">"; 2917 let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">"; 2918 let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize; 2919 } 2920 2921 def regext : Operand<i64> { 2922 let PrintMethod 2923 = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">"; 2924 2925 let DecoderMethod = "DecodeAddrRegExtendOperand"; 2926 let ParserMatchClass 2927 = !cast<AsmOperandClass>(prefix # regext_asmoperand); 2928 } 2929} 2930 2931multiclass regexts_wx<int MemSize, string prefix> { 2932 // Rm is an X-register if LSL or SXTX are specified as the shift. 2933 defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">; 2934 2935 // Rm is a W-register if UXTW or SXTW are specified as the shift. 2936 defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">; 2937} 2938 2939defm byte_ : regexts_wx<1, "byte_">; 2940defm hword_ : regexts_wx<2, "hword_">; 2941defm word_ : regexts_wx<4, "word_">; 2942defm dword_ : regexts_wx<8, "dword_">; 2943defm qword_ : regexts_wx<16, "qword_">; 2944 2945 2946//===------------------------------ 2947// 2. The instructions themselves. 2948//===------------------------------ 2949 2950// We have the following instructions to implement: 2951// | | B | H | W | X | 2952// |-----------------+-------+-------+-------+--------| 2953// | unsigned str | STRB | STRH | STR | STR | 2954// | unsigned ldr | LDRB | LDRH | LDR | LDR | 2955// | signed ldr to W | LDRSB | LDRSH | - | - | 2956// | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) | 2957 2958// This will instantiate the LDR/STR instructions you'd expect to use for an 2959// unsigned datatype (first two rows above) or floating-point register, which is 2960// reasonably uniform across all access sizes. 2961 2962 2963//===------------------------------ 2964// 2.1 Regular instructions 2965//===------------------------------ 2966 2967// This class covers the basic unsigned or irrelevantly-signed loads and stores, 2968// to general-purpose and floating-point registers. 2969 2970class AddrParams<string prefix> { 2971 Operand uimm12 = !cast<Operand>(prefix # "_uimm12"); 2972 2973 Operand regextWm = !cast<Operand>(prefix # "_Wm_regext"); 2974 Operand regextXm = !cast<Operand>(prefix # "_Xm_regext"); 2975} 2976 2977def byte_addrparams : AddrParams<"byte">; 2978def hword_addrparams : AddrParams<"hword">; 2979def word_addrparams : AddrParams<"word">; 2980def dword_addrparams : AddrParams<"dword">; 2981def qword_addrparams : AddrParams<"qword">; 2982 2983multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v, 2984 bit high_opc, string asmsuffix, 2985 RegisterClass GPR, AddrParams params> { 2986 // Unsigned immediate 2987 def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0}, 2988 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12), 2989 "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]", 2990 [], NoItinerary> { 2991 let mayStore = 1; 2992 } 2993 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]", 2994 (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 2995 2996 def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1}, 2997 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 2998 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]", 2999 [], NoItinerary> { 3000 let mayLoad = 1; 3001 } 3002 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]", 3003 (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3004 3005 // Register offset (four of these: load/store and Wm/Xm). 3006 let mayLoad = 1 in { 3007 def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0, 3008 (outs GPR:$Rt), 3009 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 3010 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 3011 [], NoItinerary>; 3012 3013 def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1, 3014 (outs GPR:$Rt), 3015 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 3016 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 3017 [], NoItinerary>; 3018 } 3019 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]", 3020 (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn, 3021 GPR64:$Rm, 2)>; 3022 3023 let mayStore = 1 in { 3024 def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0, 3025 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm, 3026 params.regextWm:$Ext), 3027 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 3028 [], NoItinerary>; 3029 3030 def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1, 3031 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 3032 params.regextXm:$Ext), 3033 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 3034 [], NoItinerary>; 3035 } 3036 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]", 3037 (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn, 3038 GPR64:$Rm, 2)>; 3039 3040 // Unaligned immediate 3041 def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0}, 3042 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3043 "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3044 [], NoItinerary> { 3045 let mayStore = 1; 3046 } 3047 def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]", 3048 (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3049 3050 def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1}, 3051 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9), 3052 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3053 [], NoItinerary> { 3054 let mayLoad = 1; 3055 } 3056 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]", 3057 (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3058 3059 // Post-indexed 3060 def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0}, 3061 (outs GPR64xsp:$Rn_wb), 3062 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3063 "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9", 3064 [], NoItinerary> { 3065 let Constraints = "$Rn = $Rn_wb"; 3066 let mayStore = 1; 3067 3068 // Decoder only needed for unpredictability checking (FIXME). 3069 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3070 } 3071 3072 def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1}, 3073 (outs GPR:$Rt, GPR64xsp:$Rn_wb), 3074 (ins GPR64xsp:$Rn, simm9:$SImm9), 3075 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9", 3076 [], NoItinerary> { 3077 let mayLoad = 1; 3078 let Constraints = "$Rn = $Rn_wb"; 3079 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3080 } 3081 3082 // Pre-indexed 3083 def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0}, 3084 (outs GPR64xsp:$Rn_wb), 3085 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3086 "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!", 3087 [], NoItinerary> { 3088 let Constraints = "$Rn = $Rn_wb"; 3089 let mayStore = 1; 3090 3091 // Decoder only needed for unpredictability checking (FIXME). 3092 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3093 } 3094 3095 def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1}, 3096 (outs GPR:$Rt, GPR64xsp:$Rn_wb), 3097 (ins GPR64xsp:$Rn, simm9:$SImm9), 3098 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!", 3099 [], NoItinerary> { 3100 let mayLoad = 1; 3101 let Constraints = "$Rn = $Rn_wb"; 3102 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3103 } 3104 3105} 3106 3107// STRB/LDRB: First define the instructions 3108defm LS8 3109 : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>; 3110 3111// STRH/LDRH 3112defm LS16 3113 : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>; 3114 3115 3116// STR/LDR to/from a W register 3117defm LS32 3118 : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>; 3119 3120// STR/LDR to/from an X register 3121defm LS64 3122 : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>; 3123 3124let Predicates = [HasFPARMv8] in { 3125// STR/LDR to/from a B register 3126defm LSFP8 3127 : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>; 3128 3129// STR/LDR to/from an H register 3130defm LSFP16 3131 : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>; 3132 3133// STR/LDR to/from an S register 3134defm LSFP32 3135 : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>; 3136// STR/LDR to/from a D register 3137defm LSFP64 3138 : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>; 3139// STR/LDR to/from a Q register 3140defm LSFP128 3141 : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128, 3142 qword_addrparams>; 3143} 3144 3145//===------------------------------ 3146// 2.3 Signed loads 3147//===------------------------------ 3148 3149// Byte and half-word signed loads can both go into either an X or a W register, 3150// so it's worth factoring out. Signed word loads don't fit because there is no 3151// W version. 3152multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params, 3153 string prefix> { 3154 // Unsigned offset 3155 def w : A64I_LSunsigimm<size, 0b0, 0b11, 3156 (outs GPR32:$Rt), 3157 (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 3158 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]", 3159 [], NoItinerary> { 3160 let mayLoad = 1; 3161 } 3162 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]", 3163 (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>; 3164 3165 def x : A64I_LSunsigimm<size, 0b0, 0b10, 3166 (outs GPR64:$Rt), 3167 (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 3168 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]", 3169 [], NoItinerary> { 3170 let mayLoad = 1; 3171 } 3172 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]", 3173 (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3174 3175 // Register offset 3176 let mayLoad = 1 in { 3177 def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0, 3178 (outs GPR32:$Rt), 3179 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 3180 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3181 [], NoItinerary>; 3182 3183 def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1, 3184 (outs GPR32:$Rt), 3185 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 3186 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3187 [], NoItinerary>; 3188 3189 def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0, 3190 (outs GPR64:$Rt), 3191 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 3192 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3193 [], NoItinerary>; 3194 3195 def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1, 3196 (outs GPR64:$Rt), 3197 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 3198 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3199 [], NoItinerary>; 3200 } 3201 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]", 3202 (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn, 3203 GPR64:$Rm, 2)>; 3204 3205 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]", 3206 (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn, 3207 GPR64:$Rm, 2)>; 3208 3209 3210 let mayLoad = 1 in { 3211 // Unaligned offset 3212 def w_U : A64I_LSunalimm<size, 0b0, 0b11, 3213 (outs GPR32:$Rt), 3214 (ins GPR64xsp:$Rn, simm9:$SImm9), 3215 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3216 [], NoItinerary>; 3217 3218 def x_U : A64I_LSunalimm<size, 0b0, 0b10, 3219 (outs GPR64:$Rt), 3220 (ins GPR64xsp:$Rn, simm9:$SImm9), 3221 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3222 [], NoItinerary>; 3223 3224 3225 // Post-indexed 3226 def w_PostInd : A64I_LSpostind<size, 0b0, 0b11, 3227 (outs GPR32:$Rt, GPR64xsp:$Rn_wb), 3228 (ins GPR64xsp:$Rn, simm9:$SImm9), 3229 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9", 3230 [], NoItinerary> { 3231 let Constraints = "$Rn = $Rn_wb"; 3232 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3233 } 3234 3235 def x_PostInd : A64I_LSpostind<size, 0b0, 0b10, 3236 (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3237 (ins GPR64xsp:$Rn, simm9:$SImm9), 3238 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9", 3239 [], NoItinerary> { 3240 let Constraints = "$Rn = $Rn_wb"; 3241 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3242 } 3243 3244 // Pre-indexed 3245 def w_PreInd : A64I_LSpreind<size, 0b0, 0b11, 3246 (outs GPR32:$Rt, GPR64xsp:$Rn_wb), 3247 (ins GPR64xsp:$Rn, simm9:$SImm9), 3248 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!", 3249 [], NoItinerary> { 3250 let Constraints = "$Rn = $Rn_wb"; 3251 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3252 } 3253 3254 def x_PreInd : A64I_LSpreind<size, 0b0, 0b10, 3255 (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3256 (ins GPR64xsp:$Rn, simm9:$SImm9), 3257 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!", 3258 [], NoItinerary> { 3259 let Constraints = "$Rn = $Rn_wb"; 3260 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3261 } 3262 } // let mayLoad = 1 3263} 3264 3265// LDRSB 3266defm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">; 3267// LDRSH 3268defm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">; 3269 3270// LDRSW: load a 32-bit register, sign-extending to 64-bits. 3271def LDRSWx 3272 : A64I_LSunsigimm<0b10, 0b0, 0b10, 3273 (outs GPR64:$Rt), 3274 (ins GPR64xsp:$Rn, word_uimm12:$UImm12), 3275 "ldrsw\t$Rt, [$Rn, $UImm12]", 3276 [], NoItinerary> { 3277 let mayLoad = 1; 3278} 3279def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3280 3281let mayLoad = 1 in { 3282 def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0, 3283 (outs GPR64:$Rt), 3284 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext), 3285 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]", 3286 [], NoItinerary>; 3287 3288 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1, 3289 (outs GPR64:$Rt), 3290 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext), 3291 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]", 3292 [], NoItinerary>; 3293} 3294def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]", 3295 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>; 3296 3297 3298def LDURSWx 3299 : A64I_LSunalimm<0b10, 0b0, 0b10, 3300 (outs GPR64:$Rt), 3301 (ins GPR64xsp:$Rn, simm9:$SImm9), 3302 "ldursw\t$Rt, [$Rn, $SImm9]", 3303 [], NoItinerary> { 3304 let mayLoad = 1; 3305} 3306def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3307 3308def LDRSWx_PostInd 3309 : A64I_LSpostind<0b10, 0b0, 0b10, 3310 (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3311 (ins GPR64xsp:$Rn, simm9:$SImm9), 3312 "ldrsw\t$Rt, [$Rn], $SImm9", 3313 [], NoItinerary> { 3314 let mayLoad = 1; 3315 let Constraints = "$Rn = $Rn_wb"; 3316 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3317} 3318 3319def LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10, 3320 (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3321 (ins GPR64xsp:$Rn, simm9:$SImm9), 3322 "ldrsw\t$Rt, [$Rn, $SImm9]!", 3323 [], NoItinerary> { 3324 let mayLoad = 1; 3325 let Constraints = "$Rn = $Rn_wb"; 3326 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3327} 3328 3329//===------------------------------ 3330// 2.4 Prefetch operations 3331//===------------------------------ 3332 3333def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs), 3334 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12), 3335 "prfm\t$Rt, [$Rn, $UImm12]", 3336 [], NoItinerary> { 3337 let mayLoad = 1; 3338} 3339def : InstAlias<"prfm $Rt, [$Rn]", 3340 (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>; 3341 3342let mayLoad = 1 in { 3343 def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs), 3344 (ins prefetch_op:$Rt, GPR64xsp:$Rn, 3345 GPR32:$Rm, dword_Wm_regext:$Ext), 3346 "prfm\t$Rt, [$Rn, $Rm, $Ext]", 3347 [], NoItinerary>; 3348 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs), 3349 (ins prefetch_op:$Rt, GPR64xsp:$Rn, 3350 GPR64:$Rm, dword_Xm_regext:$Ext), 3351 "prfm\t$Rt, [$Rn, $Rm, $Ext]", 3352 [], NoItinerary>; 3353} 3354 3355def : InstAlias<"prfm $Rt, [$Rn, $Rm]", 3356 (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn, 3357 GPR64:$Rm, 2)>; 3358 3359 3360def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs), 3361 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3362 "prfum\t$Rt, [$Rn, $SImm9]", 3363 [], NoItinerary> { 3364 let mayLoad = 1; 3365} 3366def : InstAlias<"prfum $Rt, [$Rn]", 3367 (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>; 3368 3369//===----------------------------------------------------------------------===// 3370// Load-store register (unprivileged) instructions 3371//===----------------------------------------------------------------------===// 3372// Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH 3373 3374// These instructions very much mirror the "unscaled immediate" loads, but since 3375// there are no floating-point variants we need to split them out into their own 3376// section to avoid instantiation of "ldtr d0, [sp]" etc. 3377 3378multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR, 3379 string prefix> { 3380 def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00, 3381 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3382 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3383 [], NoItinerary> { 3384 let mayStore = 1; 3385 } 3386 3387 def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]", 3388 (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3389 3390 def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01, 3391 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9), 3392 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3393 [], NoItinerary> { 3394 let mayLoad = 1; 3395 } 3396 3397 def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]", 3398 (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3399 3400} 3401 3402// STTRB/LDTRB: First define the instructions 3403defm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">; 3404 3405// STTRH/LDTRH 3406defm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">; 3407 3408// STTR/LDTR to/from a W register 3409defm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">; 3410 3411// STTR/LDTR to/from an X register 3412defm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">; 3413 3414// Now a class for the signed instructions that can go to either 32 or 64 3415// bits... 3416multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> { 3417 let mayLoad = 1 in { 3418 def w : A64I_LSunpriv<size, 0b0, 0b11, 3419 (outs GPR32:$Rt), 3420 (ins GPR64xsp:$Rn, simm9:$SImm9), 3421 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3422 [], NoItinerary>; 3423 3424 def x : A64I_LSunpriv<size, 0b0, 0b10, 3425 (outs GPR64:$Rt), 3426 (ins GPR64xsp:$Rn, simm9:$SImm9), 3427 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3428 [], NoItinerary>; 3429 } 3430 3431 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]", 3432 (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>; 3433 3434 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]", 3435 (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3436 3437} 3438 3439// LDTRSB 3440defm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">; 3441// LDTRSH 3442defm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">; 3443 3444// And finally LDTRSW which only goes to 64 bits. 3445def LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10, 3446 (outs GPR64:$Rt), 3447 (ins GPR64xsp:$Rn, simm9:$SImm9), 3448 "ldtrsw\t$Rt, [$Rn, $SImm9]", 3449 [], NoItinerary> { 3450 let mayLoad = 1; 3451} 3452def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3453 3454//===----------------------------------------------------------------------===// 3455// Load-store register pair (offset) instructions 3456//===----------------------------------------------------------------------===// 3457// 3458// and 3459// 3460//===----------------------------------------------------------------------===// 3461// Load-store register pair (post-indexed) instructions 3462//===----------------------------------------------------------------------===// 3463// Contains: STP, LDP, LDPSW 3464// 3465// and 3466// 3467//===----------------------------------------------------------------------===// 3468// Load-store register pair (pre-indexed) instructions 3469//===----------------------------------------------------------------------===// 3470// Contains: STP, LDP, LDPSW 3471// 3472// and 3473// 3474//===----------------------------------------------------------------------===// 3475// Load-store non-temporal register pair (offset) instructions 3476//===----------------------------------------------------------------------===// 3477// Contains: STNP, LDNP 3478 3479 3480// Anything that creates an MCInst (Decoding, selection and AsmParsing) has to 3481// know the access size via some means. An isolated operand does not have this 3482// information unless told from here, which means we need separate tablegen 3483// Operands for each access size. This multiclass takes care of instantiating 3484// the correct template functions in the rest of the backend. 3485 3486multiclass offsets_simm7<string MemSize, string prefix> { 3487 // The bare signed 7-bit immediate is used in post-indexed instructions, but 3488 // because of the scaling performed a generic "simm7" operand isn't 3489 // appropriate here either. 3490 def simm7_asmoperand : AsmOperandClass { 3491 let Name = "SImm7_Scaled" # MemSize; 3492 let PredicateMethod = "isSImm7Scaled<" # MemSize # ">"; 3493 let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">"; 3494 let DiagnosticType = "LoadStoreSImm7_" # MemSize; 3495 } 3496 3497 def simm7 : Operand<i64> { 3498 let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">"; 3499 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand"); 3500 } 3501} 3502 3503defm word_ : offsets_simm7<"4", "word_">; 3504defm dword_ : offsets_simm7<"8", "dword_">; 3505defm qword_ : offsets_simm7<"16", "qword_">; 3506 3507multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg, 3508 Operand simm7, string prefix> { 3509 def _STR : A64I_LSPoffset<opc, v, 0b0, (outs), 3510 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3511 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3512 let mayStore = 1; 3513 let DecoderMethod = "DecodeLDSTPairInstruction"; 3514 } 3515 def : InstAlias<"stp $Rt, $Rt2, [$Rn]", 3516 (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt, 3517 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3518 3519 def _LDR : A64I_LSPoffset<opc, v, 0b1, 3520 (outs SomeReg:$Rt, SomeReg:$Rt2), 3521 (ins GPR64xsp:$Rn, simm7:$SImm7), 3522 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3523 let mayLoad = 1; 3524 let DecoderMethod = "DecodeLDSTPairInstruction"; 3525 } 3526 def : InstAlias<"ldp $Rt, $Rt2, [$Rn]", 3527 (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt, 3528 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3529 3530 def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0, 3531 (outs GPR64xsp:$Rn_wb), 3532 (ins SomeReg:$Rt, SomeReg:$Rt2, 3533 GPR64xsp:$Rn, 3534 simm7:$SImm7), 3535 "stp\t$Rt, $Rt2, [$Rn], $SImm7", 3536 [], NoItinerary> { 3537 let mayStore = 1; 3538 let Constraints = "$Rn = $Rn_wb"; 3539 3540 // Decoder only needed for unpredictability checking (FIXME). 3541 let DecoderMethod = "DecodeLDSTPairInstruction"; 3542 } 3543 3544 def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1, 3545 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb), 3546 (ins GPR64xsp:$Rn, simm7:$SImm7), 3547 "ldp\t$Rt, $Rt2, [$Rn], $SImm7", 3548 [], NoItinerary> { 3549 let mayLoad = 1; 3550 let Constraints = "$Rn = $Rn_wb"; 3551 let DecoderMethod = "DecodeLDSTPairInstruction"; 3552 } 3553 3554 def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb), 3555 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3556 "stp\t$Rt, $Rt2, [$Rn, $SImm7]!", 3557 [], NoItinerary> { 3558 let mayStore = 1; 3559 let Constraints = "$Rn = $Rn_wb"; 3560 let DecoderMethod = "DecodeLDSTPairInstruction"; 3561 } 3562 3563 def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1, 3564 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb), 3565 (ins GPR64xsp:$Rn, simm7:$SImm7), 3566 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!", 3567 [], NoItinerary> { 3568 let mayLoad = 1; 3569 let Constraints = "$Rn = $Rn_wb"; 3570 let DecoderMethod = "DecodeLDSTPairInstruction"; 3571 } 3572 3573 def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs), 3574 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3575 "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3576 let mayStore = 1; 3577 let DecoderMethod = "DecodeLDSTPairInstruction"; 3578 } 3579 def : InstAlias<"stnp $Rt, $Rt2, [$Rn]", 3580 (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt, 3581 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3582 3583 def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1, 3584 (outs SomeReg:$Rt, SomeReg:$Rt2), 3585 (ins GPR64xsp:$Rn, simm7:$SImm7), 3586 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3587 let mayLoad = 1; 3588 let DecoderMethod = "DecodeLDSTPairInstruction"; 3589 } 3590 def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]", 3591 (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt, 3592 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3593 3594} 3595 3596 3597defm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">; 3598defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">; 3599 3600let Predicates = [HasFPARMv8] in { 3601defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">; 3602defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">; 3603defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7, 3604 "LSFPPair128">; 3605} 3606 3607 3608def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1, 3609 (outs GPR64:$Rt, GPR64:$Rt2), 3610 (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3611 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3612 let mayLoad = 1; 3613 let DecoderMethod = "DecodeLDSTPairInstruction"; 3614} 3615def : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]", 3616 (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>; 3617 3618def LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1, 3619 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb), 3620 (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3621 "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7", 3622 [], NoItinerary> { 3623 let mayLoad = 1; 3624 let Constraints = "$Rn = $Rn_wb"; 3625 let DecoderMethod = "DecodeLDSTPairInstruction"; 3626} 3627 3628def LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1, 3629 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb), 3630 (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3631 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!", 3632 [], NoItinerary> { 3633 let mayLoad = 1; 3634 let Constraints = "$Rn = $Rn_wb"; 3635 let DecoderMethod = "DecodeLDSTPairInstruction"; 3636} 3637 3638//===----------------------------------------------------------------------===// 3639// Logical (immediate) instructions 3640//===----------------------------------------------------------------------===// 3641// Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV 3642 3643multiclass logical_imm_operands<string prefix, string note, 3644 int size, ValueType VT> { 3645 def _asmoperand : AsmOperandClass { 3646 let Name = "LogicalImm" # note # size; 3647 let PredicateMethod = "isLogicalImm" # note # "<" # size # ">"; 3648 let RenderMethod = "addLogicalImmOperands<" # size # ">"; 3649 let DiagnosticType = "LogicalSecondSource"; 3650 } 3651 3652 def _operand 3653 : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> { 3654 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 3655 let PrintMethod = "printLogicalImmOperand<" # size # ">"; 3656 let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">"; 3657 } 3658} 3659 3660defm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>; 3661defm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>; 3662 3663// The mov versions only differ in assembly parsing, where they 3664// exclude values representable with either MOVZ or MOVN. 3665defm logical_imm32_mov 3666 : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>; 3667defm logical_imm64_mov 3668 : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>; 3669 3670 3671multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> { 3672 def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd), 3673 (ins GPR32:$Rn, logical_imm32_operand:$Imm), 3674 !strconcat(asmop, "\t$Rd, $Rn, $Imm"), 3675 [(set i32:$Rd, 3676 (opnode i32:$Rn, logical_imm32_operand:$Imm))], 3677 NoItinerary>; 3678 3679 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd), 3680 (ins GPR64:$Rn, logical_imm64_operand:$Imm), 3681 !strconcat(asmop, "\t$Rd, $Rn, $Imm"), 3682 [(set i64:$Rd, 3683 (opnode i64:$Rn, logical_imm64_operand:$Imm))], 3684 NoItinerary>; 3685} 3686 3687defm AND : A64I_logimmSizes<0b00, "and", and>; 3688defm ORR : A64I_logimmSizes<0b01, "orr", or>; 3689defm EOR : A64I_logimmSizes<0b10, "eor", xor>; 3690 3691let Defs = [NZCV] in { 3692 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd), 3693 (ins GPR32:$Rn, logical_imm32_operand:$Imm), 3694 "ands\t$Rd, $Rn, $Imm", 3695 [], NoItinerary>; 3696 3697 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd), 3698 (ins GPR64:$Rn, logical_imm64_operand:$Imm), 3699 "ands\t$Rd, $Rn, $Imm", 3700 [], NoItinerary>; 3701} 3702 3703 3704def : InstAlias<"tst $Rn, $Imm", 3705 (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>; 3706def : InstAlias<"tst $Rn, $Imm", 3707 (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>; 3708def : InstAlias<"mov $Rd, $Imm", 3709 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>; 3710def : InstAlias<"mov $Rd, $Imm", 3711 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>; 3712 3713//===----------------------------------------------------------------------===// 3714// Logical (shifted register) instructions 3715//===----------------------------------------------------------------------===// 3716// Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV 3717 3718// Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS" 3719// behaves differently for unsigned comparisons, so we defensively only allow 3720// signed or n/a as the operand. In practice "unsigned greater than 0" is "not 3721// equal to 0" and LLVM gives us this. 3722def signed_cond : PatLeaf<(cond), [{ 3723 return !isUnsignedIntSetCC(N->get()); 3724}]>; 3725 3726 3727// These instructions share their "shift" operands with add/sub (shifted 3728// register instructions). They are defined there. 3729 3730// N.b. the commutable parameter is just !N. It will be first against the wall 3731// when the revolution comes. 3732multiclass logical_shifts<string prefix, bit sf, bits<2> opc, 3733 bit N, bit commutable, 3734 string asmop, SDPatternOperator opfrag, ValueType ty, 3735 RegisterClass GPR, list<Register> defs> { 3736 let isCommutable = commutable, Defs = defs in { 3737 def _lsl : A64I_logicalshift<sf, opc, 0b00, N, 3738 (outs GPR:$Rd), 3739 (ins GPR:$Rn, GPR:$Rm, 3740 !cast<Operand>("lsl_operand_" # ty):$Imm6), 3741 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3742 [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm, 3743 !cast<Operand>("lsl_operand_" # ty):$Imm6)) 3744 )], 3745 NoItinerary>; 3746 3747 def _lsr : A64I_logicalshift<sf, opc, 0b01, N, 3748 (outs GPR:$Rd), 3749 (ins GPR:$Rn, GPR:$Rm, 3750 !cast<Operand>("lsr_operand_" # ty):$Imm6), 3751 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3752 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm, 3753 !cast<Operand>("lsr_operand_" # ty):$Imm6)) 3754 )], 3755 NoItinerary>; 3756 3757 def _asr : A64I_logicalshift<sf, opc, 0b10, N, 3758 (outs GPR:$Rd), 3759 (ins GPR:$Rn, GPR:$Rm, 3760 !cast<Operand>("asr_operand_" # ty):$Imm6), 3761 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3762 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm, 3763 !cast<Operand>("asr_operand_" # ty):$Imm6)) 3764 )], 3765 NoItinerary>; 3766 3767 def _ror : A64I_logicalshift<sf, opc, 0b11, N, 3768 (outs GPR:$Rd), 3769 (ins GPR:$Rn, GPR:$Rm, 3770 !cast<Operand>("ror_operand_" # ty):$Imm6), 3771 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3772 [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm, 3773 !cast<Operand>("ror_operand_" # ty):$Imm6)) 3774 )], 3775 NoItinerary>; 3776 } 3777 3778 def _noshift 3779 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 3780 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn, 3781 GPR:$Rm, 0)>; 3782 3783 def : Pat<(opfrag ty:$Rn, ty:$Rm), 3784 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 3785} 3786 3787multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable, 3788 string asmop, SDPatternOperator opfrag, 3789 list<Register> defs> { 3790 defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N, 3791 commutable, asmop, opfrag, i64, GPR64, defs>; 3792 defm www : logical_shifts<prefix # "www", 0b0, opc, N, 3793 commutable, asmop, opfrag, i32, GPR32, defs>; 3794} 3795 3796 3797defm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>; 3798defm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>; 3799defm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>; 3800defm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands", 3801 PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), 3802 [{ (void)N; return false; }]>, 3803 [NZCV]>; 3804 3805defm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic", 3806 PatFrag<(ops node:$lhs, node:$rhs), 3807 (and node:$lhs, (not node:$rhs))>, []>; 3808defm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn", 3809 PatFrag<(ops node:$lhs, node:$rhs), 3810 (or node:$lhs, (not node:$rhs))>, []>; 3811defm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon", 3812 PatFrag<(ops node:$lhs, node:$rhs), 3813 (xor node:$lhs, (not node:$rhs))>, []>; 3814defm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics", 3815 PatFrag<(ops node:$lhs, node:$rhs), 3816 (and node:$lhs, (not node:$rhs)), 3817 [{ (void)N; return false; }]>, 3818 [NZCV]>; 3819 3820multiclass tst_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> { 3821 let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in { 3822 def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0, 3823 (outs), 3824 (ins GPR:$Rn, GPR:$Rm, 3825 !cast<Operand>("lsl_operand_" # ty):$Imm6), 3826 "tst\t$Rn, $Rm, $Imm6", 3827 [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm, 3828 !cast<Operand>("lsl_operand_" # ty):$Imm6)), 3829 0, signed_cond))], 3830 NoItinerary>; 3831 3832 3833 def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0, 3834 (outs), 3835 (ins GPR:$Rn, GPR:$Rm, 3836 !cast<Operand>("lsr_operand_" # ty):$Imm6), 3837 "tst\t$Rn, $Rm, $Imm6", 3838 [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm, 3839 !cast<Operand>("lsr_operand_" # ty):$Imm6)), 3840 0, signed_cond))], 3841 NoItinerary>; 3842 3843 def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0, 3844 (outs), 3845 (ins GPR:$Rn, GPR:$Rm, 3846 !cast<Operand>("asr_operand_" # ty):$Imm6), 3847 "tst\t$Rn, $Rm, $Imm6", 3848 [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm, 3849 !cast<Operand>("asr_operand_" # ty):$Imm6)), 3850 0, signed_cond))], 3851 NoItinerary>; 3852 3853 def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0, 3854 (outs), 3855 (ins GPR:$Rn, GPR:$Rm, 3856 !cast<Operand>("ror_operand_" # ty):$Imm6), 3857 "tst\t$Rn, $Rm, $Imm6", 3858 [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm, 3859 !cast<Operand>("ror_operand_" # ty):$Imm6)), 3860 0, signed_cond))], 3861 NoItinerary>; 3862 } 3863 3864 def _noshift : InstAlias<"tst $Rn, $Rm", 3865 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 3866 3867 def : Pat<(A64setcc (and ty:$Rn, ty:$Rm), 0, signed_cond), 3868 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 3869} 3870 3871defm TSTxx : tst_shifts<"TSTxx", 0b1, i64, GPR64>; 3872defm TSTww : tst_shifts<"TSTww", 0b0, i32, GPR32>; 3873 3874 3875multiclass mvn_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> { 3876 let isCommutable = 0, Rn = 0b11111 in { 3877 def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1, 3878 (outs GPR:$Rd), 3879 (ins GPR:$Rm, 3880 !cast<Operand>("lsl_operand_" # ty):$Imm6), 3881 "mvn\t$Rd, $Rm, $Imm6", 3882 [(set ty:$Rd, (not (shl ty:$Rm, 3883 !cast<Operand>("lsl_operand_" # ty):$Imm6)))], 3884 NoItinerary>; 3885 3886 3887 def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1, 3888 (outs GPR:$Rd), 3889 (ins GPR:$Rm, 3890 !cast<Operand>("lsr_operand_" # ty):$Imm6), 3891 "mvn\t$Rd, $Rm, $Imm6", 3892 [(set ty:$Rd, (not (srl ty:$Rm, 3893 !cast<Operand>("lsr_operand_" # ty):$Imm6)))], 3894 NoItinerary>; 3895 3896 def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1, 3897 (outs GPR:$Rd), 3898 (ins GPR:$Rm, 3899 !cast<Operand>("asr_operand_" # ty):$Imm6), 3900 "mvn\t$Rd, $Rm, $Imm6", 3901 [(set ty:$Rd, (not (sra ty:$Rm, 3902 !cast<Operand>("asr_operand_" # ty):$Imm6)))], 3903 NoItinerary>; 3904 3905 def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1, 3906 (outs GPR:$Rd), 3907 (ins GPR:$Rm, 3908 !cast<Operand>("ror_operand_" # ty):$Imm6), 3909 "mvn\t$Rd, $Rm, $Imm6", 3910 [(set ty:$Rd, (not (rotr ty:$Rm, 3911 !cast<Operand>("lsl_operand_" # ty):$Imm6)))], 3912 NoItinerary>; 3913 } 3914 3915 def _noshift : InstAlias<"mvn $Rn, $Rm", 3916 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 3917 3918 def : Pat<(not ty:$Rm), 3919 (!cast<Instruction>(prefix # "_lsl") $Rm, 0)>; 3920} 3921 3922defm MVNxx : mvn_shifts<"MVNxx", 0b1, i64, GPR64>; 3923defm MVNww : mvn_shifts<"MVNww", 0b0, i32, GPR32>; 3924 3925def MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 3926def MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 3927 3928//===----------------------------------------------------------------------===// 3929// Move wide (immediate) instructions 3930//===----------------------------------------------------------------------===// 3931// Contains: MOVN, MOVZ, MOVK + MOV aliases 3932 3933// A wide variety of different relocations are needed for variants of these 3934// instructions, so it turns out that we need a different operand for all of 3935// them. 3936multiclass movw_operands<string prefix, string instname, int width> { 3937 def _imm_asmoperand : AsmOperandClass { 3938 let Name = instname # width # "Shifted" # shift; 3939 let PredicateMethod = "is" # instname # width # "Imm"; 3940 let RenderMethod = "addMoveWideImmOperands"; 3941 let ParserMethod = "ParseImmWithLSLOperand"; 3942 let DiagnosticType = "MOVWUImm16"; 3943 } 3944 3945 def _imm : Operand<i64> { 3946 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand"); 3947 let PrintMethod = "printMoveWideImmOperand"; 3948 let EncoderMethod = "getMoveWideImmOpValue"; 3949 let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">"; 3950 3951 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift); 3952 } 3953} 3954 3955defm movn32 : movw_operands<"movn32", "MOVN", 32>; 3956defm movn64 : movw_operands<"movn64", "MOVN", 64>; 3957defm movz32 : movw_operands<"movz32", "MOVZ", 32>; 3958defm movz64 : movw_operands<"movz64", "MOVZ", 64>; 3959defm movk32 : movw_operands<"movk32", "MOVK", 32>; 3960defm movk64 : movw_operands<"movk64", "MOVK", 64>; 3961 3962multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit, 3963 dag ins64bit> { 3964 3965 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit, 3966 !strconcat(asmop, "\t$Rd, $FullImm"), 3967 [], NoItinerary> { 3968 bits<18> FullImm; 3969 let UImm16 = FullImm{15-0}; 3970 let Shift = FullImm{17-16}; 3971 } 3972 3973 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit, 3974 !strconcat(asmop, "\t$Rd, $FullImm"), 3975 [], NoItinerary> { 3976 bits<18> FullImm; 3977 let UImm16 = FullImm{15-0}; 3978 let Shift = FullImm{17-16}; 3979 } 3980} 3981 3982let isMoveImm = 1, isReMaterializable = 1, 3983 isAsCheapAsAMove = 1, hasSideEffects = 0 in { 3984 defm MOVN : A64I_movwSizes<0b00, "movn", 3985 (ins movn32_imm:$FullImm), 3986 (ins movn64_imm:$FullImm)>; 3987 3988 // Some relocations are able to convert between a MOVZ and a MOVN. If these 3989 // are applied the instruction must be emitted with the corresponding bits as 3990 // 0, which means a MOVZ needs to override that bit from the default. 3991 let PostEncoderMethod = "fixMOVZ" in 3992 defm MOVZ : A64I_movwSizes<0b10, "movz", 3993 (ins movz32_imm:$FullImm), 3994 (ins movz64_imm:$FullImm)>; 3995} 3996 3997let Constraints = "$src = $Rd" in 3998defm MOVK : A64I_movwSizes<0b11, "movk", 3999 (ins GPR32:$src, movk32_imm:$FullImm), 4000 (ins GPR64:$src, movk64_imm:$FullImm)>; 4001 4002 4003// And now the "MOV" aliases. These also need their own operands because what 4004// they accept is completely different to what the base instructions accept. 4005multiclass movalias_operand<string prefix, string basename, 4006 string immpredicate, int width> { 4007 def _asmoperand : AsmOperandClass { 4008 let Name = basename # width # "MovAlias"; 4009 let PredicateMethod 4010 = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">"; 4011 let RenderMethod 4012 = "addMoveWideMovAliasOperands<" # width # ", " 4013 # "A64Imms::" # immpredicate # ">"; 4014 } 4015 4016 def _movimm : Operand<i64> { 4017 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 4018 4019 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift); 4020 } 4021} 4022 4023defm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>; 4024defm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>; 4025defm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>; 4026defm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>; 4027 4028// FIXME: these are officially canonical aliases, but TableGen is too limited to 4029// print them at the moment. I believe in this case an "AliasPredicate" method 4030// will need to be implemented. to allow it, as well as the more generally 4031// useful handling of non-register, non-constant operands. 4032class movalias<Instruction INST, RegisterClass GPR, Operand operand> 4033 : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>; 4034 4035def : movalias<MOVZwii, GPR32, movz32_movimm>; 4036def : movalias<MOVZxii, GPR64, movz64_movimm>; 4037def : movalias<MOVNwii, GPR32, movn32_movimm>; 4038def : movalias<MOVNxii, GPR64, movn64_movimm>; 4039 4040def movw_addressref_g0 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<0>">; 4041def movw_addressref_g1 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<1>">; 4042def movw_addressref_g2 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<2>">; 4043def movw_addressref_g3 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<3>">; 4044 4045def : Pat<(A64WrapperLarge movw_addressref_g3:$G3, movw_addressref_g2:$G2, 4046 movw_addressref_g1:$G1, movw_addressref_g0:$G0), 4047 (MOVKxii (MOVKxii (MOVKxii (MOVZxii movw_addressref_g3:$G3), 4048 movw_addressref_g2:$G2), 4049 movw_addressref_g1:$G1), 4050 movw_addressref_g0:$G0)>; 4051 4052//===----------------------------------------------------------------------===// 4053// PC-relative addressing instructions 4054//===----------------------------------------------------------------------===// 4055// Contains: ADR, ADRP 4056 4057def adr_label : Operand<i64> { 4058 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>"; 4059 4060 // This label is a 21-bit offset from PC, unscaled 4061 let PrintMethod = "printLabelOperand<21, 1>"; 4062 let ParserMatchClass = label_asmoperand<21, 1>; 4063 let OperandType = "OPERAND_PCREL"; 4064} 4065 4066def adrp_label_asmoperand : AsmOperandClass { 4067 let Name = "AdrpLabel"; 4068 let RenderMethod = "addLabelOperands<21, 4096>"; 4069 let DiagnosticType = "Label"; 4070} 4071 4072def adrp_label : Operand<i64> { 4073 let EncoderMethod = "getAdrpLabelOpValue"; 4074 4075 // This label is a 21-bit offset from PC, scaled by the page-size: 4096. 4076 let PrintMethod = "printLabelOperand<21, 4096>"; 4077 let ParserMatchClass = adrp_label_asmoperand; 4078 let OperandType = "OPERAND_PCREL"; 4079} 4080 4081let hasSideEffects = 0 in { 4082 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label), 4083 "adr\t$Rd, $Label", [], NoItinerary>; 4084 4085 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label), 4086 "adrp\t$Rd, $Label", [], NoItinerary>; 4087} 4088 4089//===----------------------------------------------------------------------===// 4090// System instructions 4091//===----------------------------------------------------------------------===// 4092// Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS 4093// + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL 4094 4095// Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values. 4096def uimm3_asmoperand : AsmOperandClass { 4097 let Name = "UImm3"; 4098 let PredicateMethod = "isUImm<3>"; 4099 let RenderMethod = "addImmOperands"; 4100 let DiagnosticType = "UImm3"; 4101} 4102 4103def uimm3 : Operand<i32> { 4104 let ParserMatchClass = uimm3_asmoperand; 4105} 4106 4107// The HINT alias can accept a simple unsigned 7-bit immediate. 4108def uimm7_asmoperand : AsmOperandClass { 4109 let Name = "UImm7"; 4110 let PredicateMethod = "isUImm<7>"; 4111 let RenderMethod = "addImmOperands"; 4112 let DiagnosticType = "UImm7"; 4113} 4114 4115def uimm7 : Operand<i32> { 4116 let ParserMatchClass = uimm7_asmoperand; 4117} 4118 4119// Multiclass namedimm is defined with the prefetch operands. Most of these fit 4120// into the NamedImmMapper scheme well: they either accept a named operand or 4121// any immediate under a particular value (which may be 0, implying no immediate 4122// is allowed). 4123defm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">; 4124defm isb : namedimm<"isb", "A64ISB::ISBMapper">; 4125defm ic : namedimm<"ic", "A64IC::ICMapper">; 4126defm dc : namedimm<"dc", "A64DC::DCMapper">; 4127defm at : namedimm<"at", "A64AT::ATMapper">; 4128defm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">; 4129 4130// However, MRS and MSR are more complicated for a few reasons: 4131// * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an 4132// implementation-defined effect 4133// * Most registers are shared, but some are read-only or write-only. 4134// * There is a variant of MSR which accepts the same register name (SPSel), 4135// but which would have a different encoding. 4136 4137// In principle these could be resolved in with more complicated subclasses of 4138// NamedImmMapper, however that imposes an overhead on other "named 4139// immediates". Both in concrete terms with virtual tables and in unnecessary 4140// abstraction. 4141 4142// The solution adopted here is to take the MRS/MSR Mappers out of the usual 4143// hierarchy (they're not derived from NamedImmMapper) and to add logic for 4144// their special situation. 4145def mrs_asmoperand : AsmOperandClass { 4146 let Name = "MRS"; 4147 let ParserMethod = "ParseSysRegOperand"; 4148 let DiagnosticType = "MRS"; 4149} 4150 4151def mrs_op : Operand<i32> { 4152 let ParserMatchClass = mrs_asmoperand; 4153 let PrintMethod = "printMRSOperand"; 4154 let DecoderMethod = "DecodeMRSOperand"; 4155} 4156 4157def msr_asmoperand : AsmOperandClass { 4158 let Name = "MSRWithReg"; 4159 4160 // Note that SPSel is valid for both this and the pstate operands, but with 4161 // different immediate encodings. This is why these operands provide a string 4162 // AArch64Operand rather than an immediate. The overlap is small enough that 4163 // it could be resolved with hackery now, but who can say in future? 4164 let ParserMethod = "ParseSysRegOperand"; 4165 let DiagnosticType = "MSR"; 4166} 4167 4168def msr_op : Operand<i32> { 4169 let ParserMatchClass = msr_asmoperand; 4170 let PrintMethod = "printMSROperand"; 4171 let DecoderMethod = "DecodeMSROperand"; 4172} 4173 4174def pstate_asmoperand : AsmOperandClass { 4175 let Name = "MSRPState"; 4176 // See comment above about parser. 4177 let ParserMethod = "ParseSysRegOperand"; 4178 let DiagnosticType = "MSR"; 4179} 4180 4181def pstate_op : Operand<i32> { 4182 let ParserMatchClass = pstate_asmoperand; 4183 let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>"; 4184 let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>"; 4185} 4186 4187// When <CRn> is specified, an assembler should accept something like "C4", not 4188// the usual "#4" immediate. 4189def CRx_asmoperand : AsmOperandClass { 4190 let Name = "CRx"; 4191 let PredicateMethod = "isUImm<4>"; 4192 let RenderMethod = "addImmOperands"; 4193 let ParserMethod = "ParseCRxOperand"; 4194 // Diagnostics are handled in all cases by ParseCRxOperand. 4195} 4196 4197def CRx : Operand<i32> { 4198 let ParserMatchClass = CRx_asmoperand; 4199 let PrintMethod = "printCRxOperand"; 4200} 4201 4202 4203// Finally, we can start defining the instructions. 4204 4205// HINT is straightforward, with a few aliases. 4206def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7", 4207 [], NoItinerary> { 4208 bits<7> UImm7; 4209 let CRm = UImm7{6-3}; 4210 let Op2 = UImm7{2-0}; 4211 4212 let Op0 = 0b00; 4213 let Op1 = 0b011; 4214 let CRn = 0b0010; 4215 let Rt = 0b11111; 4216} 4217 4218def : InstAlias<"nop", (HINTi 0)>; 4219def : InstAlias<"yield", (HINTi 1)>; 4220def : InstAlias<"wfe", (HINTi 2)>; 4221def : InstAlias<"wfi", (HINTi 3)>; 4222def : InstAlias<"sev", (HINTi 4)>; 4223def : InstAlias<"sevl", (HINTi 5)>; 4224 4225// Quite a few instructions then follow a similar pattern of fixing common 4226// fields in the bitpattern, we'll define a helper-class for them. 4227class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2, 4228 Operand operand, string asmop> 4229 : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"), 4230 [], NoItinerary> { 4231 let Op0 = op0; 4232 let Op1 = op1; 4233 let CRn = crn; 4234 let Op2 = op2; 4235 let Rt = 0b11111; 4236} 4237 4238 4239def CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">; 4240def DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">; 4241def DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">; 4242def ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">; 4243 4244def : InstAlias<"clrex", (CLREXi 0b1111)>; 4245def : InstAlias<"isb", (ISBi 0b1111)>; 4246 4247// (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP 4248// configurations at least. 4249def : Pat<(atomic_fence imm, imm), (DMBi 0xb)>; 4250 4251// Any SYS bitpattern can be represented with a complex and opaque "SYS" 4252// instruction. 4253def SYSiccix : A64I_system<0b0, (outs), 4254 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, 4255 uimm3:$Op2, GPR64:$Rt), 4256 "sys\t$Op1, $CRn, $CRm, $Op2, $Rt", 4257 [], NoItinerary> { 4258 let Op0 = 0b01; 4259} 4260 4261// You can skip the Xt argument whether it makes sense or not for the generic 4262// SYS instruction. 4263def : InstAlias<"sys $Op1, $CRn, $CRm, $Op2", 4264 (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>; 4265 4266 4267// But many have aliases, which obviously don't fit into 4268class SYSalias<dag ins, string asmstring> 4269 : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> { 4270 let isAsmParserOnly = 1; 4271 4272 bits<14> SysOp; 4273 let Op0 = 0b01; 4274 let Op1 = SysOp{13-11}; 4275 let CRn = SysOp{10-7}; 4276 let CRm = SysOp{6-3}; 4277 let Op2 = SysOp{2-0}; 4278} 4279 4280def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">; 4281 4282def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> { 4283 let Rt = 0b11111; 4284} 4285 4286def DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">; 4287def ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">; 4288 4289def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">; 4290 4291def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> { 4292 let Rt = 0b11111; 4293} 4294 4295 4296def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt), 4297 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2), 4298 "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2", 4299 [], NoItinerary> { 4300 let Op0 = 0b01; 4301} 4302 4303// The instructions themselves are rather simple for MSR and MRS. 4304def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt), 4305 "msr\t$SysReg, $Rt", [], NoItinerary> { 4306 bits<16> SysReg; 4307 let Op0 = SysReg{15-14}; 4308 let Op1 = SysReg{13-11}; 4309 let CRn = SysReg{10-7}; 4310 let CRm = SysReg{6-3}; 4311 let Op2 = SysReg{2-0}; 4312} 4313 4314def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg), 4315 "mrs\t$Rt, $SysReg", [], NoItinerary> { 4316 bits<16> SysReg; 4317 let Op0 = SysReg{15-14}; 4318 let Op1 = SysReg{13-11}; 4319 let CRn = SysReg{10-7}; 4320 let CRm = SysReg{6-3}; 4321 let Op2 = SysReg{2-0}; 4322} 4323 4324def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm), 4325 "msr\t$PState, $CRm", [], NoItinerary> { 4326 bits<6> PState; 4327 4328 let Op0 = 0b00; 4329 let Op1 = PState{5-3}; 4330 let CRn = 0b0100; 4331 let Op2 = PState{2-0}; 4332 let Rt = 0b11111; 4333} 4334 4335//===----------------------------------------------------------------------===// 4336// Test & branch (immediate) instructions 4337//===----------------------------------------------------------------------===// 4338// Contains: TBZ, TBNZ 4339 4340// The bit to test is a simple unsigned 6-bit immediate in the X-register 4341// versions. 4342def uimm6 : Operand<i64> { 4343 let ParserMatchClass = uimm6_asmoperand; 4344} 4345 4346def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>; 4347 4348def tbimm_target : Operand<OtherVT> { 4349 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>"; 4350 4351 // This label is a 14-bit offset from PC, scaled by the instruction-width: 4. 4352 let PrintMethod = "printLabelOperand<14, 4>"; 4353 let ParserMatchClass = label_wid14_scal4_asmoperand; 4354 4355 let OperandType = "OPERAND_PCREL"; 4356} 4357 4358def A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>; 4359def A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>; 4360 4361// These instructions correspond to patterns involving "and" with a power of 4362// two, which we need to be able to select. 4363def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">; 4364def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">; 4365 4366let isBranch = 1, isTerminator = 1 in { 4367 def TBZxii : A64I_TBimm<0b0, (outs), 4368 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label), 4369 "tbz\t$Rt, $Imm, $Label", 4370 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0), 4371 A64eq, bb:$Label)], 4372 NoItinerary>; 4373 4374 def TBNZxii : A64I_TBimm<0b1, (outs), 4375 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label), 4376 "tbnz\t$Rt, $Imm, $Label", 4377 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0), 4378 A64ne, bb:$Label)], 4379 NoItinerary>; 4380 4381 4382 // Note, these instructions overlap with the above 64-bit patterns. This is 4383 // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both 4384 // do the same thing and are both permitted assembly. They also both have 4385 // sensible DAG patterns. 4386 def TBZwii : A64I_TBimm<0b0, (outs), 4387 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label), 4388 "tbz\t$Rt, $Imm, $Label", 4389 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0), 4390 A64eq, bb:$Label)], 4391 NoItinerary> { 4392 let Imm{5} = 0b0; 4393 } 4394 4395 def TBNZwii : A64I_TBimm<0b1, (outs), 4396 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label), 4397 "tbnz\t$Rt, $Imm, $Label", 4398 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0), 4399 A64ne, bb:$Label)], 4400 NoItinerary> { 4401 let Imm{5} = 0b0; 4402 } 4403} 4404 4405//===----------------------------------------------------------------------===// 4406// Unconditional branch (immediate) instructions 4407//===----------------------------------------------------------------------===// 4408// Contains: B, BL 4409 4410def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>; 4411 4412def bimm_target : Operand<OtherVT> { 4413 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>"; 4414 4415 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4. 4416 let PrintMethod = "printLabelOperand<26, 4>"; 4417 let ParserMatchClass = label_wid26_scal4_asmoperand; 4418 4419 let OperandType = "OPERAND_PCREL"; 4420} 4421 4422def blimm_target : Operand<i64> { 4423 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>"; 4424 4425 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4. 4426 let PrintMethod = "printLabelOperand<26, 4>"; 4427 let ParserMatchClass = label_wid26_scal4_asmoperand; 4428 4429 let OperandType = "OPERAND_PCREL"; 4430} 4431 4432class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type> 4433 : A64I_Bimm<op, (outs), (ins lbl_type:$Label), 4434 !strconcat(asmop, "\t$Label"), patterns, 4435 NoItinerary>; 4436 4437let isBranch = 1 in { 4438 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> { 4439 let isTerminator = 1; 4440 let isBarrier = 1; 4441 } 4442 4443 def BLimm : A64I_BimmImpl<0b1, "bl", 4444 [(AArch64Call tglobaladdr:$Label)], blimm_target> { 4445 let isCall = 1; 4446 let Defs = [X30]; 4447 } 4448} 4449 4450def : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>; 4451 4452//===----------------------------------------------------------------------===// 4453// Unconditional branch (register) instructions 4454//===----------------------------------------------------------------------===// 4455// Contains: BR, BLR, RET, ERET, DRP. 4456 4457// Most of the notional opcode fields in the A64I_Breg format are fixed in A64 4458// at the moment. 4459class A64I_BregImpl<bits<4> opc, 4460 dag outs, dag ins, string asmstr, list<dag> patterns, 4461 InstrItinClass itin = NoItinerary> 4462 : A64I_Breg<opc, 0b11111, 0b000000, 0b00000, 4463 outs, ins, asmstr, patterns, itin> { 4464 let isBranch = 1; 4465 let isIndirectBranch = 1; 4466} 4467 4468// Note that these are not marked isCall or isReturn because as far as LLVM is 4469// concerned they're not. "ret" is just another jump unless it has been selected 4470// by LLVM as the function's return. 4471 4472let isBranch = 1 in { 4473 def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn), 4474 "br\t$Rn", [(brind i64:$Rn)]> { 4475 let isBarrier = 1; 4476 let isTerminator = 1; 4477 } 4478 4479 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn), 4480 "blr\t$Rn", [(AArch64Call i64:$Rn)]> { 4481 let isBarrier = 0; 4482 let isCall = 1; 4483 let Defs = [X30]; 4484 } 4485 4486 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn), 4487 "ret\t$Rn", []> { 4488 let isBarrier = 1; 4489 let isTerminator = 1; 4490 let isReturn = 1; 4491 } 4492 4493 // Create a separate pseudo-instruction for codegen to use so that we don't 4494 // flag x30 as used in every function. It'll be restored before the RET by the 4495 // epilogue if it's legitimately used. 4496 def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> { 4497 let isTerminator = 1; 4498 let isBarrier = 1; 4499 let isReturn = 1; 4500 } 4501 4502 def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> { 4503 let Rn = 0b11111; 4504 let isBarrier = 1; 4505 let isTerminator = 1; 4506 let isReturn = 1; 4507 } 4508 4509 def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> { 4510 let Rn = 0b11111; 4511 let isBarrier = 1; 4512 } 4513} 4514 4515def RETAlias : InstAlias<"ret", (RETx X30)>; 4516 4517 4518//===----------------------------------------------------------------------===// 4519// Address generation patterns 4520//===----------------------------------------------------------------------===// 4521 4522// Primary method of address generation for the small/absolute memory model is 4523// an ADRP/ADR pair: 4524// ADRP x0, some_variable 4525// ADD x0, x0, #:lo12:some_variable 4526// 4527// The load/store elision of the ADD is accomplished when selecting 4528// addressing-modes. This just mops up the cases where that doesn't work and we 4529// really need an address in some register. 4530 4531// This wrapper applies a LO12 modifier to the address. Otherwise we could just 4532// use the same address. 4533 4534class ADRP_ADD<SDNode Wrapper, SDNode addrop> 4535 : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)), 4536 (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>; 4537 4538def : ADRP_ADD<A64WrapperSmall, tblockaddress>; 4539def : ADRP_ADD<A64WrapperSmall, texternalsym>; 4540def : ADRP_ADD<A64WrapperSmall, tglobaladdr>; 4541def : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>; 4542def : ADRP_ADD<A64WrapperSmall, tjumptable>; 4543 4544//===----------------------------------------------------------------------===// 4545// GOT access patterns 4546//===----------------------------------------------------------------------===// 4547 4548class GOTLoadSmall<SDNode addrfrag> 4549 : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)), 4550 (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>; 4551 4552def : GOTLoadSmall<texternalsym>; 4553def : GOTLoadSmall<tglobaladdr>; 4554def : GOTLoadSmall<tglobaltlsaddr>; 4555 4556//===----------------------------------------------------------------------===// 4557// Tail call handling 4558//===----------------------------------------------------------------------===// 4559 4560let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in { 4561 def TC_RETURNdi 4562 : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff), 4563 [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>; 4564 4565 def TC_RETURNxi 4566 : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), 4567 [(AArch64tcret i64:$dst, (i32 timm:$FPDiff))]>; 4568} 4569 4570let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 4571 Uses = [XSP] in { 4572 def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [], 4573 (Bimm bimm_target:$Label)>; 4574 4575 def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [], 4576 (BRx GPR64:$Rd)>; 4577} 4578 4579 4580def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)), 4581 (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>; 4582 4583//===----------------------------------------------------------------------===// 4584// Thread local storage 4585//===----------------------------------------------------------------------===// 4586 4587// This is a pseudo-instruction representing the ".tlsdesccall" directive in 4588// assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the 4589// current location. It should always be immediately followed by a BLR 4590// instruction, and is intended solely for relaxation by the linker. 4591 4592def : Pat<(A64threadpointer), (MRSxi 0xde82)>; 4593 4594def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> { 4595 let hasSideEffects = 1; 4596} 4597 4598def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var), 4599 [(A64tlsdesc_blr i64:$Rn, tglobaltlsaddr:$Var)]> { 4600 let isCall = 1; 4601 let Defs = [X30]; 4602} 4603 4604def : Pat<(A64tlsdesc_blr i64:$Rn, texternalsym:$Var), 4605 (TLSDESC_BLRx $Rn, texternalsym:$Var)>; 4606 4607//===----------------------------------------------------------------------===// 4608// Bitfield patterns 4609//===----------------------------------------------------------------------===// 4610 4611def bfi32_lsb_to_immr : SDNodeXForm<imm, [{ 4612 return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64); 4613}]>; 4614 4615def bfi64_lsb_to_immr : SDNodeXForm<imm, [{ 4616 return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64); 4617}]>; 4618 4619def bfi_width_to_imms : SDNodeXForm<imm, [{ 4620 return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64); 4621}]>; 4622 4623 4624// The simpler patterns deal with cases where no AND mask is actually needed 4625// (either all bits are used or the low 32 bits are used). 4626let AddedComplexity = 10 in { 4627 4628def : Pat<(A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS), 4629 (BFIxxii $src, $Rn, 4630 (bfi64_lsb_to_immr (i64 imm:$ImmR)), 4631 (bfi_width_to_imms (i64 imm:$ImmS)))>; 4632 4633def : Pat<(A64Bfi i32:$src, i32:$Rn, imm:$ImmR, imm:$ImmS), 4634 (BFIwwii $src, $Rn, 4635 (bfi32_lsb_to_immr (i64 imm:$ImmR)), 4636 (bfi_width_to_imms (i64 imm:$ImmS)))>; 4637 4638 4639def : Pat<(and (A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS), 4640 (i64 4294967295)), 4641 (SUBREG_TO_REG (i64 0), 4642 (BFIwwii (EXTRACT_SUBREG $src, sub_32), 4643 (EXTRACT_SUBREG $Rn, sub_32), 4644 (bfi32_lsb_to_immr (i64 imm:$ImmR)), 4645 (bfi_width_to_imms (i64 imm:$ImmS))), 4646 sub_32)>; 4647 4648} 4649 4650//===----------------------------------------------------------------------===// 4651// Miscellaneous patterns 4652//===----------------------------------------------------------------------===// 4653 4654// Truncation from 64 to 32-bits just involves renaming your register. 4655def : Pat<(i32 (trunc i64:$val)), (EXTRACT_SUBREG $val, sub_32)>; 4656 4657// Similarly, extension where we don't care about the high bits is 4658// just a rename. 4659def : Pat<(i64 (anyext i32:$val)), 4660 (INSERT_SUBREG (IMPLICIT_DEF), $val, sub_32)>; 4661 4662// SELECT instructions providing f128 types need to be handled by a 4663// pseudo-instruction since the eventual code will need to introduce basic 4664// blocks and control flow. 4665def F128CSEL : PseudoInst<(outs FPR128:$Rd), 4666 (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond), 4667 [(set f128:$Rd, (simple_select f128:$Rn, f128:$Rm))]> { 4668 let Uses = [NZCV]; 4669 let usesCustomInserter = 1; 4670} 4671 4672//===----------------------------------------------------------------------===// 4673// Load/store patterns 4674//===----------------------------------------------------------------------===// 4675 4676// There are lots of patterns here, because we need to allow at least three 4677// parameters to vary independently. 4678// 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ... 4679// 2. LLVM source: zextloadi8, anyextloadi8, ... 4680// 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ... 4681// 4682// The biggest problem turns out to be the address-generation variable. At the 4683// point of instantiation we need to produce two DAGs, one for the pattern and 4684// one for the instruction. Doing this at the lowest level of classes doesn't 4685// work. 4686// 4687// Consider the simple uimm12 addressing mode, and the desire to match both (add 4688// GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the 4689// instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or 4690// "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this 4691// operation, and PatFrags are for selection not output. 4692// 4693// As a result, the address-generation patterns are the final 4694// instantiations. However, we do still need to vary the operand for the address 4695// further down (At the point we're deciding A64WrapperSmall, we don't know 4696// the memory width of the operation). 4697 4698//===------------------------------ 4699// 1. Basic infrastructural defs 4700//===------------------------------ 4701 4702// First, some simple classes for !foreach and !subst to use: 4703class Decls { 4704 dag pattern; 4705} 4706 4707def decls : Decls; 4708def ALIGN; 4709def INST; 4710def OFFSET; 4711def SHIFT; 4712 4713// You can't use !subst on an actual immediate, but you *can* use it on an 4714// operand record that happens to match a single immediate. So we do. 4715def imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>; 4716def imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>; 4717def imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>; 4718def imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>; 4719def imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>; 4720 4721// If the low bits of a pointer are known to be 0 then an "or" is just as good 4722// as addition for computing an offset. This fragment forwards that check for 4723// TableGen's use. 4724def add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs), 4725[{ 4726 return CurDAG->isBaseWithConstantOffset(SDValue(N, 0)); 4727}]>; 4728 4729// Load/store (unsigned immediate) operations with relocations against global 4730// symbols (for lo12) are only valid if those symbols have correct alignment 4731// (since the immediate offset is divided by the access scale, it can't have a 4732// remainder). 4733// 4734// The guaranteed alignment is provided as part of the WrapperSmall 4735// operation, and checked against one of these. 4736def any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>; 4737def min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>; 4738def min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>; 4739def min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>; 4740def min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>; 4741 4742// "Normal" load/store instructions can be used on atomic operations, provided 4743// the ordering parameter is at most "monotonic". Anything above that needs 4744// special handling with acquire/release instructions. 4745class simple_load<PatFrag base> 4746 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4747 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic; 4748}]>; 4749 4750def atomic_load_simple_i8 : simple_load<atomic_load_8>; 4751def atomic_load_simple_i16 : simple_load<atomic_load_16>; 4752def atomic_load_simple_i32 : simple_load<atomic_load_32>; 4753def atomic_load_simple_i64 : simple_load<atomic_load_64>; 4754 4755class simple_store<PatFrag base> 4756 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4757 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic; 4758}]>; 4759 4760def atomic_store_simple_i8 : simple_store<atomic_store_8>; 4761def atomic_store_simple_i16 : simple_store<atomic_store_16>; 4762def atomic_store_simple_i32 : simple_store<atomic_store_32>; 4763def atomic_store_simple_i64 : simple_store<atomic_store_64>; 4764 4765//===------------------------------ 4766// 2. UImm12 and SImm9 4767//===------------------------------ 4768 4769// These instructions have two operands providing the address so they can be 4770// treated similarly for most purposes. 4771 4772//===------------------------------ 4773// 2.1 Base patterns covering extend/truncate semantics 4774//===------------------------------ 4775 4776// Atomic patterns can be shared between integer operations of all sizes, a 4777// quick multiclass here allows reuse. 4778multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base, 4779 dag Offset, dag address, ValueType transty, 4780 ValueType sty> { 4781 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address), 4782 (LOAD Base, Offset)>; 4783 4784 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt), 4785 (STORE $Rt, Base, Offset)>; 4786} 4787 4788// Instructions accessing a memory chunk smaller than a register (or, in a 4789// pinch, the same size) have a characteristic set of patterns they want to 4790// match: extending loads and truncating stores. This class deals with the 4791// sign-neutral version of those patterns. 4792// 4793// It will be instantiated across multiple addressing-modes. 4794multiclass ls_small_pats<Instruction LOAD, Instruction STORE, 4795 dag Base, dag Offset, 4796 dag address, ValueType sty> 4797 : ls_atomic_pats<LOAD, STORE, Base, Offset, address, i32, sty> { 4798 def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>; 4799 4800 def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>; 4801 4802 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit 4803 // register was actually set. 4804 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)), 4805 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>; 4806 4807 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)), 4808 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>; 4809 4810 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address), 4811 (STORE $Rt, Base, Offset)>; 4812 4813 // For truncating store from 64-bits, we have to manually tell LLVM to 4814 // ignore the high bits of the x register. 4815 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address), 4816 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>; 4817} 4818 4819// Next come patterns for sign-extending loads. 4820multiclass load_signed_pats<string T, string U, dag Base, dag Offset, 4821 dag address, ValueType sty> { 4822 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)), 4823 (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>; 4824 4825 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)), 4826 (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>; 4827 4828} 4829 4830// and finally "natural-width" loads and stores come next. 4831multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base, 4832 dag Offset, dag address, ValueType sty> { 4833 def : Pat<(sty (load address)), (LOAD Base, Offset)>; 4834 def : Pat<(store sty:$Rt, address), (STORE $Rt, Base, Offset)>; 4835} 4836 4837// Integer operations also get atomic instructions to select for. 4838multiclass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base, 4839 dag Offset, dag address, ValueType sty> 4840 : ls_neutral_pats<LOAD, STORE, Base, Offset, address, sty>, 4841 ls_atomic_pats<LOAD, STORE, Base, Offset, address, sty, sty>; 4842 4843//===------------------------------ 4844// 2.2. Addressing-mode instantiations 4845//===------------------------------ 4846 4847multiclass uimm12_pats<dag address, dag Base, dag Offset> { 4848 defm : ls_small_pats<LS8_LDR, LS8_STR, Base, 4849 !foreach(decls.pattern, Offset, 4850 !subst(OFFSET, byte_uimm12, decls.pattern)), 4851 !foreach(decls.pattern, address, 4852 !subst(OFFSET, byte_uimm12, 4853 !subst(ALIGN, any_align, decls.pattern))), 4854 i8>; 4855 defm : ls_small_pats<LS16_LDR, LS16_STR, Base, 4856 !foreach(decls.pattern, Offset, 4857 !subst(OFFSET, hword_uimm12, decls.pattern)), 4858 !foreach(decls.pattern, address, 4859 !subst(OFFSET, hword_uimm12, 4860 !subst(ALIGN, min_align2, decls.pattern))), 4861 i16>; 4862 defm : ls_small_pats<LS32_LDR, LS32_STR, Base, 4863 !foreach(decls.pattern, Offset, 4864 !subst(OFFSET, word_uimm12, decls.pattern)), 4865 !foreach(decls.pattern, address, 4866 !subst(OFFSET, word_uimm12, 4867 !subst(ALIGN, min_align4, decls.pattern))), 4868 i32>; 4869 4870 defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base, 4871 !foreach(decls.pattern, Offset, 4872 !subst(OFFSET, word_uimm12, decls.pattern)), 4873 !foreach(decls.pattern, address, 4874 !subst(OFFSET, word_uimm12, 4875 !subst(ALIGN, min_align4, decls.pattern))), 4876 i32>; 4877 4878 defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base, 4879 !foreach(decls.pattern, Offset, 4880 !subst(OFFSET, dword_uimm12, decls.pattern)), 4881 !foreach(decls.pattern, address, 4882 !subst(OFFSET, dword_uimm12, 4883 !subst(ALIGN, min_align8, decls.pattern))), 4884 i64>; 4885 4886 defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base, 4887 !foreach(decls.pattern, Offset, 4888 !subst(OFFSET, hword_uimm12, decls.pattern)), 4889 !foreach(decls.pattern, address, 4890 !subst(OFFSET, hword_uimm12, 4891 !subst(ALIGN, min_align2, decls.pattern))), 4892 f16>; 4893 4894 defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base, 4895 !foreach(decls.pattern, Offset, 4896 !subst(OFFSET, word_uimm12, decls.pattern)), 4897 !foreach(decls.pattern, address, 4898 !subst(OFFSET, word_uimm12, 4899 !subst(ALIGN, min_align4, decls.pattern))), 4900 f32>; 4901 4902 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base, 4903 !foreach(decls.pattern, Offset, 4904 !subst(OFFSET, dword_uimm12, decls.pattern)), 4905 !foreach(decls.pattern, address, 4906 !subst(OFFSET, dword_uimm12, 4907 !subst(ALIGN, min_align8, decls.pattern))), 4908 f64>; 4909 4910 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base, 4911 !foreach(decls.pattern, Offset, 4912 !subst(OFFSET, qword_uimm12, decls.pattern)), 4913 !foreach(decls.pattern, address, 4914 !subst(OFFSET, qword_uimm12, 4915 !subst(ALIGN, min_align16, decls.pattern))), 4916 f128>; 4917 4918 defm : load_signed_pats<"B", "", Base, 4919 !foreach(decls.pattern, Offset, 4920 !subst(OFFSET, byte_uimm12, decls.pattern)), 4921 !foreach(decls.pattern, address, 4922 !subst(OFFSET, byte_uimm12, 4923 !subst(ALIGN, any_align, decls.pattern))), 4924 i8>; 4925 4926 defm : load_signed_pats<"H", "", Base, 4927 !foreach(decls.pattern, Offset, 4928 !subst(OFFSET, hword_uimm12, decls.pattern)), 4929 !foreach(decls.pattern, address, 4930 !subst(OFFSET, hword_uimm12, 4931 !subst(ALIGN, min_align2, decls.pattern))), 4932 i16>; 4933 4934 def : Pat<(sextloadi32 !foreach(decls.pattern, address, 4935 !subst(OFFSET, word_uimm12, 4936 !subst(ALIGN, min_align4, decls.pattern)))), 4937 (LDRSWx Base, !foreach(decls.pattern, Offset, 4938 !subst(OFFSET, word_uimm12, decls.pattern)))>; 4939} 4940 4941// Straightforward patterns of last resort: a pointer with or without an 4942// appropriate offset. 4943defm : uimm12_pats<(i64 i64:$Rn), (i64 i64:$Rn), (i64 0)>; 4944defm : uimm12_pats<(add i64:$Rn, OFFSET:$UImm12), 4945 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>; 4946 4947// The offset could be hidden behind an "or", of course: 4948defm : uimm12_pats<(add_like_or i64:$Rn, OFFSET:$UImm12), 4949 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>; 4950 4951// Global addresses under the small-absolute model should use these 4952// instructions. There are ELF relocations specifically for it. 4953defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN), 4954 (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>; 4955 4956defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12, 4957 ALIGN), 4958 (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>; 4959 4960// External symbols that make it this far should also get standard relocations. 4961defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12, 4962 ALIGN), 4963 (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>; 4964 4965defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN), 4966 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>; 4967 4968// We also want to use uimm12 instructions for local variables at the moment. 4969def tframeindex_XFORM : SDNodeXForm<frameindex, [{ 4970 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 4971 return CurDAG->getTargetFrameIndex(FI, MVT::i64); 4972}]>; 4973 4974defm : uimm12_pats<(i64 frameindex:$Rn), 4975 (tframeindex_XFORM tframeindex:$Rn), (i64 0)>; 4976 4977// These can be much simpler than uimm12 because we don't to change the operand 4978// type (e.g. LDURB and LDURH take the same operands). 4979multiclass simm9_pats<dag address, dag Base, dag Offset> { 4980 defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>; 4981 defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>; 4982 4983 defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address, i32>; 4984 defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address, i64>; 4985 4986 defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address, f16>; 4987 defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address, f32>; 4988 defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address, f64>; 4989 defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address, 4990 f128>; 4991 4992 def : Pat<(i64 (zextloadi32 address)), 4993 (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>; 4994 4995 def : Pat<(truncstorei32 i64:$Rt, address), 4996 (LS32_STUR (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>; 4997 4998 defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>; 4999 defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>; 5000 def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>; 5001} 5002 5003defm : simm9_pats<(add i64:$Rn, simm9:$SImm9), 5004 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>; 5005 5006defm : simm9_pats<(add_like_or i64:$Rn, simm9:$SImm9), 5007 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>; 5008 5009 5010//===------------------------------ 5011// 3. Register offset patterns 5012//===------------------------------ 5013 5014// Atomic patterns can be shared between integer operations of all sizes, a 5015// quick multiclass here allows reuse. 5016multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base, 5017 dag Offset, dag Extend, dag address, 5018 ValueType transty, ValueType sty> { 5019 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address), 5020 (LOAD Base, Offset, Extend)>; 5021 5022 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt), 5023 (STORE $Rt, Base, Offset, Extend)>; 5024} 5025 5026// The register offset instructions take three operands giving the instruction, 5027// and have an annoying split between instructions where Rm is 32-bit and 5028// 64-bit. So we need a special hierarchy to describe them. Other than that the 5029// same operations should be supported as for simm9 and uimm12 addressing. 5030 5031multiclass ro_small_pats<Instruction LOAD, Instruction STORE, 5032 dag Base, dag Offset, dag Extend, 5033 dag address, ValueType sty> 5034 : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, i32, sty> { 5035 def : Pat<(!cast<SDNode>(zextload # sty) address), 5036 (LOAD Base, Offset, Extend)>; 5037 5038 def : Pat<(!cast<SDNode>(extload # sty) address), 5039 (LOAD Base, Offset, Extend)>; 5040 5041 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit 5042 // register was actually set. 5043 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)), 5044 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>; 5045 5046 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)), 5047 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>; 5048 5049 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address), 5050 (STORE $Rt, Base, Offset, Extend)>; 5051 5052 // For truncating store from 64-bits, we have to manually tell LLVM to 5053 // ignore the high bits of the x register. 5054 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address), 5055 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset, Extend)>; 5056 5057} 5058 5059// Next come patterns for sign-extending loads. 5060multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend, 5061 dag address, ValueType sty> { 5062 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)), 5063 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset") 5064 Base, Offset, Extend)>; 5065 5066 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)), 5067 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset") 5068 Base, Offset, Extend)>; 5069} 5070 5071// and finally "natural-width" loads and stores come next. 5072multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE, 5073 dag Base, dag Offset, dag Extend, dag address, 5074 ValueType sty> { 5075 def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>; 5076 def : Pat<(store sty:$Rt, address), 5077 (STORE $Rt, Base, Offset, Extend)>; 5078} 5079 5080multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE, 5081 dag Base, dag Offset, dag Extend, dag address, 5082 ValueType sty> 5083 : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, sty>, 5084 ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, sty, sty>; 5085 5086multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset, 5087 dag Extend> { 5088 defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"), 5089 !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"), 5090 Base, Offset, Extend, 5091 !foreach(decls.pattern, address, 5092 !subst(SHIFT, imm_eq0, decls.pattern)), 5093 i8>; 5094 defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"), 5095 !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"), 5096 Base, Offset, Extend, 5097 !foreach(decls.pattern, address, 5098 !subst(SHIFT, imm_eq1, decls.pattern)), 5099 i16>; 5100 defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"), 5101 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"), 5102 Base, Offset, Extend, 5103 !foreach(decls.pattern, address, 5104 !subst(SHIFT, imm_eq2, decls.pattern)), 5105 i32>; 5106 5107 defm : ro_int_neutral_pats< 5108 !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"), 5109 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"), 5110 Base, Offset, Extend, 5111 !foreach(decls.pattern, address, 5112 !subst(SHIFT, imm_eq2, decls.pattern)), 5113 i32>; 5114 5115 defm : ro_int_neutral_pats< 5116 !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"), 5117 !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"), 5118 Base, Offset, Extend, 5119 !foreach(decls.pattern, address, 5120 !subst(SHIFT, imm_eq3, decls.pattern)), 5121 i64>; 5122 5123 defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"), 5124 !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"), 5125 Base, Offset, Extend, 5126 !foreach(decls.pattern, address, 5127 !subst(SHIFT, imm_eq1, decls.pattern)), 5128 f16>; 5129 5130 defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"), 5131 !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"), 5132 Base, Offset, Extend, 5133 !foreach(decls.pattern, address, 5134 !subst(SHIFT, imm_eq2, decls.pattern)), 5135 f32>; 5136 5137 defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"), 5138 !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"), 5139 Base, Offset, Extend, 5140 !foreach(decls.pattern, address, 5141 !subst(SHIFT, imm_eq3, decls.pattern)), 5142 f64>; 5143 5144 defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"), 5145 !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"), 5146 Base, Offset, Extend, 5147 !foreach(decls.pattern, address, 5148 !subst(SHIFT, imm_eq4, decls.pattern)), 5149 f128>; 5150 5151 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend, 5152 !foreach(decls.pattern, address, 5153 !subst(SHIFT, imm_eq0, decls.pattern)), 5154 i8>; 5155 5156 defm : ro_signed_pats<"H", Rm, Base, Offset, Extend, 5157 !foreach(decls.pattern, address, 5158 !subst(SHIFT, imm_eq1, decls.pattern)), 5159 i16>; 5160 5161 def : Pat<(sextloadi32 !foreach(decls.pattern, address, 5162 !subst(SHIFT, imm_eq2, decls.pattern))), 5163 (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset") 5164 Base, Offset, Extend)>; 5165} 5166 5167 5168// Finally we're in a position to tell LLVM exactly what addresses are reachable 5169// using register-offset instructions. Essentially a base plus a possibly 5170// extended, possibly shifted (by access size) offset. 5171 5172defm : regoff_pats<"Wm", (add i64:$Rn, (sext i32:$Rm)), 5173 (i64 i64:$Rn), (i32 i32:$Rm), (i64 6)>; 5174 5175defm : regoff_pats<"Wm", (add i64:$Rn, (shl (sext i32:$Rm), SHIFT)), 5176 (i64 i64:$Rn), (i32 i32:$Rm), (i64 7)>; 5177 5178defm : regoff_pats<"Wm", (add i64:$Rn, (zext i32:$Rm)), 5179 (i64 i64:$Rn), (i32 i32:$Rm), (i64 2)>; 5180 5181defm : regoff_pats<"Wm", (add i64:$Rn, (shl (zext i32:$Rm), SHIFT)), 5182 (i64 i64:$Rn), (i32 i32:$Rm), (i64 3)>; 5183 5184defm : regoff_pats<"Xm", (add i64:$Rn, i64:$Rm), 5185 (i64 i64:$Rn), (i64 i64:$Rm), (i64 2)>; 5186 5187defm : regoff_pats<"Xm", (add i64:$Rn, (shl i64:$Rm, SHIFT)), 5188 (i64 i64:$Rn), (i64 i64:$Rm), (i64 3)>; 5189 5190//===----------------------------------------------------------------------===// 5191// Advanced SIMD (NEON) Support 5192// 5193 5194include "AArch64InstrNEON.td" 5195