Disassembler.cpp revision 263508
1//===-- lib/MC/Disassembler.cpp - Disassembler Public C Interface ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "Disassembler.h" 11#include "llvm-c/Disassembler.h" 12#include "llvm/MC/MCAsmInfo.h" 13#include "llvm/MC/MCContext.h" 14#include "llvm/MC/MCDisassembler.h" 15#include "llvm/MC/MCInst.h" 16#include "llvm/MC/MCInstPrinter.h" 17#include "llvm/MC/MCInstrInfo.h" 18#include "llvm/MC/MCRegisterInfo.h" 19#include "llvm/MC/MCRelocationInfo.h" 20#include "llvm/MC/MCSubtargetInfo.h" 21#include "llvm/MC/MCSymbolizer.h" 22#include "llvm/Support/ErrorHandling.h" 23#include "llvm/Support/FormattedStream.h" 24#include "llvm/Support/MemoryObject.h" 25#include "llvm/Support/TargetRegistry.h" 26 27namespace llvm { 28class Target; 29} // namespace llvm 30using namespace llvm; 31 32// LLVMCreateDisasm() creates a disassembler for the TripleName. Symbolic 33// disassembly is supported by passing a block of information in the DisInfo 34// parameter and specifying the TagType and callback functions as described in 35// the header llvm-c/Disassembler.h . The pointer to the block and the 36// functions can all be passed as NULL. If successful, this returns a 37// disassembler context. If not, it returns NULL. 38// 39LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *Triple, const char *CPU, 40 void *DisInfo, int TagType, 41 LLVMOpInfoCallback GetOpInfo, 42 LLVMSymbolLookupCallback SymbolLookUp){ 43 // Get the target. 44 std::string Error; 45 const Target *TheTarget = TargetRegistry::lookupTarget(Triple, Error); 46 if (!TheTarget) 47 return 0; 48 49 const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple); 50 if (!MRI) 51 return 0; 52 53 // Get the assembler info needed to setup the MCContext. 54 const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, Triple); 55 if (!MAI) 56 return 0; 57 58 const MCInstrInfo *MII = TheTarget->createMCInstrInfo(); 59 if (!MII) 60 return 0; 61 62 // Package up features to be passed to target/subtarget 63 std::string FeaturesStr; 64 65 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU, 66 FeaturesStr); 67 if (!STI) 68 return 0; 69 70 // Set up the MCContext for creating symbols and MCExpr's. 71 MCContext *Ctx = new MCContext(MAI, MRI, 0); 72 if (!Ctx) 73 return 0; 74 75 // Set up disassembler. 76 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI); 77 if (!DisAsm) 78 return 0; 79 80 OwningPtr<MCRelocationInfo> RelInfo( 81 TheTarget->createMCRelocationInfo(Triple, *Ctx)); 82 if (!RelInfo) 83 return 0; 84 85 OwningPtr<MCSymbolizer> Symbolizer( 86 TheTarget->createMCSymbolizer(Triple, GetOpInfo, SymbolLookUp, DisInfo, 87 Ctx, RelInfo.take())); 88 DisAsm->setSymbolizer(Symbolizer); 89 DisAsm->setupForSymbolicDisassembly(GetOpInfo, SymbolLookUp, DisInfo, 90 Ctx, RelInfo); 91 // Set up the instruction printer. 92 int AsmPrinterVariant = MAI->getAssemblerDialect(); 93 MCInstPrinter *IP = TheTarget->createMCInstPrinter(AsmPrinterVariant, 94 *MAI, *MII, *MRI, *STI); 95 if (!IP) 96 return 0; 97 98 LLVMDisasmContext *DC = new LLVMDisasmContext(Triple, DisInfo, TagType, 99 GetOpInfo, SymbolLookUp, 100 TheTarget, MAI, MRI, 101 STI, MII, Ctx, DisAsm, IP); 102 if (!DC) 103 return 0; 104 105 DC->setCPU(CPU); 106 return DC; 107} 108 109LLVMDisasmContextRef LLVMCreateDisasm(const char *Triple, void *DisInfo, 110 int TagType, LLVMOpInfoCallback GetOpInfo, 111 LLVMSymbolLookupCallback SymbolLookUp) { 112 return LLVMCreateDisasmCPU(Triple, "", DisInfo, TagType, GetOpInfo, 113 SymbolLookUp); 114} 115 116// 117// LLVMDisasmDispose() disposes of the disassembler specified by the context. 118// 119void LLVMDisasmDispose(LLVMDisasmContextRef DCR){ 120 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR; 121 delete DC; 122} 123 124namespace { 125// 126// The memory object created by LLVMDisasmInstruction(). 127// 128class DisasmMemoryObject : public MemoryObject { 129 uint8_t *Bytes; 130 uint64_t Size; 131 uint64_t BasePC; 132public: 133 DisasmMemoryObject(uint8_t *bytes, uint64_t size, uint64_t basePC) : 134 Bytes(bytes), Size(size), BasePC(basePC) {} 135 136 uint64_t getBase() const { return BasePC; } 137 uint64_t getExtent() const { return Size; } 138 139 int readByte(uint64_t Addr, uint8_t *Byte) const { 140 if (Addr - BasePC >= Size) 141 return -1; 142 *Byte = Bytes[Addr - BasePC]; 143 return 0; 144 } 145}; 146} // end anonymous namespace 147 148/// \brief Emits the comments that are stored in \p DC comment stream. 149/// Each comment in the comment stream must end with a newline. 150static void emitComments(LLVMDisasmContext *DC, 151 formatted_raw_ostream &FormattedOS) { 152 // Flush the stream before taking its content. 153 DC->CommentStream.flush(); 154 StringRef Comments = DC->CommentsToEmit.str(); 155 // Get the default information for printing a comment. 156 const MCAsmInfo *MAI = DC->getAsmInfo(); 157 const char *CommentBegin = MAI->getCommentString(); 158 unsigned CommentColumn = MAI->getCommentColumn(); 159 bool IsFirst = true; 160 while (!Comments.empty()) { 161 if (!IsFirst) 162 FormattedOS << '\n'; 163 // Emit a line of comments. 164 FormattedOS.PadToColumn(CommentColumn); 165 size_t Position = Comments.find('\n'); 166 FormattedOS << CommentBegin << ' ' << Comments.substr(0, Position); 167 // Move after the newline character. 168 Comments = Comments.substr(Position+1); 169 IsFirst = false; 170 } 171 FormattedOS.flush(); 172 173 // Tell the comment stream that the vector changed underneath it. 174 DC->CommentsToEmit.clear(); 175 DC->CommentStream.resync(); 176} 177 178/// \brief Gets latency information for \p Inst form the itinerary 179/// scheduling model, based on \p DC information. 180/// \return The maximum expected latency over all the operands or -1 181/// if no information are available. 182static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) { 183 const int NoInformationAvailable = -1; 184 185 // Check if we have a CPU to get the itinerary information. 186 if (DC->getCPU().empty()) 187 return NoInformationAvailable; 188 189 // Get itinerary information. 190 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); 191 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU()); 192 // Get the scheduling class of the requested instruction. 193 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode()); 194 unsigned SCClass = Desc.getSchedClass(); 195 196 int Latency = 0; 197 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd; 198 ++OpIdx) 199 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx)); 200 201 return Latency; 202} 203 204/// \brief Gets latency information for \p Inst, based on \p DC information. 205/// \return The maximum expected latency over all the definitions or -1 206/// if no information are available. 207static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) { 208 // Try to compute scheduling information. 209 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); 210 const MCSchedModel *SCModel = STI->getSchedModel(); 211 const int NoInformationAvailable = -1; 212 213 // Check if we have a scheduling model for instructions. 214 if (!SCModel || !SCModel->hasInstrSchedModel()) 215 // Try to fall back to the itinerary model if we do not have a 216 // scheduling model. 217 return getItineraryLatency(DC, Inst); 218 219 // Get the scheduling class of the requested instruction. 220 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode()); 221 unsigned SCClass = Desc.getSchedClass(); 222 const MCSchedClassDesc *SCDesc = SCModel->getSchedClassDesc(SCClass); 223 // Resolving the variant SchedClass requires an MI to pass to 224 // SubTargetInfo::resolveSchedClass. 225 if (!SCDesc || !SCDesc->isValid() || SCDesc->isVariant()) 226 return NoInformationAvailable; 227 228 // Compute output latency. 229 int Latency = 0; 230 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; 231 DefIdx != DefEnd; ++DefIdx) { 232 // Lookup the definition's write latency in SubtargetInfo. 233 const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc, 234 DefIdx); 235 Latency = std::max(Latency, WLEntry->Cycles); 236 } 237 238 return Latency; 239} 240 241 242/// \brief Emits latency information in DC->CommentStream for \p Inst, based 243/// on the information available in \p DC. 244static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) { 245 int Latency = getLatency(DC, Inst); 246 247 // Report only interesting latency. 248 if (Latency < 2) 249 return; 250 251 DC->CommentStream << "Latency: " << Latency << '\n'; 252} 253 254// 255// LLVMDisasmInstruction() disassembles a single instruction using the 256// disassembler context specified in the parameter DC. The bytes of the 257// instruction are specified in the parameter Bytes, and contains at least 258// BytesSize number of bytes. The instruction is at the address specified by 259// the PC parameter. If a valid instruction can be disassembled its string is 260// returned indirectly in OutString which whos size is specified in the 261// parameter OutStringSize. This function returns the number of bytes in the 262// instruction or zero if there was no valid instruction. If this function 263// returns zero the caller will have to pick how many bytes they want to step 264// over by printing a .byte, .long etc. to continue. 265// 266size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes, 267 uint64_t BytesSize, uint64_t PC, char *OutString, 268 size_t OutStringSize){ 269 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR; 270 // Wrap the pointer to the Bytes, BytesSize and PC in a MemoryObject. 271 DisasmMemoryObject MemoryObject(Bytes, BytesSize, PC); 272 273 uint64_t Size; 274 MCInst Inst; 275 const MCDisassembler *DisAsm = DC->getDisAsm(); 276 MCInstPrinter *IP = DC->getIP(); 277 MCDisassembler::DecodeStatus S; 278 SmallVector<char, 64> InsnStr; 279 raw_svector_ostream Annotations(InsnStr); 280 S = DisAsm->getInstruction(Inst, Size, MemoryObject, PC, 281 /*REMOVE*/ nulls(), Annotations); 282 switch (S) { 283 case MCDisassembler::Fail: 284 case MCDisassembler::SoftFail: 285 // FIXME: Do something different for soft failure modes? 286 return 0; 287 288 case MCDisassembler::Success: { 289 Annotations.flush(); 290 StringRef AnnotationsStr = Annotations.str(); 291 292 SmallVector<char, 64> InsnStr; 293 raw_svector_ostream OS(InsnStr); 294 formatted_raw_ostream FormattedOS(OS); 295 IP->printInst(&Inst, FormattedOS, AnnotationsStr); 296 297 if (DC->getOptions() & LLVMDisassembler_Option_PrintLatency) 298 emitLatency(DC, Inst); 299 300 emitComments(DC, FormattedOS); 301 302 assert(OutStringSize != 0 && "Output buffer cannot be zero size"); 303 size_t OutputSize = std::min(OutStringSize-1, InsnStr.size()); 304 std::memcpy(OutString, InsnStr.data(), OutputSize); 305 OutString[OutputSize] = '\0'; // Terminate string. 306 307 return Size; 308 } 309 } 310 llvm_unreachable("Invalid DecodeStatus!"); 311} 312 313// 314// LLVMSetDisasmOptions() sets the disassembler's options. It returns 1 if it 315// can set all the Options and 0 otherwise. 316// 317int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){ 318 if (Options & LLVMDisassembler_Option_UseMarkup){ 319 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR; 320 MCInstPrinter *IP = DC->getIP(); 321 IP->setUseMarkup(1); 322 DC->addOptions(LLVMDisassembler_Option_UseMarkup); 323 Options &= ~LLVMDisassembler_Option_UseMarkup; 324 } 325 if (Options & LLVMDisassembler_Option_PrintImmHex){ 326 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR; 327 MCInstPrinter *IP = DC->getIP(); 328 IP->setPrintImmHex(1); 329 DC->addOptions(LLVMDisassembler_Option_PrintImmHex); 330 Options &= ~LLVMDisassembler_Option_PrintImmHex; 331 } 332 if (Options & LLVMDisassembler_Option_AsmPrinterVariant){ 333 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR; 334 // Try to set up the new instruction printer. 335 const MCAsmInfo *MAI = DC->getAsmInfo(); 336 const MCInstrInfo *MII = DC->getInstrInfo(); 337 const MCRegisterInfo *MRI = DC->getRegisterInfo(); 338 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); 339 int AsmPrinterVariant = MAI->getAssemblerDialect(); 340 AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0; 341 MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter( 342 AsmPrinterVariant, *MAI, *MII, *MRI, *STI); 343 if (IP) { 344 DC->setIP(IP); 345 DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant); 346 Options &= ~LLVMDisassembler_Option_AsmPrinterVariant; 347 } 348 } 349 if (Options & LLVMDisassembler_Option_SetInstrComments) { 350 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR; 351 MCInstPrinter *IP = DC->getIP(); 352 IP->setCommentStream(DC->CommentStream); 353 DC->addOptions(LLVMDisassembler_Option_SetInstrComments); 354 Options &= ~LLVMDisassembler_Option_SetInstrComments; 355 } 356 if (Options & LLVMDisassembler_Option_PrintLatency) { 357 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR; 358 DC->addOptions(LLVMDisassembler_Option_PrintLatency); 359 Options &= ~LLVMDisassembler_Option_PrintLatency; 360 } 361 return (Options == 0); 362} 363