FunctionLoweringInfo.cpp revision 263508 
1//===-- FunctionLoweringInfo.cpp ------------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements routines for translating functions from LLVM IR into
11// Machine IR.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "function-lowering-info"
16#include "llvm/CodeGen/FunctionLoweringInfo.h"
17#include "llvm/ADT/PostOrderIterator.h"
18#include "llvm/CodeGen/Analysis.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineModuleInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/DebugInfo.h"
25#include "llvm/IR/DataLayout.h"
26#include "llvm/IR/DerivedTypes.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/Instructions.h"
29#include "llvm/IR/IntrinsicInst.h"
30#include "llvm/IR/LLVMContext.h"
31#include "llvm/IR/Module.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/MathExtras.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetLowering.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/Target/TargetRegisterInfo.h"
39#include <algorithm>
40using namespace llvm;
41
42/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
43/// PHI nodes or outside of the basic block that defines it, or used by a
44/// switch or atomic instruction, which may expand to multiple basic blocks.
45static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
46  if (I->use_empty()) return false;
47  if (isa<PHINode>(I)) return true;
48  const BasicBlock *BB = I->getParent();
49  for (Value::const_use_iterator UI = I->use_begin(), E = I->use_end();
50        UI != E; ++UI) {
51    const User *U = *UI;
52    if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
53      return true;
54  }
55  return false;
56}
57
58void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf) {
59  const TargetLowering *TLI = TM.getTargetLowering();
60
61  Fn = &fn;
62  MF = &mf;
63  RegInfo = &MF->getRegInfo();
64
65  // Check whether the function can return without sret-demotion.
66  SmallVector<ISD::OutputArg, 4> Outs;
67  GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
68  CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
69                                       Fn->isVarArg(),
70                                       Outs, Fn->getContext());
71
72  // Initialize the mapping of values to registers.  This is only set up for
73  // instruction values that are used outside of the block that defines
74  // them.
75  Function::const_iterator BB = Fn->begin(), EB = Fn->end();
76  for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
77    if (const AllocaInst *AI = dyn_cast<AllocaInst>(I))
78      if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
79        Type *Ty = AI->getAllocatedType();
80        uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
81        unsigned Align =
82          std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
83                   AI->getAlignment());
84
85        TySize *= CUI->getZExtValue();   // Get total allocated size.
86        if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
87
88        // The object may need to be placed onto the stack near the stack
89        // protector if one exists. Determine here if this object is a suitable
90        // candidate. I.e., it would trigger the creation of a stack protector.
91        bool MayNeedSP =
92          (AI->isArrayAllocation() ||
93           (TySize >= 8 && isa<ArrayType>(Ty) &&
94            cast<ArrayType>(Ty)->getElementType()->isIntegerTy(8)));
95        StaticAllocaMap[AI] =
96          MF->getFrameInfo()->CreateStackObject(TySize, Align, false,
97                                                MayNeedSP, AI);
98      }
99
100  for (; BB != EB; ++BB)
101    for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
102         I != E; ++I) {
103      // Mark values used outside their block as exported, by allocating
104      // a virtual register for them.
105      if (isUsedOutsideOfDefiningBlock(I))
106        if (!isa<AllocaInst>(I) ||
107            !StaticAllocaMap.count(cast<AllocaInst>(I)))
108          InitializeRegForValue(I);
109
110      // Collect llvm.dbg.declare information. This is done now instead of
111      // during the initial isel pass through the IR so that it is done
112      // in a predictable order.
113      if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
114        MachineModuleInfo &MMI = MF->getMMI();
115        DIVariable DIVar(DI->getVariable());
116        assert((!DIVar || DIVar.isVariable()) &&
117          "Variable in DbgDeclareInst should be either null or a DIVariable.");
118        if (MMI.hasDebugInfo() &&
119            DIVar &&
120            !DI->getDebugLoc().isUnknown()) {
121          // Don't handle byval struct arguments or VLAs, for example.
122          // Non-byval arguments are handled here (they refer to the stack
123          // temporary alloca at this point).
124          const Value *Address = DI->getAddress();
125          if (Address) {
126            if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
127              Address = BCI->getOperand(0);
128            if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
129              DenseMap<const AllocaInst *, int>::iterator SI =
130                StaticAllocaMap.find(AI);
131              if (SI != StaticAllocaMap.end()) { // Check for VLAs.
132                int FI = SI->second;
133                MMI.setVariableDbgInfo(DI->getVariable(),
134                                       FI, DI->getDebugLoc());
135              }
136            }
137          }
138        }
139      }
140    }
141
142  // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
143  // also creates the initial PHI MachineInstrs, though none of the input
144  // operands are populated.
145  for (BB = Fn->begin(); BB != EB; ++BB) {
146    MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
147    MBBMap[BB] = MBB;
148    MF->push_back(MBB);
149
150    // Transfer the address-taken flag. This is necessary because there could
151    // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
152    // the first one should be marked.
153    if (BB->hasAddressTaken())
154      MBB->setHasAddressTaken();
155
156    // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
157    // appropriate.
158    for (BasicBlock::const_iterator I = BB->begin();
159         const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
160      if (PN->use_empty()) continue;
161
162      // Skip empty types
163      if (PN->getType()->isEmptyTy())
164        continue;
165
166      DebugLoc DL = PN->getDebugLoc();
167      unsigned PHIReg = ValueMap[PN];
168      assert(PHIReg && "PHI node does not have an assigned virtual register!");
169
170      SmallVector<EVT, 4> ValueVTs;
171      ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
172      for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
173        EVT VT = ValueVTs[vti];
174        unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
175        const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
176        for (unsigned i = 0; i != NumRegisters; ++i)
177          BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
178        PHIReg += NumRegisters;
179      }
180    }
181  }
182
183  // Mark landing pad blocks.
184  for (BB = Fn->begin(); BB != EB; ++BB)
185    if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
186      MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
187}
188
189/// clear - Clear out all the function-specific state. This returns this
190/// FunctionLoweringInfo to an empty state, ready to be used for a
191/// different function.
192void FunctionLoweringInfo::clear() {
193  assert(CatchInfoFound.size() == CatchInfoLost.size() &&
194         "Not all catch info was assigned to a landing pad!");
195
196  MBBMap.clear();
197  ValueMap.clear();
198  StaticAllocaMap.clear();
199#ifndef NDEBUG
200  CatchInfoLost.clear();
201  CatchInfoFound.clear();
202#endif
203  LiveOutRegInfo.clear();
204  VisitedBBs.clear();
205  ArgDbgValues.clear();
206  ByValArgFrameIndexMap.clear();
207  RegFixups.clear();
208}
209
210/// CreateReg - Allocate a single virtual register for the given type.
211unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
212  return RegInfo->
213    createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT));
214}
215
216/// CreateRegs - Allocate the appropriate number of virtual registers of
217/// the correctly promoted or expanded types.  Assign these registers
218/// consecutive vreg numbers and return the first assigned number.
219///
220/// In the case that the given value has struct or array type, this function
221/// will assign registers for each member or element.
222///
223unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
224  const TargetLowering *TLI = TM.getTargetLowering();
225
226  SmallVector<EVT, 4> ValueVTs;
227  ComputeValueVTs(*TLI, Ty, ValueVTs);
228
229  unsigned FirstReg = 0;
230  for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
231    EVT ValueVT = ValueVTs[Value];
232    MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
233
234    unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
235    for (unsigned i = 0; i != NumRegs; ++i) {
236      unsigned R = CreateReg(RegisterVT);
237      if (!FirstReg) FirstReg = R;
238    }
239  }
240  return FirstReg;
241}
242
243/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
244/// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
245/// the register's LiveOutInfo is for a smaller bit width, it is extended to
246/// the larger bit width by zero extension. The bit width must be no smaller
247/// than the LiveOutInfo's existing bit width.
248const FunctionLoweringInfo::LiveOutInfo *
249FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
250  if (!LiveOutRegInfo.inBounds(Reg))
251    return NULL;
252
253  LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
254  if (!LOI->IsValid)
255    return NULL;
256
257  if (BitWidth > LOI->KnownZero.getBitWidth()) {
258    LOI->NumSignBits = 1;
259    LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
260    LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
261  }
262
263  return LOI;
264}
265
266/// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
267/// register based on the LiveOutInfo of its operands.
268void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
269  Type *Ty = PN->getType();
270  if (!Ty->isIntegerTy() || Ty->isVectorTy())
271    return;
272
273  const TargetLowering *TLI = TM.getTargetLowering();
274
275  SmallVector<EVT, 1> ValueVTs;
276  ComputeValueVTs(*TLI, Ty, ValueVTs);
277  assert(ValueVTs.size() == 1 &&
278         "PHIs with non-vector integer types should have a single VT.");
279  EVT IntVT = ValueVTs[0];
280
281  if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
282    return;
283  IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
284  unsigned BitWidth = IntVT.getSizeInBits();
285
286  unsigned DestReg = ValueMap[PN];
287  if (!TargetRegisterInfo::isVirtualRegister(DestReg))
288    return;
289  LiveOutRegInfo.grow(DestReg);
290  LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
291
292  Value *V = PN->getIncomingValue(0);
293  if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
294    DestLOI.NumSignBits = 1;
295    APInt Zero(BitWidth, 0);
296    DestLOI.KnownZero = Zero;
297    DestLOI.KnownOne = Zero;
298    return;
299  }
300
301  if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
302    APInt Val = CI->getValue().zextOrTrunc(BitWidth);
303    DestLOI.NumSignBits = Val.getNumSignBits();
304    DestLOI.KnownZero = ~Val;
305    DestLOI.KnownOne = Val;
306  } else {
307    assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
308                                "CopyToReg node was created.");
309    unsigned SrcReg = ValueMap[V];
310    if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
311      DestLOI.IsValid = false;
312      return;
313    }
314    const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
315    if (!SrcLOI) {
316      DestLOI.IsValid = false;
317      return;
318    }
319    DestLOI = *SrcLOI;
320  }
321
322  assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
323         DestLOI.KnownOne.getBitWidth() == BitWidth &&
324         "Masks should have the same bit width as the type.");
325
326  for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
327    Value *V = PN->getIncomingValue(i);
328    if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
329      DestLOI.NumSignBits = 1;
330      APInt Zero(BitWidth, 0);
331      DestLOI.KnownZero = Zero;
332      DestLOI.KnownOne = Zero;
333      return;
334    }
335
336    if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
337      APInt Val = CI->getValue().zextOrTrunc(BitWidth);
338      DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
339      DestLOI.KnownZero &= ~Val;
340      DestLOI.KnownOne &= Val;
341      continue;
342    }
343
344    assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
345                                "its CopyToReg node was created.");
346    unsigned SrcReg = ValueMap[V];
347    if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
348      DestLOI.IsValid = false;
349      return;
350    }
351    const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
352    if (!SrcLOI) {
353      DestLOI.IsValid = false;
354      return;
355    }
356    DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
357    DestLOI.KnownZero &= SrcLOI->KnownZero;
358    DestLOI.KnownOne &= SrcLOI->KnownOne;
359  }
360}
361
362/// setArgumentFrameIndex - Record frame index for the byval
363/// argument. This overrides previous frame index entry for this argument,
364/// if any.
365void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
366                                                 int FI) {
367  ByValArgFrameIndexMap[A] = FI;
368}
369
370/// getArgumentFrameIndex - Get frame index for the byval argument.
371/// If the argument does not have any assigned frame index then 0 is
372/// returned.
373int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
374  DenseMap<const Argument *, int>::iterator I =
375    ByValArgFrameIndexMap.find(A);
376  if (I != ByValArgFrameIndexMap.end())
377    return I->second;
378  DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
379  return 0;
380}
381
382/// ComputeUsesVAFloatArgument - Determine if any floating-point values are
383/// being passed to this variadic function, and set the MachineModuleInfo's
384/// usesVAFloatArgument flag if so. This flag is used to emit an undefined
385/// reference to _fltused on Windows, which will link in MSVCRT's
386/// floating-point support.
387void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
388                                      MachineModuleInfo *MMI)
389{
390  FunctionType *FT = cast<FunctionType>(
391    I.getCalledValue()->getType()->getContainedType(0));
392  if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
393    for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
394      Type* T = I.getArgOperand(i)->getType();
395      for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
396           i != e; ++i) {
397        if (i->isFloatingPointTy()) {
398          MMI->setUsesVAFloatArgument(true);
399          return;
400        }
401      }
402    }
403  }
404}
405
406/// AddCatchInfo - Extract the personality and type infos from an eh.selector
407/// call, and add them to the specified machine basic block.
408void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI,
409                        MachineBasicBlock *MBB) {
410  // Inform the MachineModuleInfo of the personality for this landing pad.
411  const ConstantExpr *CE = cast<ConstantExpr>(I.getArgOperand(1));
412  assert(CE->getOpcode() == Instruction::BitCast &&
413         isa<Function>(CE->getOperand(0)) &&
414         "Personality should be a function");
415  MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
416
417  // Gather all the type infos for this landing pad and pass them along to
418  // MachineModuleInfo.
419  std::vector<const GlobalVariable *> TyInfo;
420  unsigned N = I.getNumArgOperands();
421
422  for (unsigned i = N - 1; i > 1; --i) {
423    if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(i))) {
424      unsigned FilterLength = CI->getZExtValue();
425      unsigned FirstCatch = i + FilterLength + !FilterLength;
426      assert(FirstCatch <= N && "Invalid filter length");
427
428      if (FirstCatch < N) {
429        TyInfo.reserve(N - FirstCatch);
430        for (unsigned j = FirstCatch; j < N; ++j)
431          TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
432        MMI->addCatchTypeInfo(MBB, TyInfo);
433        TyInfo.clear();
434      }
435
436      if (!FilterLength) {
437        // Cleanup.
438        MMI->addCleanup(MBB);
439      } else {
440        // Filter.
441        TyInfo.reserve(FilterLength - 1);
442        for (unsigned j = i + 1; j < FirstCatch; ++j)
443          TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
444        MMI->addFilterTypeInfo(MBB, TyInfo);
445        TyInfo.clear();
446      }
447
448      N = i;
449    }
450  }
451
452  if (N > 2) {
453    TyInfo.reserve(N - 2);
454    for (unsigned j = 2; j < N; ++j)
455      TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
456    MMI->addCatchTypeInfo(MBB, TyInfo);
457  }
458}
459
460/// AddLandingPadInfo - Extract the exception handling information from the
461/// landingpad instruction and add them to the specified machine module info.
462void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
463                             MachineBasicBlock *MBB) {
464  MMI.addPersonality(MBB,
465                     cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
466
467  if (I.isCleanup())
468    MMI.addCleanup(MBB);
469
470  // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
471  //        but we need to do it this way because of how the DWARF EH emitter
472  //        processes the clauses.
473  for (unsigned i = I.getNumClauses(); i != 0; --i) {
474    Value *Val = I.getClause(i - 1);
475    if (I.isCatch(i - 1)) {
476      MMI.addCatchTypeInfo(MBB,
477                           dyn_cast<GlobalVariable>(Val->stripPointerCasts()));
478    } else {
479      // Add filters in a list.
480      Constant *CVal = cast<Constant>(Val);
481      SmallVector<const GlobalVariable*, 4> FilterList;
482      for (User::op_iterator
483             II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
484        FilterList.push_back(cast<GlobalVariable>((*II)->stripPointerCasts()));
485
486      MMI.addFilterTypeInfo(MBB, FilterList);
487    }
488  }
489}
490