Target.td revision 263508
1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/IR/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 25class SubRegIndex<int size, int offset = 0> { 26 string Namespace = ""; 27 28 // Size - Size (in bits) of the sub-registers represented by this index. 29 int Size = size; 30 31 // Offset - Offset of the first bit that is part of this sub-register index. 32 // Set it to -1 if the same index is used to represent sub-registers that can 33 // be at different offsets (for example when using an index to access an 34 // element in a register tuple). 35 int Offset = offset; 36 37 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 38 // This indicates that this SubRegIndex is the result of composing A and B. 39 // See ComposedSubRegIndex. 40 list<SubRegIndex> ComposedOf = []; 41 42 // CoveringSubRegIndices - A list of two or more sub-register indexes that 43 // cover this sub-register. 44 // 45 // This field should normally be left blank as TableGen can infer it. 46 // 47 // TableGen automatically detects sub-registers that straddle the registers 48 // in the SubRegs field of a Register definition. For example: 49 // 50 // Q0 = dsub_0 -> D0, dsub_1 -> D1 51 // Q1 = dsub_0 -> D2, dsub_1 -> D3 52 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 53 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 54 // 55 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given 56 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 57 // CoveringSubRegIndices = [dsub_1, dsub_2]. 58 list<SubRegIndex> CoveringSubRegIndices = []; 59} 60 61// ComposedSubRegIndex - A sub-register that is the result of composing A and B. 62// Offset is set to the sum of A and B's Offsets. Size is set to B's Size. 63class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> 64 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1, 65 !if(!eq(B.Offset, -1), -1, 66 !add(A.Offset, B.Offset)))> { 67 // See SubRegIndex. 68 let ComposedOf = [A, B]; 69} 70 71// RegAltNameIndex - The alternate name set to use for register operands of 72// this register class when printing. 73class RegAltNameIndex { 74 string Namespace = ""; 75} 76def NoRegAltName : RegAltNameIndex; 77 78// Register - You should define one instance of this class for each register 79// in the target machine. String n will become the "name" of the register. 80class Register<string n, list<string> altNames = []> { 81 string Namespace = ""; 82 string AsmName = n; 83 list<string> AltNames = altNames; 84 85 // Aliases - A list of registers that this register overlaps with. A read or 86 // modification of this register can potentially read or modify the aliased 87 // registers. 88 list<Register> Aliases = []; 89 90 // SubRegs - A list of registers that are parts of this register. Note these 91 // are "immediate" sub-registers and the registers within the list do not 92 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 93 // not [AX, AH, AL]. 94 list<Register> SubRegs = []; 95 96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 97 // to address it. Sub-sub-register indices are automatically inherited from 98 // SubRegs. 99 list<SubRegIndex> SubRegIndices = []; 100 101 // RegAltNameIndices - The alternate name indices which are valid for this 102 // register. 103 list<RegAltNameIndex> RegAltNameIndices = []; 104 105 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 106 // These values can be determined by locating the <target>.h file in the 107 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 108 // order of these names correspond to the enumeration used by gcc. A value of 109 // -1 indicates that the gcc number is undefined and -2 that register number 110 // is invalid for this mode/flavour. 111 list<int> DwarfNumbers = []; 112 113 // CostPerUse - Additional cost of instructions using this register compared 114 // to other registers in its class. The register allocator will try to 115 // minimize the number of instructions using a register with a CostPerUse. 116 // This is used by the x86-64 and ARM Thumb targets where some registers 117 // require larger instruction encodings. 118 int CostPerUse = 0; 119 120 // CoveredBySubRegs - When this bit is set, the value of this register is 121 // completely determined by the value of its sub-registers. For example, the 122 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 123 // covered by its sub-register AX. 124 bit CoveredBySubRegs = 0; 125 126 // HWEncoding - The target specific hardware encoding for this register. 127 bits<16> HWEncoding = 0; 128} 129 130// RegisterWithSubRegs - This can be used to define instances of Register which 131// need to specify sub-registers. 132// List "subregs" specifies which registers are sub-registers to this one. This 133// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 134// This allows the code generator to be careful not to put two values with 135// overlapping live ranges into registers which alias. 136class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 137 let SubRegs = subregs; 138} 139 140// DAGOperand - An empty base class that unifies RegisterClass's and other forms 141// of Operand's that are legal as type qualifiers in DAG patterns. This should 142// only ever be used for defining multiclasses that are polymorphic over both 143// RegisterClass's and other Operand's. 144class DAGOperand { } 145 146// RegisterClass - Now that all of the registers are defined, and aliases 147// between registers are defined, specify which registers belong to which 148// register classes. This also defines the default allocation order of 149// registers by register allocators. 150// 151class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 152 dag regList, RegAltNameIndex idx = NoRegAltName> 153 : DAGOperand { 154 string Namespace = namespace; 155 156 // RegType - Specify the list ValueType of the registers in this register 157 // class. Note that all registers in a register class must have the same 158 // ValueTypes. This is a list because some targets permit storing different 159 // types in same register, for example vector values with 128-bit total size, 160 // but different count/size of items, like SSE on x86. 161 // 162 list<ValueType> RegTypes = regTypes; 163 164 // Size - Specify the spill size in bits of the registers. A default value of 165 // zero lets tablgen pick an appropriate size. 166 int Size = 0; 167 168 // Alignment - Specify the alignment required of the registers when they are 169 // stored or loaded to memory. 170 // 171 int Alignment = alignment; 172 173 // CopyCost - This value is used to specify the cost of copying a value 174 // between two registers in this register class. The default value is one 175 // meaning it takes a single instruction to perform the copying. A negative 176 // value means copying is extremely expensive or impossible. 177 int CopyCost = 1; 178 179 // MemberList - Specify which registers are in this class. If the 180 // allocation_order_* method are not specified, this also defines the order of 181 // allocation used by the register allocator. 182 // 183 dag MemberList = regList; 184 185 // AltNameIndex - The alternate register name to use when printing operands 186 // of this register class. Every register in the register class must have 187 // a valid alternate name for the given index. 188 RegAltNameIndex altNameIndex = idx; 189 190 // isAllocatable - Specify that the register class can be used for virtual 191 // registers and register allocation. Some register classes are only used to 192 // model instruction operand constraints, and should have isAllocatable = 0. 193 bit isAllocatable = 1; 194 195 // AltOrders - List of alternative allocation orders. The default order is 196 // MemberList itself, and that is good enough for most targets since the 197 // register allocators automatically remove reserved registers and move 198 // callee-saved registers to the end. 199 list<dag> AltOrders = []; 200 201 // AltOrderSelect - The body of a function that selects the allocation order 202 // to use in a given machine function. The code will be inserted in a 203 // function like this: 204 // 205 // static inline unsigned f(const MachineFunction &MF) { ... } 206 // 207 // The function should return 0 to select the default order defined by 208 // MemberList, 1 to select the first AltOrders entry and so on. 209 code AltOrderSelect = [{}]; 210} 211 212// The memberList in a RegisterClass is a dag of set operations. TableGen 213// evaluates these set operations and expand them into register lists. These 214// are the most common operation, see test/TableGen/SetTheory.td for more 215// examples of what is possible: 216// 217// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 218// register class, or a sub-expression. This is also the way to simply list 219// registers. 220// 221// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 222// 223// (and GPR, CSR) - Set intersection. All registers from the first set that are 224// also in the second set. 225// 226// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 227// numbered registers. Takes an optional 4th operand which is a stride to use 228// when generating the sequence. 229// 230// (shl GPR, 4) - Remove the first N elements. 231// 232// (trunc GPR, 4) - Truncate after the first N elements. 233// 234// (rotl GPR, 1) - Rotate N places to the left. 235// 236// (rotr GPR, 1) - Rotate N places to the right. 237// 238// (decimate GPR, 2) - Pick every N'th element, starting with the first. 239// 240// (interleave A, B, ...) - Interleave the elements from each argument list. 241// 242// All of these operators work on ordered sets, not lists. That means 243// duplicates are removed from sub-expressions. 244 245// Set operators. The rest is defined in TargetSelectionDAG.td. 246def sequence; 247def decimate; 248def interleave; 249 250// RegisterTuples - Automatically generate super-registers by forming tuples of 251// sub-registers. This is useful for modeling register sequence constraints 252// with pseudo-registers that are larger than the architectural registers. 253// 254// The sub-register lists are zipped together: 255// 256// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 257// 258// Generates the same registers as: 259// 260// let SubRegIndices = [sube, subo] in { 261// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 262// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 263// } 264// 265// The generated pseudo-registers inherit super-classes and fields from their 266// first sub-register. Most fields from the Register class are inferred, and 267// the AsmName and Dwarf numbers are cleared. 268// 269// RegisterTuples instances can be used in other set operations to form 270// register classes and so on. This is the only way of using the generated 271// registers. 272class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { 273 // SubRegs - N lists of registers to be zipped up. Super-registers are 274 // synthesized from the first element of each SubRegs list, the second 275 // element and so on. 276 list<dag> SubRegs = Regs; 277 278 // SubRegIndices - N SubRegIndex instances. This provides the names of the 279 // sub-registers in the synthesized super-registers. 280 list<SubRegIndex> SubRegIndices = Indices; 281} 282 283 284//===----------------------------------------------------------------------===// 285// DwarfRegNum - This class provides a mapping of the llvm register enumeration 286// to the register numbering used by gcc and gdb. These values are used by a 287// debug information writer to describe where values may be located during 288// execution. 289class DwarfRegNum<list<int> Numbers> { 290 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 291 // These values can be determined by locating the <target>.h file in the 292 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 293 // order of these names correspond to the enumeration used by gcc. A value of 294 // -1 indicates that the gcc number is undefined and -2 that register number 295 // is invalid for this mode/flavour. 296 list<int> DwarfNumbers = Numbers; 297} 298 299// DwarfRegAlias - This class declares that a given register uses the same dwarf 300// numbers as another one. This is useful for making it clear that the two 301// registers do have the same number. It also lets us build a mapping 302// from dwarf register number to llvm register. 303class DwarfRegAlias<Register reg> { 304 Register DwarfAlias = reg; 305} 306 307//===----------------------------------------------------------------------===// 308// Pull in the common support for scheduling 309// 310include "llvm/Target/TargetSchedule.td" 311 312class Predicate; // Forward def 313 314//===----------------------------------------------------------------------===// 315// Instruction set description - These classes correspond to the C++ classes in 316// the Target/TargetInstrInfo.h file. 317// 318class Instruction { 319 string Namespace = ""; 320 321 dag OutOperandList; // An dag containing the MI def operand list. 322 dag InOperandList; // An dag containing the MI use operand list. 323 string AsmString = ""; // The .s format to print the instruction with. 324 325 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 326 // otherwise, uninitialized. 327 list<dag> Pattern; 328 329 // The follow state will eventually be inferred automatically from the 330 // instruction pattern. 331 332 list<Register> Uses = []; // Default to using no non-operand registers 333 list<Register> Defs = []; // Default to modifying no non-operand registers 334 335 // Predicates - List of predicates which will be turned into isel matching 336 // code. 337 list<Predicate> Predicates = []; 338 339 // Size - Size of encoded instruction, or zero if the size cannot be determined 340 // from the opcode. 341 int Size = 0; 342 343 // DecoderNamespace - The "namespace" in which this instruction exists, on 344 // targets like ARM which multiple ISA namespaces exist. 345 string DecoderNamespace = ""; 346 347 // Code size, for instruction selection. 348 // FIXME: What does this actually mean? 349 int CodeSize = 0; 350 351 // Added complexity passed onto matching pattern. 352 int AddedComplexity = 0; 353 354 // These bits capture information about the high-level semantics of the 355 // instruction. 356 bit isReturn = 0; // Is this instruction a return instruction? 357 bit isBranch = 0; // Is this instruction a branch instruction? 358 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 359 bit isCompare = 0; // Is this instruction a comparison instruction? 360 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 361 bit isBitcast = 0; // Is this instruction a bitcast instruction? 362 bit isSelect = 0; // Is this instruction a select instruction? 363 bit isBarrier = 0; // Can control flow fall through this instruction? 364 bit isCall = 0; // Is this instruction a call instruction? 365 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 366 bit mayLoad = ?; // Is it possible for this inst to read memory? 367 bit mayStore = ?; // Is it possible for this inst to write memory? 368 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 369 bit isCommutable = 0; // Is this 3 operand instruction commutable? 370 bit isTerminator = 0; // Is this part of the terminator for a basic block? 371 bit isReMaterializable = 0; // Is this instruction re-materializable? 372 bit isPredicable = 0; // Is this instruction predicable? 373 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 374 bit usesCustomInserter = 0; // Pseudo instr needing special help. 375 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. 376 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 377 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 378 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 379 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 380 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 381 bit isPseudo = 0; // Is this instruction a pseudo-instruction? 382 // If so, won't have encoding information for 383 // the [MC]CodeEmitter stuff. 384 385 // Side effect flags - When set, the flags have these meanings: 386 // 387 // hasSideEffects - The instruction has side effects that are not 388 // captured by any operands of the instruction or other flags. 389 // 390 // neverHasSideEffects (deprecated) - Set on an instruction with no pattern 391 // if it has no side effects. This is now equivalent to setting 392 // "hasSideEffects = 0". 393 bit hasSideEffects = ?; 394 bit neverHasSideEffects = 0; 395 396 // Is this instruction a "real" instruction (with a distinct machine 397 // encoding), or is it a pseudo instruction used for codegen modeling 398 // purposes. 399 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 400 // instructions can (and often do) still have encoding information 401 // associated with them. Once we've migrated all of them over to true 402 // pseudo-instructions that are lowered to real instructions prior to 403 // the printer/emitter, we can remove this attribute and just use isPseudo. 404 // 405 // The intended use is: 406 // isPseudo: Does not have encoding information and should be expanded, 407 // at the latest, during lowering to MCInst. 408 // 409 // isCodeGenOnly: Does have encoding information and can go through to the 410 // CodeEmitter unchanged, but duplicates a canonical instruction 411 // definition's encoding and should be ignored when constructing the 412 // assembler match tables. 413 bit isCodeGenOnly = 0; 414 415 // Is this instruction a pseudo instruction for use by the assembler parser. 416 bit isAsmParserOnly = 0; 417 418 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 419 420 // Scheduling information from TargetSchedule.td. 421 list<SchedReadWrite> SchedRW; 422 423 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 424 425 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 426 /// be encoded into the output machineinstr. 427 string DisableEncoding = ""; 428 429 string PostEncoderMethod = ""; 430 string DecoderMethod = ""; 431 432 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 433 bits<64> TSFlags = 0; 434 435 ///@name Assembler Parser Support 436 ///@{ 437 438 string AsmMatchConverter = ""; 439 440 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 441 /// two-operand matcher inst-alias for a three operand instruction. 442 /// For example, the arm instruction "add r3, r3, r5" can be written 443 /// as "add r3, r5". The constraint is of the same form as a tied-operand 444 /// constraint. For example, "$Rn = $Rd". 445 string TwoOperandAliasConstraint = ""; 446 447 ///@} 448 449 /// UseNamedOperandTable - If set, the operand indices of this instruction 450 /// can be queried via the getNamedOperandIdx() function which is generated 451 /// by TableGen. 452 bit UseNamedOperandTable = 0; 453} 454 455/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 456/// Which instruction it expands to and how the operands map from the 457/// pseudo. 458class PseudoInstExpansion<dag Result> { 459 dag ResultInst = Result; // The instruction to generate. 460 bit isPseudo = 1; 461} 462 463/// Predicates - These are extra conditionals which are turned into instruction 464/// selector matching code. Currently each predicate is just a string. 465class Predicate<string cond> { 466 string CondString = cond; 467 468 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 469 /// matcher, this is true. Targets should set this by inheriting their 470 /// feature from the AssemblerPredicate class in addition to Predicate. 471 bit AssemblerMatcherPredicate = 0; 472 473 /// AssemblerCondString - Name of the subtarget feature being tested used 474 /// as alternative condition string used for assembler matcher. 475 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". 476 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". 477 /// It can also list multiple features separated by ",". 478 /// e.g. "ModeThumb,FeatureThumb2" is translated to 479 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 480 string AssemblerCondString = ""; 481 482 /// PredicateName - User-level name to use for the predicate. Mainly for use 483 /// in diagnostics such as missing feature errors in the asm matcher. 484 string PredicateName = ""; 485} 486 487/// NoHonorSignDependentRounding - This predicate is true if support for 488/// sign-dependent-rounding is not enabled. 489def NoHonorSignDependentRounding 490 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 491 492class Requires<list<Predicate> preds> { 493 list<Predicate> Predicates = preds; 494} 495 496/// ops definition - This is just a simple marker used to identify the operand 497/// list for an instruction. outs and ins are identical both syntactically and 498/// semanticallyr; they are used to define def operands and use operands to 499/// improve readibility. This should be used like this: 500/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 501def ops; 502def outs; 503def ins; 504 505/// variable_ops definition - Mark this instruction as taking a variable number 506/// of operands. 507def variable_ops; 508 509 510/// PointerLikeRegClass - Values that are designed to have pointer width are 511/// derived from this. TableGen treats the register class as having a symbolic 512/// type that it doesn't know, and resolves the actual regclass to use by using 513/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 514class PointerLikeRegClass<int Kind> { 515 int RegClassKind = Kind; 516} 517 518 519/// ptr_rc definition - Mark this operand as being a pointer value whose 520/// register class is resolved dynamically via a callback to TargetInstrInfo. 521/// FIXME: We should probably change this to a class which contain a list of 522/// flags. But currently we have but one flag. 523def ptr_rc : PointerLikeRegClass<0>; 524 525/// unknown definition - Mark this operand as being of unknown type, causing 526/// it to be resolved by inference in the context it is used. 527class unknown_class; 528def unknown : unknown_class; 529 530/// AsmOperandClass - Representation for the kinds of operands which the target 531/// specific parser can create and the assembly matcher may need to distinguish. 532/// 533/// Operand classes are used to define the order in which instructions are 534/// matched, to ensure that the instruction which gets matched for any 535/// particular list of operands is deterministic. 536/// 537/// The target specific parser must be able to classify a parsed operand into a 538/// unique class which does not partially overlap with any other classes. It can 539/// match a subset of some other class, in which case the super class field 540/// should be defined. 541class AsmOperandClass { 542 /// The name to use for this class, which should be usable as an enum value. 543 string Name = ?; 544 545 /// The super classes of this operand. 546 list<AsmOperandClass> SuperClasses = []; 547 548 /// The name of the method on the target specific operand to call to test 549 /// whether the operand is an instance of this class. If not set, this will 550 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 551 /// signature should be: 552 /// bool isFoo() const; 553 string PredicateMethod = ?; 554 555 /// The name of the method on the target specific operand to call to add the 556 /// target specific operand to an MCInst. If not set, this will default to 557 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 558 /// signature should be: 559 /// void addFooOperands(MCInst &Inst, unsigned N) const; 560 string RenderMethod = ?; 561 562 /// The name of the method on the target specific operand to call to custom 563 /// handle the operand parsing. This is useful when the operands do not relate 564 /// to immediates or registers and are very instruction specific (as flags to 565 /// set in a processor register, coprocessor number, ...). 566 string ParserMethod = ?; 567 568 // The diagnostic type to present when referencing this operand in a 569 // match failure error message. By default, use a generic "invalid operand" 570 // diagnostic. The target AsmParser maps these codes to text. 571 string DiagnosticType = ""; 572} 573 574def ImmAsmOperand : AsmOperandClass { 575 let Name = "Imm"; 576} 577 578/// Operand Types - These provide the built-in operand types that may be used 579/// by a target. Targets can optionally provide their own operand types as 580/// needed, though this should not be needed for RISC targets. 581class Operand<ValueType ty> : DAGOperand { 582 ValueType Type = ty; 583 string PrintMethod = "printOperand"; 584 string EncoderMethod = ""; 585 string DecoderMethod = ""; 586 string AsmOperandLowerMethod = ?; 587 string OperandType = "OPERAND_UNKNOWN"; 588 dag MIOperandInfo = (ops); 589 590 // ParserMatchClass - The "match class" that operands of this type fit 591 // in. Match classes are used to define the order in which instructions are 592 // match, to ensure that which instructions gets matched is deterministic. 593 // 594 // The target specific parser must be able to classify an parsed operand into 595 // a unique class, which does not partially overlap with any other classes. It 596 // can match a subset of some other class, in which case the AsmOperandClass 597 // should declare the other operand as one of its super classes. 598 AsmOperandClass ParserMatchClass = ImmAsmOperand; 599} 600 601class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> 602 : DAGOperand { 603 // RegClass - The register class of the operand. 604 RegisterClass RegClass = regclass; 605 // PrintMethod - The target method to call to print register operands of 606 // this type. The method normally will just use an alt-name index to look 607 // up the name to print. Default to the generic printOperand(). 608 string PrintMethod = pm; 609 // ParserMatchClass - The "match class" that operands of this type fit 610 // in. Match classes are used to define the order in which instructions are 611 // match, to ensure that which instructions gets matched is deterministic. 612 // 613 // The target specific parser must be able to classify an parsed operand into 614 // a unique class, which does not partially overlap with any other classes. It 615 // can match a subset of some other class, in which case the AsmOperandClass 616 // should declare the other operand as one of its super classes. 617 AsmOperandClass ParserMatchClass; 618} 619 620let OperandType = "OPERAND_IMMEDIATE" in { 621def i1imm : Operand<i1>; 622def i8imm : Operand<i8>; 623def i16imm : Operand<i16>; 624def i32imm : Operand<i32>; 625def i64imm : Operand<i64>; 626 627def f32imm : Operand<f32>; 628def f64imm : Operand<f64>; 629} 630 631/// zero_reg definition - Special node to stand for the zero register. 632/// 633def zero_reg; 634 635/// All operands which the MC layer classifies as predicates should inherit from 636/// this class in some manner. This is already handled for the most commonly 637/// used PredicateOperand, but may be useful in other circumstances. 638class PredicateOp; 639 640/// OperandWithDefaultOps - This Operand class can be used as the parent class 641/// for an Operand that needs to be initialized with a default value if 642/// no value is supplied in a pattern. This class can be used to simplify the 643/// pattern definitions for instructions that have target specific flags 644/// encoded as immediate operands. 645class OperandWithDefaultOps<ValueType ty, dag defaultops> 646 : Operand<ty> { 647 dag DefaultOps = defaultops; 648} 649 650/// PredicateOperand - This can be used to define a predicate operand for an 651/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 652/// AlwaysVal specifies the value of this predicate when set to "always 653/// execute". 654class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 655 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp { 656 let MIOperandInfo = OpTypes; 657} 658 659/// OptionalDefOperand - This is used to define a optional definition operand 660/// for an instruction. DefaultOps is the register the operand represents if 661/// none is supplied, e.g. zero_reg. 662class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 663 : OperandWithDefaultOps<ty, defaultops> { 664 let MIOperandInfo = OpTypes; 665} 666 667 668// InstrInfo - This class should only be instantiated once to provide parameters 669// which are global to the target machine. 670// 671class InstrInfo { 672 // Target can specify its instructions in either big or little-endian formats. 673 // For instance, while both Sparc and PowerPC are big-endian platforms, the 674 // Sparc manual specifies its instructions in the format [31..0] (big), while 675 // PowerPC specifies them using the format [0..31] (little). 676 bit isLittleEndianEncoding = 0; 677 678 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset 679 // by default, and TableGen will infer their value from the instruction 680 // pattern when possible. 681 // 682 // Normally, TableGen will issue an error it it can't infer the value of a 683 // property that hasn't been set explicitly. When guessInstructionProperties 684 // is set, it will guess a safe value instead. 685 // 686 // This option is a temporary migration help. It will go away. 687 bit guessInstructionProperties = 1; 688} 689 690// Standard Pseudo Instructions. 691// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 692// Only these instructions are allowed in the TargetOpcode namespace. 693let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in { 694def PHI : Instruction { 695 let OutOperandList = (outs); 696 let InOperandList = (ins variable_ops); 697 let AsmString = "PHINODE"; 698} 699def INLINEASM : Instruction { 700 let OutOperandList = (outs); 701 let InOperandList = (ins variable_ops); 702 let AsmString = ""; 703 let neverHasSideEffects = 1; // Note side effect is encoded in an operand. 704} 705def PROLOG_LABEL : Instruction { 706 let OutOperandList = (outs); 707 let InOperandList = (ins i32imm:$id); 708 let AsmString = ""; 709 let hasCtrlDep = 1; 710 let isNotDuplicable = 1; 711} 712def EH_LABEL : Instruction { 713 let OutOperandList = (outs); 714 let InOperandList = (ins i32imm:$id); 715 let AsmString = ""; 716 let hasCtrlDep = 1; 717 let isNotDuplicable = 1; 718} 719def GC_LABEL : Instruction { 720 let OutOperandList = (outs); 721 let InOperandList = (ins i32imm:$id); 722 let AsmString = ""; 723 let hasCtrlDep = 1; 724 let isNotDuplicable = 1; 725} 726def KILL : Instruction { 727 let OutOperandList = (outs); 728 let InOperandList = (ins variable_ops); 729 let AsmString = ""; 730 let neverHasSideEffects = 1; 731} 732def EXTRACT_SUBREG : Instruction { 733 let OutOperandList = (outs unknown:$dst); 734 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 735 let AsmString = ""; 736 let neverHasSideEffects = 1; 737} 738def INSERT_SUBREG : Instruction { 739 let OutOperandList = (outs unknown:$dst); 740 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 741 let AsmString = ""; 742 let neverHasSideEffects = 1; 743 let Constraints = "$supersrc = $dst"; 744} 745def IMPLICIT_DEF : Instruction { 746 let OutOperandList = (outs unknown:$dst); 747 let InOperandList = (ins); 748 let AsmString = ""; 749 let neverHasSideEffects = 1; 750 let isReMaterializable = 1; 751 let isAsCheapAsAMove = 1; 752} 753def SUBREG_TO_REG : Instruction { 754 let OutOperandList = (outs unknown:$dst); 755 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 756 let AsmString = ""; 757 let neverHasSideEffects = 1; 758} 759def COPY_TO_REGCLASS : Instruction { 760 let OutOperandList = (outs unknown:$dst); 761 let InOperandList = (ins unknown:$src, i32imm:$regclass); 762 let AsmString = ""; 763 let neverHasSideEffects = 1; 764 let isAsCheapAsAMove = 1; 765} 766def DBG_VALUE : Instruction { 767 let OutOperandList = (outs); 768 let InOperandList = (ins variable_ops); 769 let AsmString = "DBG_VALUE"; 770 let neverHasSideEffects = 1; 771} 772def REG_SEQUENCE : Instruction { 773 let OutOperandList = (outs unknown:$dst); 774 let InOperandList = (ins variable_ops); 775 let AsmString = ""; 776 let neverHasSideEffects = 1; 777 let isAsCheapAsAMove = 1; 778} 779def COPY : Instruction { 780 let OutOperandList = (outs unknown:$dst); 781 let InOperandList = (ins unknown:$src); 782 let AsmString = ""; 783 let neverHasSideEffects = 1; 784 let isAsCheapAsAMove = 1; 785} 786def BUNDLE : Instruction { 787 let OutOperandList = (outs); 788 let InOperandList = (ins variable_ops); 789 let AsmString = "BUNDLE"; 790} 791def LIFETIME_START : Instruction { 792 let OutOperandList = (outs); 793 let InOperandList = (ins i32imm:$id); 794 let AsmString = "LIFETIME_START"; 795 let neverHasSideEffects = 1; 796} 797def LIFETIME_END : Instruction { 798 let OutOperandList = (outs); 799 let InOperandList = (ins i32imm:$id); 800 let AsmString = "LIFETIME_END"; 801 let neverHasSideEffects = 1; 802} 803def STACKMAP : Instruction { 804 let OutOperandList = (outs); 805 let InOperandList = (ins i32imm:$id, i32imm:$nbytes, variable_ops); 806 let isCall = 1; 807 let mayLoad = 1; 808} 809def PATCHPOINT : Instruction { 810 let OutOperandList = (outs unknown:$dst); 811 let InOperandList = (ins i32imm:$id, i32imm:$nbytes, unknown:$callee, 812 i32imm:$nargs, i32imm:$cc, variable_ops); 813 let isCall = 1; 814 let mayLoad = 1; 815} 816} 817 818//===----------------------------------------------------------------------===// 819// AsmParser - This class can be implemented by targets that wish to implement 820// .s file parsing. 821// 822// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 823// syntax on X86 for example). 824// 825class AsmParser { 826 // AsmParserClassName - This specifies the suffix to use for the asmparser 827 // class. Generated AsmParser classes are always prefixed with the target 828 // name. 829 string AsmParserClassName = "AsmParser"; 830 831 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 832 // function of the AsmParser class to call on every matched instruction. 833 // This can be used to perform target specific instruction post-processing. 834 string AsmParserInstCleanup = ""; 835 836 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand 837 // written register name matcher 838 bit ShouldEmitMatchRegisterName = 1; 839 840 /// Does the instruction mnemonic allow '.' 841 bit MnemonicContainsDot = 0; 842} 843def DefaultAsmParser : AsmParser; 844 845//===----------------------------------------------------------------------===// 846// AsmParserVariant - Subtargets can have multiple different assembly parsers 847// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 848// implemented by targets to describe such variants. 849// 850class AsmParserVariant { 851 // Variant - AsmParsers can be of multiple different variants. Variants are 852 // used to support targets that need to parser multiple formats for the 853 // assembly language. 854 int Variant = 0; 855 856 // Name - The AsmParser variant name (e.g., AT&T vs Intel). 857 string Name = ""; 858 859 // CommentDelimiter - If given, the delimiter string used to recognize 860 // comments which are hard coded in the .td assembler strings for individual 861 // instructions. 862 string CommentDelimiter = ""; 863 864 // RegisterPrefix - If given, the token prefix which indicates a register 865 // token. This is used by the matcher to automatically recognize hard coded 866 // register tokens as constrained registers, instead of tokens, for the 867 // purposes of matching. 868 string RegisterPrefix = ""; 869} 870def DefaultAsmParserVariant : AsmParserVariant; 871 872/// AssemblerPredicate - This is a Predicate that can be used when the assembler 873/// matches instructions and aliases. 874class AssemblerPredicate<string cond, string name = ""> { 875 bit AssemblerMatcherPredicate = 1; 876 string AssemblerCondString = cond; 877 string PredicateName = name; 878} 879 880/// TokenAlias - This class allows targets to define assembler token 881/// operand aliases. That is, a token literal operand which is equivalent 882/// to another, canonical, token literal. For example, ARM allows: 883/// vmov.u32 s4, #0 -> vmov.i32, #0 884/// 'u32' is a more specific designator for the 32-bit integer type specifier 885/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 886/// def : TokenAlias<".u32", ".i32">; 887/// 888/// This works by marking the match class of 'From' as a subclass of the 889/// match class of 'To'. 890class TokenAlias<string From, string To> { 891 string FromToken = From; 892 string ToToken = To; 893} 894 895/// MnemonicAlias - This class allows targets to define assembler mnemonic 896/// aliases. This should be used when all forms of one mnemonic are accepted 897/// with a different mnemonic. For example, X86 allows: 898/// sal %al, 1 -> shl %al, 1 899/// sal %ax, %cl -> shl %ax, %cl 900/// sal %eax, %cl -> shl %eax, %cl 901/// etc. Though "sal" is accepted with many forms, all of them are directly 902/// translated to a shl, so it can be handled with (in the case of X86, it 903/// actually has one for each suffix as well): 904/// def : MnemonicAlias<"sal", "shl">; 905/// 906/// Mnemonic aliases are mapped before any other translation in the match phase, 907/// and do allow Requires predicates, e.g.: 908/// 909/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 910/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 911/// 912/// Mnemonic aliases can also be constrained to specific variants, e.g.: 913/// 914/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 915/// 916/// If no variant (e.g., "att" or "intel") is specified then the alias is 917/// applied unconditionally. 918class MnemonicAlias<string From, string To, string VariantName = ""> { 919 string FromMnemonic = From; 920 string ToMnemonic = To; 921 string AsmVariantName = VariantName; 922 923 // Predicates - Predicates that must be true for this remapping to happen. 924 list<Predicate> Predicates = []; 925} 926 927/// InstAlias - This defines an alternate assembly syntax that is allowed to 928/// match an instruction that has a different (more canonical) assembly 929/// representation. 930class InstAlias<string Asm, dag Result, bit Emit = 0b1> { 931 string AsmString = Asm; // The .s format to match the instruction with. 932 dag ResultInst = Result; // The MCInst to generate. 933 bit EmitAlias = Emit; // Emit the alias instead of what's aliased. 934 935 // Predicates - Predicates that must be true for this to match. 936 list<Predicate> Predicates = []; 937} 938 939//===----------------------------------------------------------------------===// 940// AsmWriter - This class can be implemented by targets that need to customize 941// the format of the .s file writer. 942// 943// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 944// on X86 for example). 945// 946class AsmWriter { 947 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 948 // class. Generated AsmWriter classes are always prefixed with the target 949 // name. 950 string AsmWriterClassName = "AsmPrinter"; 951 952 // Variant - AsmWriters can be of multiple different variants. Variants are 953 // used to support targets that need to emit assembly code in ways that are 954 // mostly the same for different targets, but have minor differences in 955 // syntax. If the asmstring contains {|} characters in them, this integer 956 // will specify which alternative to use. For example "{x|y|z}" with Variant 957 // == 1, will expand to "y". 958 int Variant = 0; 959 960 961 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar 962 // layout, the asmwriter can actually generate output in this columns (in 963 // verbose-asm mode). These two values indicate the width of the first column 964 // (the "opcode" area) and the width to reserve for subsequent operands. When 965 // verbose asm mode is enabled, operands will be indented to respect this. 966 int FirstOperandColumn = -1; 967 968 // OperandSpacing - Space between operand columns. 969 int OperandSpacing = -1; 970 971 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls 972 // generation of the printInstruction() method. For MC printers, it takes 973 // an MCInstr* operand, otherwise it takes a MachineInstr*. 974 bit isMCAsmWriter = 0; 975} 976def DefaultAsmWriter : AsmWriter; 977 978 979//===----------------------------------------------------------------------===// 980// Target - This class contains the "global" target information 981// 982class Target { 983 // InstructionSet - Instruction set description for this target. 984 InstrInfo InstructionSet; 985 986 // AssemblyParsers - The AsmParser instances available for this target. 987 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 988 989 /// AssemblyParserVariants - The AsmParserVariant instances available for 990 /// this target. 991 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 992 993 // AssemblyWriters - The AsmWriter instances available for this target. 994 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 995} 996 997//===----------------------------------------------------------------------===// 998// SubtargetFeature - A characteristic of the chip set. 999// 1000class SubtargetFeature<string n, string a, string v, string d, 1001 list<SubtargetFeature> i = []> { 1002 // Name - Feature name. Used by command line (-mattr=) to determine the 1003 // appropriate target chip. 1004 // 1005 string Name = n; 1006 1007 // Attribute - Attribute to be set by feature. 1008 // 1009 string Attribute = a; 1010 1011 // Value - Value the attribute to be set to by feature. 1012 // 1013 string Value = v; 1014 1015 // Desc - Feature description. Used by command line (-mattr=) to display help 1016 // information. 1017 // 1018 string Desc = d; 1019 1020 // Implies - Features that this feature implies are present. If one of those 1021 // features isn't set, then this one shouldn't be set either. 1022 // 1023 list<SubtargetFeature> Implies = i; 1024} 1025 1026/// Specifies a Subtarget feature that this instruction is deprecated on. 1027class Deprecated<SubtargetFeature dep> { 1028 SubtargetFeature DeprecatedFeatureMask = dep; 1029} 1030 1031/// A custom predicate used to determine if an instruction is 1032/// deprecated or not. 1033class ComplexDeprecationPredicate<string dep> { 1034 string ComplexDeprecationPredicate = dep; 1035} 1036 1037//===----------------------------------------------------------------------===// 1038// Processor chip sets - These values represent each of the chip sets supported 1039// by the scheduler. Each Processor definition requires corresponding 1040// instruction itineraries. 1041// 1042class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 1043 // Name - Chip set name. Used by command line (-mcpu=) to determine the 1044 // appropriate target chip. 1045 // 1046 string Name = n; 1047 1048 // SchedModel - The machine model for scheduling and instruction cost. 1049 // 1050 SchedMachineModel SchedModel = NoSchedModel; 1051 1052 // ProcItin - The scheduling information for the target processor. 1053 // 1054 ProcessorItineraries ProcItin = pi; 1055 1056 // Features - list of 1057 list<SubtargetFeature> Features = f; 1058} 1059 1060// ProcessorModel allows subtargets to specify the more general 1061// SchedMachineModel instead if a ProcessorItinerary. Subtargets will 1062// gradually move to this newer form. 1063// 1064// Although this class always passes NoItineraries to the Processor 1065// class, the SchedMachineModel may still define valid Itineraries. 1066class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f> 1067 : Processor<n, NoItineraries, f> { 1068 let SchedModel = m; 1069} 1070 1071//===----------------------------------------------------------------------===// 1072// InstrMapping - This class is used to create mapping tables to relate 1073// instructions with each other based on the values specified in RowFields, 1074// ColFields, KeyCol and ValueCols. 1075// 1076class InstrMapping { 1077 // FilterClass - Used to limit search space only to the instructions that 1078 // define the relationship modeled by this InstrMapping record. 1079 string FilterClass; 1080 1081 // RowFields - List of fields/attributes that should be same for all the 1082 // instructions in a row of the relation table. Think of this as a set of 1083 // properties shared by all the instructions related by this relationship 1084 // model and is used to categorize instructions into subgroups. For instance, 1085 // if we want to define a relation that maps 'Add' instruction to its 1086 // predicated forms, we can define RowFields like this: 1087 // 1088 // let RowFields = BaseOp 1089 // All add instruction predicated/non-predicated will have to set their BaseOp 1090 // to the same value. 1091 // 1092 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } 1093 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } 1094 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' } 1095 list<string> RowFields = []; 1096 1097 // List of fields/attributes that are same for all the instructions 1098 // in a column of the relation table. 1099 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged 1100 // based on the 'predSense' values. All the instruction in a specific 1101 // column have the same value and it is fixed for the column according 1102 // to the values set in 'ValueCols'. 1103 list<string> ColFields = []; 1104 1105 // Values for the fields/attributes listed in 'ColFields'. 1106 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction 1107 // that models this relation) should be non-predicated. 1108 // In the example above, 'Add' is the key instruction. 1109 list<string> KeyCol = []; 1110 1111 // List of values for the fields/attributes listed in 'ColFields', one for 1112 // each column in the relation table. 1113 // 1114 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the 1115 // table. First column requires all the instructions to have predSense 1116 // set to 'true' and second column requires it to be 'false'. 1117 list<list<string> > ValueCols = []; 1118} 1119 1120//===----------------------------------------------------------------------===// 1121// Pull in the common support for calling conventions. 1122// 1123include "llvm/Target/TargetCallingConv.td" 1124 1125//===----------------------------------------------------------------------===// 1126// Pull in the common support for DAG isel generation. 1127// 1128include "llvm/Target/TargetSelectionDAG.td" 1129