MCSubtargetInfo.h revision 263508 
1//==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subtarget options of a Target machine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_MC_MCSUBTARGET_H
15#define LLVM_MC_MCSUBTARGET_H
16
17#include "llvm/MC/MCInstrItineraries.h"
18#include "llvm/MC/SubtargetFeature.h"
19#include <string>
20
21namespace llvm {
22
23class StringRef;
24
25//===----------------------------------------------------------------------===//
26///
27/// MCSubtargetInfo - Generic base class for all target subtargets.
28///
29class MCSubtargetInfo {
30  std::string TargetTriple;            // Target triple
31  const SubtargetFeatureKV *ProcFeatures;  // Processor feature list
32  const SubtargetFeatureKV *ProcDesc;  // Processor descriptions
33
34  // Scheduler machine model
35  const SubtargetInfoKV *ProcSchedModels;
36  const MCWriteProcResEntry *WriteProcResTable;
37  const MCWriteLatencyEntry *WriteLatencyTable;
38  const MCReadAdvanceEntry *ReadAdvanceTable;
39  const MCSchedModel *CPUSchedModel;
40
41  const InstrStage *Stages;            // Instruction itinerary stages
42  const unsigned *OperandCycles;       // Itinerary operand cycles
43  const unsigned *ForwardingPaths;     // Forwarding paths
44  unsigned NumFeatures;                // Number of processor features
45  unsigned NumProcs;                   // Number of processors
46  uint64_t FeatureBits;                // Feature bits for current CPU + FS
47
48public:
49  void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
50                           const SubtargetFeatureKV *PF,
51                           const SubtargetFeatureKV *PD,
52                           const SubtargetInfoKV *ProcSched,
53                           const MCWriteProcResEntry *WPR,
54                           const MCWriteLatencyEntry *WL,
55                           const MCReadAdvanceEntry *RA,
56                           const InstrStage *IS,
57                           const unsigned *OC, const unsigned *FP,
58                           unsigned NF, unsigned NP);
59
60  /// getTargetTriple - Return the target triple string.
61  StringRef getTargetTriple() const {
62    return TargetTriple;
63  }
64
65  /// getFeatureBits - Return the feature bits.
66  ///
67  uint64_t getFeatureBits() const {
68    return FeatureBits;
69  }
70
71  /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
72  /// feature string). Recompute feature bits and scheduling model.
73  void InitMCProcessorInfo(StringRef CPU, StringRef FS);
74
75  /// InitCPUSchedModel - Recompute scheduling model based on CPU.
76  void InitCPUSchedModel(StringRef CPU);
77
78  /// ToggleFeature - Toggle a feature and returns the re-computed feature
79  /// bits. This version does not change the implied bits.
80  uint64_t ToggleFeature(uint64_t FB);
81
82  /// ToggleFeature - Toggle a feature and returns the re-computed feature
83  /// bits. This version will also change all implied bits.
84  uint64_t ToggleFeature(StringRef FS);
85
86  /// getSchedModelForCPU - Get the machine model of a CPU.
87  ///
88  const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
89
90  /// getSchedModel - Get the machine model for this subtarget's CPU.
91  ///
92  const MCSchedModel *getSchedModel() const { return CPUSchedModel; }
93
94  /// Return an iterator at the first process resource consumed by the given
95  /// scheduling class.
96  const MCWriteProcResEntry *getWriteProcResBegin(
97    const MCSchedClassDesc *SC) const {
98    return &WriteProcResTable[SC->WriteProcResIdx];
99  }
100  const MCWriteProcResEntry *getWriteProcResEnd(
101    const MCSchedClassDesc *SC) const {
102    return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
103  }
104
105  const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
106                                                  unsigned DefIdx) const {
107    assert(DefIdx < SC->NumWriteLatencyEntries &&
108           "MachineModel does not specify a WriteResource for DefIdx");
109
110    return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
111  }
112
113  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
114                           unsigned WriteResID) const {
115    // TODO: The number of read advance entries in a class can be significant
116    // (~50). Consider compressing the WriteID into a dense ID of those that are
117    // used by ReadAdvance and representing them as a bitset.
118    for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
119           *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
120      if (I->UseIdx < UseIdx)
121        continue;
122      if (I->UseIdx > UseIdx)
123        break;
124      // Find the first WriteResIdx match, which has the highest cycle count.
125      if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
126        return I->Cycles;
127      }
128    }
129    return 0;
130  }
131
132  /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
133  ///
134  InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
135
136  /// Initialize an InstrItineraryData instance.
137  void initInstrItins(InstrItineraryData &InstrItins) const;
138};
139
140} // End llvm namespace
141
142#endif
143