IntrinsicsARM.td revision 263508
1//===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines all of the ARM-specific intrinsics. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// TLS 17 18let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". 19 20def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">, 21 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>; 22 23//===----------------------------------------------------------------------===// 24// Saturating Arithmentic 25 26def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">, 27 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 28 [IntrNoMem, Commutative]>; 29def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">, 30 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 31def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">, 32 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 33def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">, 34 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 35 36//===----------------------------------------------------------------------===// 37// Load, Store and Clear exclusive 38 39def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>; 40def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>; 41def int_arm_clrex : Intrinsic<[]>; 42 43def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, 44 llvm_ptr_ty]>; 45def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>; 46 47//===----------------------------------------------------------------------===// 48// Data barrier instructions 49def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, Intrinsic<[], [llvm_i32_ty]>; 50def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, Intrinsic<[], [llvm_i32_ty]>; 51 52//===----------------------------------------------------------------------===// 53// VFP 54 55def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">, 56 Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; 57def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">, 58 Intrinsic<[], [llvm_i32_ty], []>; 59def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], 60 [IntrNoMem]>; 61def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], 62 [IntrNoMem]>; 63 64//===----------------------------------------------------------------------===// 65// Coprocessor 66 67// Move to coprocessor 68def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">, 69 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 70 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; 71def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">, 72 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 73 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; 74 75// Move from coprocessor 76def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">, 77 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 78 llvm_i32_ty, llvm_i32_ty], []>; 79def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">, 80 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 81 llvm_i32_ty, llvm_i32_ty], []>; 82 83// Coprocessor data processing 84def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">, 85 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 86 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; 87def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">, 88 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 89 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; 90 91// Move from two registers to coprocessor 92def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">, 93 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 94 llvm_i32_ty, llvm_i32_ty], []>; 95def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">, 96 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 97 llvm_i32_ty, llvm_i32_ty], []>; 98 99//===----------------------------------------------------------------------===// 100// CRC32 101 102def int_arm_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 103 [IntrNoMem]>; 104def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 105 [IntrNoMem]>; 106def int_arm_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 107 [IntrNoMem]>; 108def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 109 [IntrNoMem]>; 110def int_arm_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 111 [IntrNoMem]>; 112def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 113 [IntrNoMem]>; 114 115//===----------------------------------------------------------------------===// 116// HINT 117def int_arm_sevl : Intrinsic<[], []>; 118 119//===----------------------------------------------------------------------===// 120// Advanced SIMD (NEON) 121 122// The following classes do not correspond directly to GCC builtins. 123class Neon_1Arg_Intrinsic 124 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; 125class Neon_1Arg_Narrow_Intrinsic 126 : Intrinsic<[llvm_anyvector_ty], 127 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>; 128class Neon_2Arg_Intrinsic 129 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 130 [IntrNoMem]>; 131class Neon_2Arg_Narrow_Intrinsic 132 : Intrinsic<[llvm_anyvector_ty], 133 [LLVMExtendedElementVectorType<0>, 134 LLVMExtendedElementVectorType<0>], 135 [IntrNoMem]>; 136class Neon_2Arg_Long_Intrinsic 137 : Intrinsic<[llvm_anyvector_ty], 138 [LLVMTruncatedElementVectorType<0>, 139 LLVMTruncatedElementVectorType<0>], 140 [IntrNoMem]>; 141class Neon_3Arg_Intrinsic 142 : Intrinsic<[llvm_anyvector_ty], 143 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 144 [IntrNoMem]>; 145class Neon_3Arg_Long_Intrinsic 146 : Intrinsic<[llvm_anyvector_ty], 147 [LLVMMatchType<0>, 148 LLVMTruncatedElementVectorType<0>, 149 LLVMTruncatedElementVectorType<0>], 150 [IntrNoMem]>; 151class Neon_CvtFxToFP_Intrinsic 152 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; 153class Neon_CvtFPToFx_Intrinsic 154 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>; 155class Neon_CvtFPtoInt_1Arg_Intrinsic 156 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; 157 158// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors. 159// Besides the table, VTBL has one other v8i8 argument and VTBX has two. 160// Overall, the classes range from 2 to 6 v8i8 arguments. 161class Neon_Tbl2Arg_Intrinsic 162 : Intrinsic<[llvm_v8i8_ty], 163 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; 164class Neon_Tbl3Arg_Intrinsic 165 : Intrinsic<[llvm_v8i8_ty], 166 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; 167class Neon_Tbl4Arg_Intrinsic 168 : Intrinsic<[llvm_v8i8_ty], 169 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], 170 [IntrNoMem]>; 171class Neon_Tbl5Arg_Intrinsic 172 : Intrinsic<[llvm_v8i8_ty], 173 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, 174 llvm_v8i8_ty], [IntrNoMem]>; 175class Neon_Tbl6Arg_Intrinsic 176 : Intrinsic<[llvm_v8i8_ty], 177 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, 178 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; 179 180// Arithmetic ops 181 182let Properties = [IntrNoMem, Commutative] in { 183 184 // Vector Add. 185 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic; 186 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic; 187 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic; 188 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic; 189 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic; 190 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic; 191 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic; 192 193 // Vector Multiply. 194 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic; 195 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic; 196 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic; 197 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic; 198 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic; 199 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic; 200 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic; 201 202 // Vector Maximum. 203 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic; 204 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic; 205 def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic; 206 207 // Vector Minimum. 208 def int_arm_neon_vmins : Neon_2Arg_Intrinsic; 209 def int_arm_neon_vminu : Neon_2Arg_Intrinsic; 210 def int_arm_neon_vminnm : Neon_2Arg_Intrinsic; 211 212 // Vector Reciprocal Step. 213 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic; 214 215 // Vector Reciprocal Square Root Step. 216 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic; 217} 218 219// Vector Subtract. 220def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic; 221def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic; 222def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic; 223def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic; 224def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic; 225 226// Vector Absolute Compare. 227def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty], 228 [llvm_v2f32_ty, llvm_v2f32_ty], 229 [IntrNoMem]>; 230def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty], 231 [llvm_v4f32_ty, llvm_v4f32_ty], 232 [IntrNoMem]>; 233def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty], 234 [llvm_v2f32_ty, llvm_v2f32_ty], 235 [IntrNoMem]>; 236def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty], 237 [llvm_v4f32_ty, llvm_v4f32_ty], 238 [IntrNoMem]>; 239 240// Vector Absolute Differences. 241def int_arm_neon_vabds : Neon_2Arg_Intrinsic; 242def int_arm_neon_vabdu : Neon_2Arg_Intrinsic; 243 244// Vector Pairwise Add. 245def int_arm_neon_vpadd : Neon_2Arg_Intrinsic; 246 247// Vector Pairwise Add Long. 248// Note: This is different than the other "long" NEON intrinsics because 249// the result vector has half as many elements as the source vector. 250// The source and destination vector types must be specified separately. 251def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], 252 [IntrNoMem]>; 253def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], 254 [IntrNoMem]>; 255 256// Vector Pairwise Add and Accumulate Long. 257// Note: This is similar to vpaddl but the destination vector also appears 258// as the first argument. 259def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty], 260 [LLVMMatchType<0>, llvm_anyvector_ty], 261 [IntrNoMem]>; 262def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty], 263 [LLVMMatchType<0>, llvm_anyvector_ty], 264 [IntrNoMem]>; 265 266// Vector Pairwise Maximum and Minimum. 267def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic; 268def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic; 269def int_arm_neon_vpmins : Neon_2Arg_Intrinsic; 270def int_arm_neon_vpminu : Neon_2Arg_Intrinsic; 271 272// Vector Shifts: 273// 274// The various saturating and rounding vector shift operations need to be 275// represented by intrinsics in LLVM, and even the basic VSHL variable shift 276// operation cannot be safely translated to LLVM's shift operators. VSHL can 277// be used for both left and right shifts, or even combinations of the two, 278// depending on the signs of the shift amounts. It also has well-defined 279// behavior for shift amounts that LLVM leaves undefined. Only basic shifts 280// by constants can be represented with LLVM's shift operators. 281// 282// The shift counts for these intrinsics are always vectors, even for constant 283// shifts, where the constant is replicated. For consistency with VSHL (and 284// other variable shift instructions), left shifts have positive shift counts 285// and right shifts have negative shift counts. This convention is also used 286// for constant right shift intrinsics, and to help preserve sanity, the 287// intrinsic names use "shift" instead of either "shl" or "shr". Where 288// applicable, signed and unsigned versions of the intrinsics are 289// distinguished with "s" and "u" suffixes. A few NEON shift instructions, 290// such as VQSHLU, take signed operands but produce unsigned results; these 291// use a "su" suffix. 292 293// Vector Shift. 294def int_arm_neon_vshifts : Neon_2Arg_Intrinsic; 295def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic; 296def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic; 297def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic; 298def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic; 299 300// Vector Rounding Shift. 301def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic; 302def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic; 303def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic; 304 305// Vector Saturating Shift. 306def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic; 307def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic; 308def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic; 309def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic; 310def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic; 311def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic; 312 313// Vector Saturating Rounding Shift. 314def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic; 315def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic; 316def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic; 317def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic; 318def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic; 319 320// Vector Shift and Insert. 321def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic; 322 323// Vector Absolute Value and Saturating Absolute Value. 324def int_arm_neon_vabs : Neon_1Arg_Intrinsic; 325def int_arm_neon_vqabs : Neon_1Arg_Intrinsic; 326 327// Vector Saturating Negate. 328def int_arm_neon_vqneg : Neon_1Arg_Intrinsic; 329 330// Vector Count Leading Sign/Zero Bits. 331def int_arm_neon_vcls : Neon_1Arg_Intrinsic; 332def int_arm_neon_vclz : Neon_1Arg_Intrinsic; 333 334// Vector Count One Bits. 335def int_arm_neon_vcnt : Neon_1Arg_Intrinsic; 336 337// Vector Reciprocal Estimate. 338def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic; 339 340// Vector Reciprocal Square Root Estimate. 341def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic; 342 343// Vector Conversions Between Floating-point and Integer 344def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic; 345def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic; 346def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic; 347def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic; 348def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic; 349def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic; 350def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic; 351def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic; 352 353// Vector Conversions Between Floating-point and Fixed-point. 354def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic; 355def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic; 356def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic; 357def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic; 358 359// Vector Conversions Between Half-Precision and Single-Precision. 360def int_arm_neon_vcvtfp2hf 361 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>; 362def int_arm_neon_vcvthf2fp 363 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>; 364 365// Narrowing Saturating Vector Moves. 366def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic; 367def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic; 368def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic; 369 370// Vector Table Lookup. 371// The first 1-4 arguments are the table. 372def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic; 373def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic; 374def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic; 375def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic; 376 377// Vector Table Extension. 378// Some elements of the destination vector may not be updated, so the original 379// value of that vector is passed as the first argument. The next 1-4 380// arguments after that are the table. 381def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic; 382def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic; 383def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic; 384def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic; 385 386// Vector Rounding 387def int_arm_neon_vrintn : Neon_1Arg_Intrinsic; 388def int_arm_neon_vrintx : Neon_1Arg_Intrinsic; 389def int_arm_neon_vrinta : Neon_1Arg_Intrinsic; 390def int_arm_neon_vrintz : Neon_1Arg_Intrinsic; 391def int_arm_neon_vrintm : Neon_1Arg_Intrinsic; 392def int_arm_neon_vrintp : Neon_1Arg_Intrinsic; 393 394// De-interleaving vector loads from N-element structures. 395// Source operands are the address and alignment. 396def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty], 397 [llvm_ptr_ty, llvm_i32_ty], 398 [IntrReadArgMem]>; 399def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 400 [llvm_ptr_ty, llvm_i32_ty], 401 [IntrReadArgMem]>; 402def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 403 LLVMMatchType<0>], 404 [llvm_ptr_ty, llvm_i32_ty], 405 [IntrReadArgMem]>; 406def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 407 LLVMMatchType<0>, LLVMMatchType<0>], 408 [llvm_ptr_ty, llvm_i32_ty], 409 [IntrReadArgMem]>; 410 411// Vector load N-element structure to one lane. 412// Source operands are: the address, the N input vectors (since only one 413// lane is assigned), the lane number, and the alignment. 414def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 415 [llvm_ptr_ty, LLVMMatchType<0>, 416 LLVMMatchType<0>, llvm_i32_ty, 417 llvm_i32_ty], [IntrReadArgMem]>; 418def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 419 LLVMMatchType<0>], 420 [llvm_ptr_ty, LLVMMatchType<0>, 421 LLVMMatchType<0>, LLVMMatchType<0>, 422 llvm_i32_ty, llvm_i32_ty], 423 [IntrReadArgMem]>; 424def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 425 LLVMMatchType<0>, LLVMMatchType<0>], 426 [llvm_ptr_ty, LLVMMatchType<0>, 427 LLVMMatchType<0>, LLVMMatchType<0>, 428 LLVMMatchType<0>, llvm_i32_ty, 429 llvm_i32_ty], [IntrReadArgMem]>; 430 431// Interleaving vector stores from N-element structures. 432// Source operands are: the address, the N vectors, and the alignment. 433def int_arm_neon_vst1 : Intrinsic<[], 434 [llvm_ptr_ty, llvm_anyvector_ty, 435 llvm_i32_ty], [IntrReadWriteArgMem]>; 436def int_arm_neon_vst2 : Intrinsic<[], 437 [llvm_ptr_ty, llvm_anyvector_ty, 438 LLVMMatchType<0>, llvm_i32_ty], 439 [IntrReadWriteArgMem]>; 440def int_arm_neon_vst3 : Intrinsic<[], 441 [llvm_ptr_ty, llvm_anyvector_ty, 442 LLVMMatchType<0>, LLVMMatchType<0>, 443 llvm_i32_ty], [IntrReadWriteArgMem]>; 444def int_arm_neon_vst4 : Intrinsic<[], 445 [llvm_ptr_ty, llvm_anyvector_ty, 446 LLVMMatchType<0>, LLVMMatchType<0>, 447 LLVMMatchType<0>, llvm_i32_ty], 448 [IntrReadWriteArgMem]>; 449 450// Vector store N-element structure from one lane. 451// Source operands are: the address, the N vectors, the lane number, and 452// the alignment. 453def int_arm_neon_vst2lane : Intrinsic<[], 454 [llvm_ptr_ty, llvm_anyvector_ty, 455 LLVMMatchType<0>, llvm_i32_ty, 456 llvm_i32_ty], [IntrReadWriteArgMem]>; 457def int_arm_neon_vst3lane : Intrinsic<[], 458 [llvm_ptr_ty, llvm_anyvector_ty, 459 LLVMMatchType<0>, LLVMMatchType<0>, 460 llvm_i32_ty, llvm_i32_ty], 461 [IntrReadWriteArgMem]>; 462def int_arm_neon_vst4lane : Intrinsic<[], 463 [llvm_ptr_ty, llvm_anyvector_ty, 464 LLVMMatchType<0>, LLVMMatchType<0>, 465 LLVMMatchType<0>, llvm_i32_ty, 466 llvm_i32_ty], [IntrReadWriteArgMem]>; 467 468// Vector bitwise select. 469def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty], 470 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 471 [IntrNoMem]>; 472 473 474// Crypto instructions 475def int_arm_neon_aesd : Neon_2Arg_Intrinsic; 476def int_arm_neon_aese : Neon_2Arg_Intrinsic; 477def int_arm_neon_aesimc : Neon_1Arg_Intrinsic; 478def int_arm_neon_aesmc : Neon_1Arg_Intrinsic; 479def int_arm_neon_sha1h : Neon_1Arg_Intrinsic; 480def int_arm_neon_sha1su1 : Neon_2Arg_Intrinsic; 481def int_arm_neon_sha256su0 : Neon_2Arg_Intrinsic; 482def int_arm_neon_sha1c : Neon_3Arg_Intrinsic; 483def int_arm_neon_sha1m : Neon_3Arg_Intrinsic; 484def int_arm_neon_sha1p : Neon_3Arg_Intrinsic; 485def int_arm_neon_sha1su0: Neon_3Arg_Intrinsic; 486def int_arm_neon_sha256h: Neon_3Arg_Intrinsic; 487def int_arm_neon_sha256h2: Neon_3Arg_Intrinsic; 488def int_arm_neon_sha256su1: Neon_3Arg_Intrinsic; 489 490} // end TargetPrefix 491